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Preliminary banking in Raiden DX, not worth

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This commit is contained in:
Angelo Salese 2011-01-02 22:37:48 +00:00
parent 188401b226
commit bc563f265b
2 changed files with 34 additions and 5 deletions
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33
src/mame/drivers/raiden2.c
View File

@ -304,7 +304,7 @@ WRITE16_MEMBER(raiden2_state::cop_dma_trigger_w)
for (i=address;i<address+length;i+=4) for (i=address;i<address+length;i+=4)
{ {
space.write_dword(i, (cop_dma_v1) | (cop_dma_v2 << 16)); //TODO: fill value space.write_dword(i, (cop_dma_v1) | (cop_dma_v2 << 16));
} }
} }
} }
@ -466,7 +466,7 @@ WRITE16_MEMBER(raiden2_state::cop_cmd_w)
// raidndx only // raidndx only
case 0x7e05: case 0x7e05:
space.write_dword(0x470, (space.read_dword(cop_regs[4]) & 0x30) << 10); space.write_dword(0x470, (space.read_dword(cop_regs[4]) & 0x30) << 6);
// Actually, wherever the bank selection actually is // Actually, wherever the bank selection actually is
// And probably 8 bytes too, but they zero all the rest // And probably 8 bytes too, but they zero all the rest
break; break;
@ -649,8 +649,15 @@ WRITE16_MEMBER(raiden2_state::tile_bank_01_w)
} }
} }
READ16_MEMBER(raiden2_state::cop_tile_bank_2_r)
{
return cop_bank;
}
WRITE16_MEMBER(raiden2_state::cop_tile_bank_2_w) WRITE16_MEMBER(raiden2_state::cop_tile_bank_2_w)
{ {
COMBINE_DATA(&cop_bank);
if(ACCESSING_BITS_8_15) { if(ACCESSING_BITS_8_15) {
int new_bank = 4 | (data >> 14); int new_bank = 4 | (data >> 14);
if(new_bank != fg_bank) { if(new_bank != fg_bank) {
@ -660,6 +667,25 @@ WRITE16_MEMBER(raiden2_state::cop_tile_bank_2_w)
} }
} }
WRITE16_MEMBER(raiden2_state::raidendx_cop_bank_2_w)
{
COMBINE_DATA(&cop_bank);
if(ACCESSING_BITS_8_15) {
int new_bank = 4 | ((cop_bank >> 10) & 3);
if(new_bank != fg_bank) {
fg_bank = new_bank;
tilemap_mark_all_tiles_dirty(foreground_layer);
}
/* probably bit 3 is from 6c9 */
/* TODO: this doesn't work! */
memory_set_bank(space.machine, "mainbank", 8 | (cop_bank & 0x7000) >> 12);
}
}
/* TILEMAP RELATED (move to video file) */ /* TILEMAP RELATED (move to video file) */
static TILE_GET_INFO( get_back_tile_info ) static TILE_GET_INFO( get_back_tile_info )
@ -1005,7 +1031,7 @@ static ADDRESS_MAP_START( raiden2_cop_mem, ADDRESS_SPACE_PROGRAM, 16, raiden2_st
AM_RANGE(0x0043a, 0x0043b) AM_WRITE(cop_pgm_mask_w) AM_RANGE(0x0043a, 0x0043b) AM_WRITE(cop_pgm_mask_w)
AM_RANGE(0x0043c, 0x0043d) AM_WRITE(cop_pgm_trigger_w) AM_RANGE(0x0043c, 0x0043d) AM_WRITE(cop_pgm_trigger_w)
AM_RANGE(0x00444, 0x00445) AM_WRITE(cop_scale_w) AM_RANGE(0x00444, 0x00445) AM_WRITE(cop_scale_w)
AM_RANGE(0x00470, 0x00471) AM_READNOP AM_WRITE(cop_tile_bank_2_w) AM_RANGE(0x00470, 0x00471) AM_READWRITE(cop_tile_bank_2_r,cop_tile_bank_2_w)
AM_RANGE(0x00476, 0x00477) AM_WRITE(cop_dma_adr_rel_w) AM_RANGE(0x00476, 0x00477) AM_WRITE(cop_dma_adr_rel_w)
AM_RANGE(0x00478, 0x00479) AM_WRITE(cop_dma_src_w) AM_RANGE(0x00478, 0x00479) AM_WRITE(cop_dma_src_w)
@ -1070,6 +1096,7 @@ static ADDRESS_MAP_START( raiden2_mem, ADDRESS_SPACE_PROGRAM, 16, raiden2_state
ADDRESS_MAP_END ADDRESS_MAP_END
static ADDRESS_MAP_START( raidendx_mem, ADDRESS_SPACE_PROGRAM, 16, raiden2_state ) static ADDRESS_MAP_START( raidendx_mem, ADDRESS_SPACE_PROGRAM, 16, raiden2_state )
AM_RANGE(0x00470, 0x00471) AM_READWRITE(cop_tile_bank_2_r,raidendx_cop_bank_2_w)
AM_RANGE(0x004d0, 0x004d7) AM_RAM //??? AM_RANGE(0x004d0, 0x004d7) AM_RAM //???
AM_RANGE(0x0062c, 0x0062d) AM_WRITE(tilemap_enable_w) AM_RANGE(0x0062c, 0x0062d) AM_WRITE(tilemap_enable_w)
AM_RANGE(0x00610, 0x0061b) AM_WRITE(tile_scroll_w) AM_RANGE(0x00610, 0x0061b) AM_WRITE(tile_scroll_w)

4
src/mame/includes/raiden2.h
View File

@ -36,7 +36,9 @@ public:
DECLARE_WRITE16_MEMBER ( cop_dma_trigger_w ); DECLARE_WRITE16_MEMBER ( cop_dma_trigger_w );
DECLARE_WRITE16_MEMBER ( raiden2_bank_w ); DECLARE_WRITE16_MEMBER ( raiden2_bank_w );
DECLARE_READ16_MEMBER ( cop_tile_bank_2_r );
DECLARE_WRITE16_MEMBER ( cop_tile_bank_2_w ); DECLARE_WRITE16_MEMBER ( cop_tile_bank_2_w );
DECLARE_WRITE16_MEMBER ( raidendx_cop_bank_2_w );
DECLARE_WRITE16_MEMBER ( tilemap_enable_w ); DECLARE_WRITE16_MEMBER ( tilemap_enable_w );
DECLARE_WRITE16_MEMBER ( tile_scroll_w ); DECLARE_WRITE16_MEMBER ( tile_scroll_w );
DECLARE_WRITE16_MEMBER ( tile_bank_01_w ); DECLARE_WRITE16_MEMBER ( tile_bank_01_w );
@ -69,7 +71,6 @@ public:
DECLARE_WRITE16_MEMBER( test_w ); DECLARE_WRITE16_MEMBER( test_w );
void common_reset(); void common_reset();
tilemap_t *background_layer,*midground_layer,*foreground_layer,*text_layer; tilemap_t *background_layer,*midground_layer,*foreground_layer,*text_layer;
@ -77,6 +78,7 @@ public:
int bg_bank, fg_bank, mid_bank; int bg_bank, fg_bank, mid_bank;
UINT16 raiden2_tilemap_enable; UINT16 raiden2_tilemap_enable;
UINT8 prg_bank; UINT8 prg_bank;
UINT16 cop_bank;
UINT16 scrollvals[6]; UINT16 scrollvals[6];
UINT32 cop_regs[8], cop_itoa; UINT32 cop_regs[8], cop_itoa;