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https://github.com/holub/mame
synced 2025-04-24 09:20:02 +03:00
Stash jump target address before executing delay slot.
Also, don't update link register until delay slot has finished executing. Fixes hang in gauntleg, though there are math problems lurking still.
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@ -169,6 +169,7 @@ struct _mips3imp_state
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/* internal stuff */
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UINT8 cache_dirty; /* true if we need to flush the cache */
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UINT32 jmpdest; /* destination jump target */
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/* parameters for subroutines */
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UINT64 numcycles; /* return value from gettotalcycles */
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@ -1633,15 +1634,19 @@ static void generate_delay_slot_and_branch(drcuml_block *block, compiler_state *
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{
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compiler_state compiler_temp = *compiler;
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UINT32 op = *desc->opptr.l;
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/* set the link if needed */
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if (linkreg != 0)
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UML_DMOV(block, R64(linkreg), IMM((INT32)(desc->pc + 8))); // dmov <linkreg>,desc->pc + 8
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/* fetch the target register if dynamic, in case it is modified by the delay slot */
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if (desc->targetpc == BRANCH_TARGET_DYNAMIC)
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UML_MOV(block, MEM(&mips3->impstate->jmpdest), R32(RSREG)); // mov [jmpdest],<rsreg>
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/* compile the delay slot using temporary compiler state */
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assert(desc->delay != NULL);
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generate_sequence_instruction(block, &compiler_temp, desc->delay); // <next instruction>
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/* set the link if needed -- after the delay slot */
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if (linkreg != 0)
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UML_DMOV(block, R64(linkreg), IMM((INT32)(desc->pc + 8))); // dmov <linkreg>,desc->pc + 8
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/* update the cycles and jump through the hash table to the target */
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if (desc->targetpc != BRANCH_TARGET_DYNAMIC)
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{
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@ -1654,9 +1659,9 @@ static void generate_delay_slot_and_branch(drcuml_block *block, compiler_state *
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}
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else
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{
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generate_update_cycles(block, &compiler_temp, R32(RSREG), TRUE);
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generate_update_cycles(block, &compiler_temp, MEM(&mips3->impstate->jmpdest), TRUE);
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// <subtract cycles>
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UML_HASHJMP(block, IMM(mips3->impstate->mode), R32(RSREG), mips3->impstate->nocode);
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UML_HASHJMP(block, IMM(mips3->impstate->mode), MEM(&mips3->impstate->jmpdest), mips3->impstate->nocode);
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// hashjmp <mode>,<rsreg>,nocode
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}
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