snes.c: temporarily reverted some dma code to allow S-DD1 games to boot again in MESS [Fabio Priuli]
This commit is contained in:
Fabio Priuli
parent
a66c05e720
commit
bd07cb544c
@ -203,7 +203,7 @@ static TIMER_CALLBACK( snes_scanline_tick )
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timer_adjust_oneshot(state->scanline_timer, attotime_never, 0);
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timer_adjust_oneshot(state->hblank_timer, video_screen_get_time_until_pos(machine->primary_screen, snes_ppu.beam.current_vert, state->hblank_offset * state->htmult), 0);
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// printf("%02x %d\n",snes_ram[HVBJOY],snes_ppu.beam.current_vert);
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// printf("%02x %d\n",snes_ram[HVBJOY],snes_ppu.beam.current_vert);
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}
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/* This is called at the start of hblank *before* the scanline indicated in current_vert! */
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@ -418,40 +418,40 @@ READ8_HANDLER( snes_r_io )
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return state->joy4h;
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case DMAP0: case DMAP1: case DMAP2: case DMAP3: /*0x43n0*/
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case DMAP4: case DMAP5: case DMAP6: case DMAP7:
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return state->dma_channel[(offset & 0x70) >> 4].dmap;
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return state->dma_channel[(offset >> 4) & 0x07].dmap;
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case BBAD0: case BBAD1: case BBAD2: case BBAD3: /*0x43n1*/
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case BBAD4: case BBAD5: case BBAD6: case BBAD7:
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return state->dma_channel[(offset & 0x70) >> 4].dest_addr;
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return state->dma_channel[(offset >> 4) & 0x07].dest_addr;
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case A1T0L: case A1T1L: case A1T2L: case A1T3L: /*0x43n2*/
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case A1T4L: case A1T5L: case A1T6L: case A1T7L:
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return state->dma_channel[(offset & 0x70) >> 4].src_addr & 0xff;
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return state->dma_channel[(offset >> 4) & 0x07].src_addr & 0xff;
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case A1T0H: case A1T1H: case A1T2H: case A1T3H: /*0x43n3*/
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case A1T4H: case A1T5H: case A1T6H: case A1T7H:
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return (state->dma_channel[(offset & 0x70) >> 4].src_addr >> 8) & 0xff;
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return (state->dma_channel[(offset >> 4) & 0x07].src_addr >> 8) & 0xff;
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case A1B0: case A1B1: case A1B2: case A1B3: /*0x43n4*/
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case A1B4: case A1B5: case A1B6: case A1B7:
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return state->dma_channel[(offset & 0x70) >> 4].bank;
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return state->dma_channel[(offset >> 4) & 0x07].bank;
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case DAS0L: case DAS1L: case DAS2L: case DAS3L: /*0x43n5*/
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case DAS4L: case DAS5L: case DAS6L: case DAS7L:
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return state->dma_channel[(offset & 0x70) >> 4].trans_size & 0xff;
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return state->dma_channel[(offset >> 4) & 0x07].trans_size & 0xff;
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case DAS0H: case DAS1H: case DAS2H: case DAS3H: /*0x43n6*/
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case DAS4H: case DAS5H: case DAS6H: case DAS7H:
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return (state->dma_channel[(offset & 0x70) >> 4].trans_size >> 8) & 0xff;
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return (state->dma_channel[(offset >> 4) & 0x07].trans_size >> 8) & 0xff;
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case DSAB0: case DSAB1: case DSAB2: case DSAB3: /*0x43n7*/
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case DSAB4: case DSAB5: case DSAB6: case DSAB7:
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return state->dma_channel[(offset & 0x70) >> 4].ibank;
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return state->dma_channel[(offset >> 4) & 0x07].ibank;
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case A2A0L: case A2A1L: case A2A2L: case A2A3L: /*0x43n8*/
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case A2A4L: case A2A5L: case A2A6L: case A2A7L:
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return state->dma_channel[(offset & 0x70) >> 4].hdma_addr & 0xff;
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return state->dma_channel[(offset >> 4) & 0x07].hdma_addr & 0xff;
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case A2A0H: case A2A1H: case A2A2H: case A2A3H: /*0x43n9*/
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case A2A4H: case A2A5H: case A2A6H: case A2A7H:
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return (state->dma_channel[(offset & 0x70) >> 4].hdma_addr >> 8) & 0xff;
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return (state->dma_channel[(offset >> 4) & 0x07].hdma_addr >> 8) & 0xff;
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case NTRL0: case NTRL1: case NTRL2: case NTRL3: /*0x43na*/
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case NTRL4: case NTRL5: case NTRL6: case NTRL7:
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return state->dma_channel[(offset & 0x70) >> 4].hdma_line_counter;
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return state->dma_channel[(offset >> 4) & 0x07].hdma_line_counter;
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case 0x430b: case 0x431b: case 0x432b: case 0x433b: /* according to bsnes, this does not return open_bus (even if its precise effect is unknown) */
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case 0x434b: case 0x435b: case 0x436b: case 0x437b:
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return state->dma_channel[(offset & 0x70) >> 4].unk;
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return state->dma_channel[(offset >> 4) & 0x07].unk;
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#ifndef MESS
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case 0x4100: /* NSS Dip-Switches */
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@ -677,51 +677,51 @@ WRITE8_HANDLER( snes_w_io )
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/* Below is all DMA related */
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case DMAP0: case DMAP1: case DMAP2: case DMAP3: /*0x43n0*/
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case DMAP4: case DMAP5: case DMAP6: case DMAP7:
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state->dma_channel[(offset & 0x70) >> 4].dmap = data;
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state->dma_channel[(offset >> 4) & 0x07].dmap = data;
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break;
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case BBAD0: case BBAD1: case BBAD2: case BBAD3: /*0x43n1*/
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case BBAD4: case BBAD5: case BBAD6: case BBAD7:
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state->dma_channel[(offset & 0x70) >> 4].dest_addr = data;
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state->dma_channel[(offset >> 4) & 0x07].dest_addr = data;
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break;
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case A1T0L: case A1T1L: case A1T2L: case A1T3L: /*0x43n2*/
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case A1T4L: case A1T5L: case A1T6L: case A1T7L:
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state->dma_channel[(offset & 0x70) >> 4].src_addr = (state->dma_channel[(offset & 0x70) >> 4].src_addr & 0xff00) | (data << 0);
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state->dma_channel[(offset >> 4) & 0x07].src_addr = (state->dma_channel[(offset >> 4) & 0x07].src_addr & 0xff00) | (data << 0);
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break;
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case A1T0H: case A1T1H: case A1T2H: case A1T3H: /*0x43n3*/
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case A1T4H: case A1T5H: case A1T6H: case A1T7H:
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state->dma_channel[(offset & 0x70) >> 4].src_addr = (state->dma_channel[(offset & 0x70) >> 4].src_addr & 0x00ff) | (data << 8);
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state->dma_channel[(offset >> 4) & 0x07].src_addr = (state->dma_channel[(offset >> 4) & 0x07].src_addr & 0x00ff) | (data << 8);
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break;
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case A1B0: case A1B1: case A1B2: case A1B3: /*0x43n4*/
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case A1B4: case A1B5: case A1B6: case A1B7:
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state->dma_channel[(offset & 0x70) >> 4].bank = data;
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state->dma_channel[(offset >> 4) & 0x07].bank = data;
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break;
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case DAS0L: case DAS1L: case DAS2L: case DAS3L: /*0x43n5*/
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case DAS4L: case DAS5L: case DAS6L: case DAS7L:
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state->dma_channel[(offset & 0x70) >> 4].trans_size = (state->dma_channel[(offset & 0x70) >> 4].trans_size & 0xff00) | (data << 0);
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state->dma_channel[(offset >> 4) & 0x07].trans_size = (state->dma_channel[(offset >> 4) & 0x07].trans_size & 0xff00) | (data << 0);
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break;
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case DAS0H: case DAS1H: case DAS2H: case DAS3H: /*0x43n6*/
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case DAS4H: case DAS5H: case DAS6H: case DAS7H:
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state->dma_channel[(offset & 0x70) >> 4].trans_size = (state->dma_channel[(offset & 0x70) >> 4].trans_size & 0x00ff) | (data << 8);
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state->dma_channel[(offset >> 4) & 0x07].trans_size = (state->dma_channel[(offset >> 4) & 0x07].trans_size & 0x00ff) | (data << 8);
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break;
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case DSAB0: case DSAB1: case DSAB2: case DSAB3: /*0x43n7*/
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case DSAB4: case DSAB5: case DSAB6: case DSAB7:
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state->dma_channel[(offset & 0x70) >> 4].ibank = data;
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state->dma_channel[(offset >> 4) & 0x07].ibank = data;
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break;
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case A2A0L: case A2A1L: case A2A2L: case A2A3L: /*0x43n8*/
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case A2A4L: case A2A5L: case A2A6L: case A2A7L:
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state->dma_channel[(offset & 0x70) >> 4].hdma_addr = (state->dma_channel[(offset & 0x70) >> 4].hdma_addr & 0xff00) | (data << 0);
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state->dma_channel[(offset >> 4) & 0x07].hdma_addr = (state->dma_channel[(offset >> 4) & 0x07].hdma_addr & 0xff00) | (data << 0);
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break;
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case A2A0H: case A2A1H: case A2A2H: case A2A3H: /*0x43n9*/
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case A2A4H: case A2A5H: case A2A6H: case A2A7H:
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state->dma_channel[(offset & 0x70) >> 4].hdma_addr = (state->dma_channel[(offset & 0x70) >> 4].hdma_addr & 0x00ff) | (data << 8);
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state->dma_channel[(offset >> 4) & 0x07].hdma_addr = (state->dma_channel[(offset >> 4) & 0x07].hdma_addr & 0x00ff) | (data << 8);
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break;
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case NTRL0: case NTRL1: case NTRL2: case NTRL3: /*0x43na*/
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case NTRL4: case NTRL5: case NTRL6: case NTRL7:
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state->dma_channel[(offset & 0x70) >> 4].hdma_line_counter = data;
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state->dma_channel[(offset >> 4) & 0x07].hdma_line_counter = data;
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break;
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case 0x430b: case 0x431b: case 0x432b: case 0x433b:
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case 0x434b: case 0x435b: case 0x436b: case 0x437b:
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state->dma_channel[(offset & 0x70) >> 4].unk = data;
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state->dma_channel[(offset >> 4) & 0x07].unk = data;
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break;
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}
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@ -1933,8 +1933,8 @@ static void snes_hdma_update( const address_space *space, int dma )
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if (state->dma_channel[dma].dmap & 0x40)
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{
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/* One oddity: if $43xA is 0 and this is the last active HDMA channel for this scanline, only load
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one byte for Address, and use the $00 for the low byte. So Address ends up incremented one less than
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otherwise expected */
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one byte for Address, and use the $00 for the low byte. So Address ends up incremented one less than
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otherwise expected */
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abus = snes_get_hdma_addr(space->machine, dma);
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state->dma_channel[dma].trans_size = snes_abus_read(space, abus) << 8;
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@ -2058,9 +2058,10 @@ static void snes_dma( const address_space *space, UINT8 channels )
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int i;
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INT8 increment;
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UINT16 bbus;
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UINT32 abus, abus_bank, length;
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UINT32 abus, abus_bank;
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UINT16 length;
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/* FIXME: we also need to round to the nearest 8 master cycles */
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/* FIXME: we also need to round to the nearest 8 master cycles */
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/* overhead steals 8 master cycles, correct? */
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cpu_adjust_icount(space->cpu,-8);
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@ -2071,111 +2072,114 @@ static void snes_dma( const address_space *space, UINT8 channels )
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if (BIT(channels, i))
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{
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/* FIXME: the following should be used to stop DMA if the same channel is used by HDMA (being set to 1 in snes_hdma)
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However, this cannot be implemented as is atm, because currently DMA transfers always happen as soon as they are enabled... */
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However, this cannot be implemented as is atm, because currently DMA transfers always happen as soon as they are enabled... */
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state->dma_channel[i].dma_disabled = 0;
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//printf( "Making a transfer on channel %d\n", i );
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/* Find transfer addresses */
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abus = state->dma_channel[i].src_addr;
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abus_bank = state->dma_channel[i].bank << 16;
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bbus = state->dma_channel[i].dest_addr + 0x2100;
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abus = (snes_ram[SNES_DMA_BASE + (i * 0x10) + 3] << 8) + snes_ram[SNES_DMA_BASE + (i * 0x10) + 2];
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abus_bank = (snes_ram[SNES_DMA_BASE + (i * 0x10) + 4] << 16);
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bbus = 0x2100 + snes_ram[SNES_DMA_BASE + (i * 0x10) + 1];
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//printf("Address: %06x\n", abus | abus_bank);
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//printf( "Address: %06x\n", abus | abus_bank );
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/* Auto increment */
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if (state->dma_channel[i].dmap & 0x8)
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if (snes_ram[SNES_DMA_BASE + (i * 0x10)] & 0x8)
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{
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increment = 0;
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}
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else
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{
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if (state->dma_channel[i].dmap & 0x10)
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if (snes_ram[SNES_DMA_BASE + (i * 0x10)] & 0x10)
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increment = -1;
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else
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increment = 1;
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}
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/* Number of bytes to transfer */
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length = state->dma_channel[i].trans_size;
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if (!length)
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length = 0x10000; /* 0x0000 really means 0x10000 */
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length = (snes_ram[SNES_DMA_BASE + (i * 0x10) + 6] << 8) + snes_ram[SNES_DMA_BASE + (i * 0x10) + 5];
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// printf( "DMA-Ch %d: len: %X, abus: %X, bbus: %X, incr: %d, dir: %s, type: %d\n", i, length, abus | abus_bank, bbus, increment, state->dma_channel[i].dmap & 0x80 ? "PPU->CPU" : "CPU->PPU", state->dma_channel[i].dmap & 0x07);
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// printf( "DMA-Ch %d: len: %X, abus: %X, bbus: %X, incr: %d, dir: %s, type: %d\n", i, length, abus, bbus, increment, snes_ram[SNES_DMA_BASE + (i * 0x10)] & 0x80 ? "PPU->CPU" : "CPU->PPU", snes_ram[SNES_DMA_BASE + (i * 0x10)] & 0x07);
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#ifdef SNES_DBG_DMA
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mame_printf_debug( "DMA-Ch %d: len: %X, abus: %X, bbus: %X, incr: %d, dir: %s, type: %d\n", i, length, abus | abus_bank, bbus, increment, state->dma_channel[i].dmap & 0x80 ? "PPU->CPU" : "CPU->PPU", state->dma_channel[i].dmap & 0x07);
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mame_printf_debug( "DMA-Ch %d: len: %X, abus: %X, bbus: %X, incr: %d, dir: %s, type: %d\n", i, length, abus, bbus, increment, snes_ram[SNES_DMA_BASE + (i * 0x10)] & 0x80 ? "PPU->CPU" : "CPU->PPU", snes_ram[SNES_DMA_BASE + (i * 0x10)] & 0x07);
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#endif
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switch (state->dma_channel[i].dmap & 0x07)
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switch (snes_ram[SNES_DMA_BASE + (i * 0x10)] & 0x07)
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{
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case 0: /* 1 register write once */
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case 2: /* 1 register write twice */
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case 6: /* 1 register write twice */
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while (length-- && !state->dma_channel[i].dma_disabled)
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{
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snes_dma_transfer(space, i, (abus & 0xffff) | abus_bank, bbus);
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abus += increment;
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}
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break;
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case 1: /* 2 registers write once */
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case 5: /* 2 registers write twice alternate */
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while (length-- && !state->dma_channel[i].dma_disabled)
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{
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snes_dma_transfer(space, i, (abus & 0xffff) | abus_bank, bbus);
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abus += increment;
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if (!(length--) || state->dma_channel[i].dma_disabled)
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break;
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snes_dma_transfer(space, i, (abus & 0xffff) | abus_bank, bbus + 1);
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abus += increment;
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}
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break;
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case 3: /* 2 registers write twice each */
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case 7: /* 2 registers write twice each */
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while (length-- && !state->dma_channel[i].dma_disabled)
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{
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snes_dma_transfer(space, i, (abus & 0xffff) | abus_bank, bbus);
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abus += increment;
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if (!(length--) || state->dma_channel[i].dma_disabled)
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break;
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snes_dma_transfer(space, i, (abus & 0xffff) | abus_bank, bbus);
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abus += increment;
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if (!(length--) || state->dma_channel[i].dma_disabled)
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break;
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snes_dma_transfer(space, i, (abus & 0xffff) | abus_bank, bbus + 1);
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abus += increment;
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if (!(length--) || state->dma_channel[i].dma_disabled)
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break;
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snes_dma_transfer(space, i, (abus & 0xffff) | abus_bank, bbus + 1);
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abus += increment;
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}
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break;
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case 4: /* 4 registers write once */
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while (length-- && !state->dma_channel[i].dma_disabled)
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{
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snes_dma_transfer(space, i, (abus & 0xffff) | abus_bank, bbus);
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abus += increment;
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if (!(length--) || state->dma_channel[i].dma_disabled)
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break;
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snes_dma_transfer(space, i, (abus & 0xffff) | abus_bank, bbus + 1);
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abus += increment;
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if (!(length--) || state->dma_channel[i].dma_disabled)
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break;
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snes_dma_transfer(space, i, (abus & 0xffff) | abus_bank, bbus + 2);
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abus += increment;
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if (!(length--) || state->dma_channel[i].dma_disabled)
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break;
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snes_dma_transfer(space, i, (abus & 0xffff) | abus_bank, bbus + 3);
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abus += increment;
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}
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break;
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default:
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case 0: /* 1 register write once */
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case 2: /* 1 register write twice */
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case 6: /* 1 register write twice */
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do
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{
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snes_dma_transfer(space, i, (abus & 0xffff) | abus_bank, bbus);
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abus += increment;
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} while (--length && !state->dma_channel[i].dma_disabled);
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break;
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case 1: /* 2 registers write once */
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case 5: /* 2 registers write twice alternate */
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do
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{
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snes_dma_transfer(space, i, (abus & 0xffff) | abus_bank, bbus);
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abus += increment;
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if (!(--length) || state->dma_channel[i].dma_disabled)
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break;
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snes_dma_transfer(space, i, (abus & 0xffff) | abus_bank, bbus + 1);
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abus += increment;
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} while (--length && !state->dma_channel[i].dma_disabled);
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break;
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case 3: /* 2 registers write twice each */
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case 7: /* 2 registers write twice each */
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do
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{
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snes_dma_transfer(space, i, (abus & 0xffff) | abus_bank, bbus);
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abus += increment;
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if (!(--length) || state->dma_channel[i].dma_disabled)
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break;
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snes_dma_transfer(space, i, (abus & 0xffff) | abus_bank, bbus);
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abus += increment;
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if (!(--length) || state->dma_channel[i].dma_disabled)
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break;
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snes_dma_transfer(space, i, (abus & 0xffff) | abus_bank, bbus + 1);
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abus += increment;
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if (!(--length) || state->dma_channel[i].dma_disabled)
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break;
|
||||
snes_dma_transfer(space, i, (abus & 0xffff) | abus_bank, bbus + 1);
|
||||
abus += increment;
|
||||
} while (--length && !state->dma_channel[i].dma_disabled);
|
||||
break;
|
||||
case 4: /* 4 registers write once */
|
||||
do
|
||||
{
|
||||
snes_dma_transfer(space, i, (abus & 0xffff) | abus_bank, bbus);
|
||||
abus += increment;
|
||||
if (!(--length) || state->dma_channel[i].dma_disabled)
|
||||
break;
|
||||
snes_dma_transfer(space, i, (abus & 0xffff) | abus_bank, bbus + 1);
|
||||
abus += increment;
|
||||
if (!(--length) || state->dma_channel[i].dma_disabled)
|
||||
break;
|
||||
snes_dma_transfer(space, i, (abus & 0xffff) | abus_bank, bbus + 2);
|
||||
abus += increment;
|
||||
if (!(--length) || state->dma_channel[i].dma_disabled)
|
||||
break;
|
||||
snes_dma_transfer(space, i, (abus & 0xffff) | abus_bank, bbus + 3);
|
||||
abus += increment;
|
||||
} while (--length && !state->dma_channel[i].dma_disabled);
|
||||
break;
|
||||
default:
|
||||
#ifdef MAME_DEBUG
|
||||
mame_printf_debug(" DMA of unsupported type: %d\n", state->dma_channel[i].dmap & 0x07);
|
||||
mame_printf_debug(" DMA of unsupported type: %d\n", state->dma_channel[i].dmap & 0x07);
|
||||
#endif
|
||||
break;
|
||||
break;
|
||||
}
|
||||
|
||||
/* We're done, so write the new abus back to the registers */
|
||||
state->dma_channel[i].src_addr = abus;
|
||||
state->dma_channel[i].trans_size = 0;
|
||||
/* active channel takes 8 master cycles */
|
||||
/* We're done so write the new abus back to the registers */
|
||||
snes_w_io(space, SNES_DMA_BASE + (i * 0x10) + 2, abus & 0xff);
|
||||
snes_w_io(space, SNES_DMA_BASE + (i * 0x10) + 3, (abus >> 8) & 0xff);
|
||||
snes_w_io(space, SNES_DMA_BASE + (i * 0x10) + 5, 0);
|
||||
snes_w_io(space, SNES_DMA_BASE + (i * 0x10) + 6, 0);
|
||||
|
||||
/* active channel takes 8 master cycles */
|
||||
cpu_adjust_icount(space->cpu,-8);
|
||||
}
|
||||
}
|
||||
@ -2197,8 +2201,8 @@ READ8_HANDLER( superfx_r_bank2 )
|
||||
READ8_HANDLER( superfx_r_bank3 )
|
||||
{
|
||||
/* IMPORTANT: SFX RAM sits in 0x600000-0x7fffff, and it's mirrored in 0xe00000-0xffffff. However, SNES
|
||||
has only access to 0x600000-0x7dffff (because there is WRAM after that), hence we directly use the mirror
|
||||
as the place where to write & read SFX RAM. SNES handlers have been setup accordingly. */
|
||||
has only access to 0x600000-0x7dffff (because there is WRAM after that), hence we directly use the mirror
|
||||
as the place where to write & read SFX RAM. SNES handlers have been setup accordingly. */
|
||||
//printf("superfx_r_bank3: %08x = %02x\n", offset, snes_ram[0xe00000 + offset]);
|
||||
return snes_ram[0xe00000 + offset];
|
||||
}
|
||||
@ -2218,8 +2222,8 @@ WRITE8_HANDLER( superfx_w_bank2 )
|
||||
WRITE8_HANDLER( superfx_w_bank3 )
|
||||
{
|
||||
/* IMPORTANT: SFX RAM sits in 0x600000-0x7fffff, and it's mirrored in 0xe00000-0xffffff. However, SNES
|
||||
has only access to 0x600000-0x7dffff (because there is WRAM after that), hence we directly use the mirror
|
||||
as the place where to write & read SFX RAM. SNES handlers have been setup accordingly. */
|
||||
has only access to 0x600000-0x7dffff (because there is WRAM after that), hence we directly use the mirror
|
||||
as the place where to write & read SFX RAM. SNES handlers have been setup accordingly. */
|
||||
//printf("superfx_w_bank3: %08x = %02x\n", offset, data);
|
||||
snes_ram[0xe00000 + offset] = data;
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user