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pcipc.cpp: add table with bios post codes strings for PhoenixBIOS 4.0 Revision 6 and use it as default (nw)

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The tables that were already present did not have the correct codes used by the default bios in the pcipc machine.
This commit is contained in:
yz70s 2017-06-04 00:00:46 +02:00
parent 247f723094
commit bd0d880c5d
1 changed files with 188 additions and 1 deletions
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189
src/mame/drivers/pcipc.cpp
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@ -36,9 +36,11 @@ public:
};
static const boot_state_info boot_state_infos_phoenix[];
static const boot_state_info boot_state_infos_phoenix_ver40_rev6[];
static const boot_state_info boot_state_infos_award[];
DECLARE_WRITE8_MEMBER(boot_state_phoenix_w);
DECLARE_WRITE8_MEMBER(boot_state_phoenix_ver40_rev6_w);
DECLARE_WRITE8_MEMBER(boot_state_award_w);
pcipc_state(const machine_config &mconfig, device_type type, const char *tag);
@ -184,6 +186,178 @@ const pcipc_state::boot_state_info pcipc_state::boot_state_infos_phoenix[] = {
{ 0, nullptr }
};
const pcipc_state::boot_state_info pcipc_state::boot_state_infos_phoenix_ver40_rev6[] = {
// Code, "(Beeps) POST Routine Description"
{ 0x02, "Verify Real Mode." },
{ 0x03, "Disable Non-Maskable Interrupt (NMI)." },
{ 0x04, "Get CPU type." },
{ 0x06, "Initialize system hardware." },
{ 0x07, "Disable shadow and execute code from the ROM." },
{ 0x08, "Initialize chipset with initial POST values." },
{ 0x09, "Set IN POST flag." },
{ 0x0A, "Initialize CPU registers." },
{ 0x0B, "Enable CPU cache." },
{ 0x0C, "Initialize caches to initial POST values." },
{ 0x0E, "Initialize I/O component." },
{ 0x0F, "Initialize the local bus IDE." },
{ 0x10, "Initialize Power Management." },
{ 0x11, "Load alternate registers with initial POST values." },
{ 0x12, "Restore CPU control word during warm boot." },
{ 0x13, "Initialize PCI Bus Mastering devices." },
{ 0x14, "Initialize keyboard controller." },
{ 0x16, "(1-2-2-3) BIOS ROM checksum." },
{ 0x17, "Initialize cache before memory Auto size." },
{ 0x18, "8254 timer initialization." },
{ 0x1A, "8237 DMA controller initialization." },
{ 0x1C, "Reset Programmable Interrupt Controller." },
{ 0x20, "(1-3-1-1) Test DRAM refresh." },
{ 0x22, "(1-3-1-3) Test 8742 Keyboard Controller." },
{ 0x24, "Set ES segment register to 4 GB." },
{ 0x28, "Auto size DRAM." },
{ 0x29, "Initialize POST Memory Manager." },
{ 0x2A, "Clear 512 kB base RAM." },
{ 0x2C, "(1-3-4-1) RAM failure on address line xxxx*." },
{ 0x2E, "(1-3-4-3) RAM failure on data bits xxxx* of low byte of memory bus." },
{ 0x2F, "Enable cache before system BIOS shadow." },
{ 0x32, "Test CPU bus-clock frequency." },
{ 0x33, "Initialize Phoenix Dispatch Manager." },
{ 0x36, "Warm start shut down." },
{ 0x38, "Shadow system BIOS ROM." },
{ 0x3A, "Auto size cache." },
{ 0x3C, "Advanced configuration of chipset registers." },
{ 0x3D, "Load alternate registers with CMOS values." },
{ 0x41, "Initialize extended memory for RomPilot." },
{ 0x42, "Initialize interrupt vectors." },
{ 0x45, "POST device initialization." },
{ 0x46, "(2-1-2-3) Check ROM copyright notice." },
{ 0x47, "Initialize I20 support." },
{ 0x48, "Check video configuration against CMOS." },
{ 0x49, "Initialize PCI bus and devices." },
{ 0x4A, "Initialize all video adapters in system." },
{ 0x4B, "QuietBoot start (optional)." },
{ 0x4C, "Shadow video BIOS ROM." },
{ 0x4E, "Display BIOS copyright notice." },
{ 0x4F, "Initialize MultiBoot." },
{ 0x50, "Display CPU type and speed." },
{ 0x51, "Initialize EISA board." },
{ 0x52, "Test keyboard." },
{ 0x54, "Set key click if enabled." },
{ 0x55, "Enable USB devices." },
{ 0x58, "(2-2-3-1) Test for unexpected interrupts." },
{ 0x59, "Initialize POST display service." },
{ 0x5A, "Display prompt 'Press F2 to enter SETUP'." },
{ 0x5B, "Disable CPU cache." },
{ 0x5C, "Test RAM between 512 and 640 kB." },
{ 0x60, "Test extended memory." },
{ 0x62, "Test extended memory address lines." },
{ 0x64, "Jump to UserPatch1." },
{ 0x66, "Configure advanced cache registers." },
{ 0x67, "Initialize Multi Processor APIC." },
{ 0x68, "Enable external and CPU caches." },
{ 0x69, "Setup System Management Mode (SMM) area." },
{ 0x6A, "Display external L2 cache size." },
{ 0x6B, "Load custom defaults (optional)." },
{ 0x6C, "Display shadow-area message." },
{ 0x6E, "Display possible high address for UMB recovery." },
{ 0x70, "Display error messages." },
{ 0x72, "Check for configuration errors." },
{ 0x76, "Check for keyboard errors." },
{ 0x7C, "Set up hardware interrupt vectors." },
{ 0x7D, "Initialize Intelligent System Monitoring." },
{ 0x7E, "Initialize coprocessor if present." },
{ 0x80, "Disable onboard Super I/O ports and IRQs." },
{ 0x81, "Late POST device initialization." },
{ 0x82, "Detect and install external RS232 ports." },
{ 0x83, "Configure non-MCD IDE controllers." },
{ 0x84, "Detect and install external parallel ports." },
{ 0x85, "Initialize PC-compatible PnP ISA devices." },
{ 0x86, "Re-initialize onboard I/O ports." },
{ 0x87, "Configure Motherboard Configurable Devices (optional)." },
{ 0x88, "Initialize BIOS Data Area." },
{ 0x89, "Enable Non-Maskable Interrupts (NMIs)." },
{ 0x8A, "Initialize Extended BIOS Data Area." },
{ 0x8B, "Test and initialize PS/2 mouse." },
{ 0x8C, "Initialize floppy controller." },
{ 0x8F, "Determine number of ATA drives (optional)." },
{ 0x90, "Initialize hard-disk controllers." },
{ 0x91, "Initialize local-bus hard-disk controllers." },
{ 0x92, "Jump to UserPatch2." },
{ 0x93, "Build MPTABLE for multi-processor boards." },
{ 0x95, "Install CD ROM for boot." },
{ 0x96, "Clear huge ES segment register." },
{ 0x97, "Fix up Multi Processor table." },
{ 0x98, "(1-2) Search for option ROMs. One long, two short beeps on checksum failure." },
{ 0x99, "Check for SMART Drive (optional)." },
{ 0x9A, "Shadow option ROMs." },
{ 0x9C, "Set up Power Management." },
{ 0x9D, "Initialize security engine (optional)." },
{ 0x9E, "Enable hardware interrupts." },
{ 0x9F, "Determine number of ATA and SCSI drives." },
{ 0xA0, "Set time of day." },
{ 0xA2, "Check key lock." },
{ 0xA4, "Initialize typematic rate." },
{ 0xA8, "Erase F2 prompt." },
{ 0xAA, "Scan for F2 key stroke." },
{ 0xAC, "Enter SETUP." },
{ 0xAE, "Clear Boot flag." },
{ 0xB0, "Check for errors." },
{ 0xB1, "Inform RomPilot about the end of POST." },
{ 0xB2, "POST done - prepare to boot operating system." },
{ 0xB4, "1 One short beep before boot." },
{ 0xB5, "Terminate QuietBoot (optional)." },
{ 0xB6, "Check password (optional)." },
{ 0xB7, "Initialize ACPI BIOS." },
{ 0xB9, "Prepare Boot." },
{ 0xBA, "Initialize SMBIOS." },
{ 0xBB, "Initialize PnP Option ROMs." },
{ 0xBC, "Clear parity checkers." },
{ 0xBD, "Display MultiBoot menu." },
{ 0xBE, "Clear screen (optional)." },
{ 0xBF, "Check virus and backup reminders." },
{ 0xC0, "Try to boot with INT 19." },
{ 0xC1, "Initialize POST Error Manager (PEM)." },
{ 0xC2, "Initialize error logging." },
{ 0xC3, "Initialize error display function." },
{ 0xC4, "Initialize system error handler." },
{ 0xC5, "PnPnd dual CMOS (optional)." },
{ 0xC6, "Initialize note dock (optional)." },
{ 0xC7, "Initialize note dock late." },
{ 0xC8, "Force check (optional)." },
{ 0xC9, "Extended checksum (optional)." },
{ 0xCA, "Redirect Int 15h to enable remote keyboard." },
{ 0xCB, "Redirect Int 13h to Memory Technologies Devices such as ROM, RAM, PCMCIA, and serial disk." },
{ 0xCC, "Redirect Int 10h to enable remote serial video." },
{ 0xCD, "Re-map I/O and memory for PCMCIA." },
{ 0xCE, "Initialize digitizer and display message." },
{ 0xD2, "Unknown interrupt." },
// The following are for boot block in Flash ROM
{ 0xE0, "Initialize the chipset." },
{ 0xE1, "Initialize the bridge." },
{ 0xE2, "Initialize the CPU." },
{ 0xE3, "Initialize system timer." },
{ 0xE4, "Initialize system I/O." },
{ 0xE5, "Check force recovery boot." },
{ 0xE6, "Checksum BIOS ROM." },
{ 0xE7, "Go to BIOS." },
{ 0xE8, "Set Huge Segment." },
{ 0xE9, "Initialize Multi Processor." },
{ 0xEA, "Initialize OEM special code." },
{ 0xEB, "Initialize PIC and DMA." },
{ 0xEC, "Initialize Memory type." },
{ 0xED, "Initialize Memory size." },
{ 0xEE, "Shadow Boot Block." },
{ 0xEF, "System memory test." },
{ 0xF0, "Initialize interrupt vectors." },
{ 0xF1, "Initialize Run Time Clock." },
{ 0xF2, "Initialize video." },
{ 0xF3, "Initialize System Management Manager." },
{ 0xF4, "Output one beep." },
{ 0xF5, "Clear Huge Segment." },
{ 0xF6, "Boot to Mini DOS." },
{ 0xF7, "Boot to Full DOS." },
{ 0, nullptr }
};
const pcipc_state::boot_state_info pcipc_state::boot_state_infos_award[] = {
{0x01, "Processor test; Processor status verification" },
{0x02, "Processor test 2; Read/Write and verify all CPU registers" },
@ -264,6 +438,19 @@ WRITE8_MEMBER(pcipc_state::boot_state_phoenix_w)
}
WRITE8_MEMBER(pcipc_state::boot_state_phoenix_ver40_rev6_w)
{
const char *desc = "";
for(int i=0; boot_state_infos_phoenix_ver40_rev6[i].message; i++)
if(boot_state_infos_phoenix_ver40_rev6[i].val == data) {
desc = boot_state_infos_phoenix_ver40_rev6[i].message;
break;
}
logerror("Boot state %02x - %s\n", data, desc);
}
WRITE8_MEMBER(pcipc_state::boot_state_award_w)
{
const char *desc = "";
@ -283,7 +470,7 @@ static MACHINE_CONFIG_START(pcipc)
MCFG_PCI_ROOT_ADD( ":pci")
MCFG_I82439HX_ADD( ":pci:00.0", ":maincpu", 256*1024*1024)
MCFG_I82371SB_ISA_ADD(":pci:07.0")
MCFG_I82371SB_BOOT_STATE_HOOK(DEVWRITE8(":", pcipc_state, boot_state_phoenix_w))
MCFG_I82371SB_BOOT_STATE_HOOK(DEVWRITE8(":", pcipc_state, boot_state_phoenix_ver40_rev6_w))
// MCFG_IDE_PCI_ADD( ":pci:07.1", 0x80867010, 0x03, 0x00000000)
MCFG_MGA2064W_ADD( ":pci:12.0")
MACHINE_CONFIG_END