mirror of
https://github.com/holub/mame
synced 2025-04-24 09:20:02 +03:00
Merge pull request #939 from JoakimLarsson/fccpu30_2
Drivers for Force Computers CPU-30 and Signetics DUSCC milestone 1
This commit is contained in:
R. Belmont
GitHub
commit
bd5c95e2eb
@ -2032,6 +2032,18 @@ if (MACHINES["S3C2440"]~=null) then
|
||||
}
|
||||
end
|
||||
|
||||
---------------------------------------------------
|
||||
--
|
||||
--@src/devices/machine/scnxx562.h,MACHINES["DUSCC"] = true
|
||||
---------------------------------------------------
|
||||
|
||||
if (MACHINES["DUSCC"]~=null) then
|
||||
files {
|
||||
MAME_DIR .. "src/devices/machine/scnxx562.cpp",
|
||||
MAME_DIR .. "src/devices/machine/scnxx562.h",
|
||||
}
|
||||
end
|
||||
|
||||
---------------------------------------------------
|
||||
--
|
||||
--@src/devices/machine/serflash.h,MACHINES["SERFLASH"] = true
|
||||
|
||||
@ -9,13 +9,31 @@
|
||||
*
|
||||
* Todo
|
||||
* - Add clock and timers
|
||||
* - Add double buffering for each submode
|
||||
* - Add all missing registers
|
||||
* - Add configuration
|
||||
**********************************************************************/
|
||||
|
||||
#include "68230pit.h"
|
||||
|
||||
#define LOG(x) /* x */
|
||||
#define VERBOSE 0
|
||||
|
||||
#define LOG(x) do { if (VERBOSE) logerror x; } while (0)
|
||||
#define LOGR(x) LOG(x)
|
||||
#if VERBOSE == 2
|
||||
#define logerror printf
|
||||
#endif
|
||||
|
||||
#ifdef _MSC_VER
|
||||
#define FUNCNAME __func__
|
||||
#define LLFORMAT "%I64%"
|
||||
#else
|
||||
#define FUNCNAME __PRETTY_FUNCTION__
|
||||
#define LLFORMAT "%lld"
|
||||
#endif
|
||||
|
||||
//#define LOG(x) x
|
||||
//#define logerror printf
|
||||
|
||||
//**************************************************************************
|
||||
// DEVICE TYPE DEFINITIONS
|
||||
@ -27,22 +45,70 @@ const device_type PIT68230 = &device_creator<pit68230_device>;
|
||||
// pit68230_device - constructors
|
||||
//-------------------------------------------------
|
||||
pit68230_device::pit68230_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, UINT32 variant, const char *shortname, const char *source)
|
||||
: device_t (mconfig, type, name, tag, owner, clock, shortname, source),
|
||||
device_execute_interface (mconfig, *this)
|
||||
, m_icount (0)
|
||||
, m_write_pa (*this)
|
||||
, m_write_h2 (*this), m_pgcr(0), m_psrr(0), m_paddr(0), m_pbddr(0), m_pcddr(0), m_pacr(0), m_pbcr(0), m_padr(0), m_pbdr(0), m_psr(0)
|
||||
{
|
||||
: device_t (mconfig, type, name, tag, owner, clock, shortname, source),
|
||||
device_execute_interface (mconfig, *this)
|
||||
, m_icount (0)
|
||||
, m_pa_out_cb(*this)
|
||||
, m_pa_in_cb(*this)
|
||||
, m_pb_out_cb(*this)
|
||||
, m_pb_in_cb(*this)
|
||||
, m_pc_out_cb(*this)
|
||||
, m_pc_in_cb(*this)
|
||||
, m_h1_out_cb (*this)
|
||||
, m_h2_out_cb (*this)
|
||||
, m_h3_out_cb (*this)
|
||||
, m_h4_out_cb (*this)
|
||||
, m_pgcr(0)
|
||||
, m_psrr(0)
|
||||
, m_paddr(0)
|
||||
, m_pbddr(0)
|
||||
, m_pcddr(0)
|
||||
, m_pacr(0)
|
||||
, m_pbcr(0)
|
||||
, m_padr(0)
|
||||
, m_pbdr(0)
|
||||
, m_psr(0)
|
||||
, m_tcr(0)
|
||||
, m_cpr(0)
|
||||
// , m_cprh(0)
|
||||
// , m_cprm(0)
|
||||
// , m_cprl(0)
|
||||
, m_cntr(0)
|
||||
{
|
||||
}
|
||||
|
||||
|
||||
pit68230_device::pit68230_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
|
||||
: device_t (mconfig, PIT68230, "PIT68230", tag, owner, clock, "pit68230", __FILE__),
|
||||
device_execute_interface (mconfig, *this)
|
||||
, m_icount (0)
|
||||
, m_write_pa (*this)
|
||||
, m_write_h2 (*this), m_pgcr(0), m_psrr(0), m_paddr(0), m_pbddr(0), m_pcddr(0), m_pacr(0), m_pbcr(0), m_padr(0), m_pbdr(0), m_psr(0)
|
||||
{
|
||||
: device_t (mconfig, PIT68230, "PIT68230", tag, owner, clock, "pit68230", __FILE__),
|
||||
device_execute_interface (mconfig, *this)
|
||||
, m_icount (0)
|
||||
, m_pa_out_cb (*this)
|
||||
, m_pa_in_cb(*this)
|
||||
, m_pb_out_cb(*this)
|
||||
, m_pb_in_cb(*this)
|
||||
, m_pc_out_cb(*this)
|
||||
, m_pc_in_cb(*this)
|
||||
, m_h1_out_cb(*this)
|
||||
, m_h2_out_cb(*this)
|
||||
, m_h3_out_cb(*this)
|
||||
, m_h4_out_cb(*this)
|
||||
, m_pgcr(0)
|
||||
, m_psrr(0)
|
||||
, m_paddr(0)
|
||||
, m_pbddr(0)
|
||||
, m_pcddr(0)
|
||||
, m_pacr(0)
|
||||
, m_pbcr(0)
|
||||
, m_padr(0)
|
||||
, m_pbdr(0)
|
||||
, m_psr(0)
|
||||
, m_tcr(0)
|
||||
, m_cpr(0)
|
||||
// , m_cprh(0)
|
||||
// , m_cprm(0)
|
||||
// , m_cprl(0)
|
||||
, m_cntr(0)
|
||||
{
|
||||
}
|
||||
|
||||
//-------------------------------------------------
|
||||
@ -50,12 +116,18 @@ pit68230_device::pit68230_device(const machine_config &mconfig, const char *tag,
|
||||
//-------------------------------------------------
|
||||
void pit68230_device::device_start ()
|
||||
{
|
||||
LOG (logerror ("PIT68230 device started\n"));
|
||||
m_icountptr = &m_icount;
|
||||
LOG(("%s\n", FUNCNAME));
|
||||
m_icountptr = &m_icount;
|
||||
|
||||
// resolve callbacks
|
||||
m_write_pa.resolve_safe ();
|
||||
m_write_h2.resolve_safe ();
|
||||
// resolve callbacks
|
||||
m_pa_out_cb.resolve_safe();
|
||||
m_pa_in_cb.resolve_safe(0);
|
||||
m_pb_out_cb.resolve_safe();
|
||||
m_pb_in_cb.resolve_safe(0);
|
||||
m_h1_out_cb.resolve_safe();
|
||||
m_h2_out_cb.resolve_safe();
|
||||
m_h3_out_cb.resolve_safe();
|
||||
m_h4_out_cb.resolve_safe();
|
||||
}
|
||||
|
||||
//-------------------------------------------------
|
||||
@ -63,17 +135,18 @@ void pit68230_device::device_start ()
|
||||
//-------------------------------------------------
|
||||
void pit68230_device::device_reset ()
|
||||
{
|
||||
LOG (logerror ("PIT68230 device reseted\n"));
|
||||
m_pgcr = 0;
|
||||
m_psrr = 0;
|
||||
m_paddr = 0;
|
||||
m_pbddr = 0;
|
||||
m_pcddr = 0;
|
||||
m_pacr = 0; m_write_h2 (m_pacr);
|
||||
m_pbcr = 0;
|
||||
m_padr = 0; m_write_pa ((offs_t)0, m_padr); // TODO: check PADDR
|
||||
m_pbdr = 0;
|
||||
m_psr = 0;
|
||||
LOG(("%s %s \n",tag(), FUNCNAME));
|
||||
|
||||
m_pgcr = 0;
|
||||
m_psrr = 0;
|
||||
m_paddr = 0;
|
||||
m_pbddr = 0;
|
||||
m_pcddr = 0;
|
||||
m_pacr = 0; m_h2_out_cb(m_pacr);
|
||||
m_pbcr = 0;
|
||||
m_padr = 0; m_pa_out_cb((offs_t)0, m_padr); // TODO: check PADDR
|
||||
m_pbdr = 0;
|
||||
m_psr = 0;
|
||||
}
|
||||
|
||||
//-------------------------------------------------
|
||||
@ -85,16 +158,16 @@ void pit68230_device::device_timer (emu_timer &timer, device_timer_id id, INT32
|
||||
|
||||
void pit68230_device::h1_set (UINT8 state)
|
||||
{
|
||||
LOG (logerror ("h1_set %d @ m_psr %2x => ", state, m_psr));
|
||||
if (state) m_psr |= 1; else m_psr &= ~1;
|
||||
LOG (logerror ("%02x %lld\n", m_psr, machine ().firstcpu->total_cycles ()));
|
||||
LOG(("%s %s %d @ m_psr %2x => ",tag(), FUNCNAME, state, m_psr));
|
||||
if (state) m_psr |= 1; else m_psr &= ~1;
|
||||
LOG(("%02x %lld\n", m_psr, machine ().firstcpu->total_cycles ()));
|
||||
}
|
||||
|
||||
void pit68230_device::portb_setbit (UINT8 bit, UINT8 state)
|
||||
{
|
||||
LOG (logerror ("portb_setbit %d/%d @ m_pbdr %2x => ", bit, state, m_pbdr));
|
||||
if (state) m_pbdr |= (1 << bit); else m_pbdr &= ~(1 << bit);
|
||||
LOG (logerror ("%02x %lld\n", m_pbdr, machine ().firstcpu->total_cycles ()));
|
||||
LOG(("%s %s %d/%d @ m_pbdr %2x => ", tag(), FUNCNAME, bit, state, m_pbdr));
|
||||
if (state) m_pbdr |= (1 << bit); else m_pbdr &= ~(1 << bit);
|
||||
LOG(("%02x %lld\n", m_pbdr, machine ().firstcpu->total_cycles ()));
|
||||
}
|
||||
|
||||
//-------------------------------------------------
|
||||
@ -109,157 +182,373 @@ void pit68230_device::execute_run ()
|
||||
} while (m_icount > 0);
|
||||
}
|
||||
|
||||
LOG (static INT32 ow_cnt = 0)
|
||||
LOG (static INT32 ow_data = 0)
|
||||
LOG (static INT32 ow_ofs = 0)
|
||||
#if VERBOSE > 2
|
||||
static INT32 ow_cnt = 0;
|
||||
static INT32 ow_data = 0;
|
||||
static INT32 ow_ofs = 0;
|
||||
#endif
|
||||
|
||||
WRITE8_MEMBER (pit68230_device::write){
|
||||
switch (offset) {
|
||||
case PIT_68230_PGCR:
|
||||
m_pgcr = data;
|
||||
break;
|
||||
|
||||
case PIT_68230_PSRR:
|
||||
m_psrr = data;
|
||||
break;
|
||||
|
||||
case PIT_68230_PADDR:
|
||||
m_paddr = data;
|
||||
break;
|
||||
|
||||
case PIT_68230_PBDDR:
|
||||
m_pbddr = data;
|
||||
break;
|
||||
|
||||
case PIT_68230_PCDDR:
|
||||
m_pcddr = data;
|
||||
break;
|
||||
|
||||
case PIT_68230_PACR:
|
||||
m_pacr = data;
|
||||
// callbacks
|
||||
/*PACR in Mode 0
|
||||
* 5 43 H2 Control in Submode 00 && 01
|
||||
* ------------------------------------
|
||||
* 0 XX Input pin - edge-sensitive status input, H2S is set on an asserted edge.
|
||||
* 1 00 Output pin - negated, H2S is always clear.
|
||||
* 1 01 Output pin - asserted, H2S is always clear.
|
||||
* 1 10 Output pin - interlocked input handshake protocol, H2S is always clear.
|
||||
* 1 11 Output pin - pulsed input handshake protocol, H2S is always clear.
|
||||
*
|
||||
* 5 43 H2 Control in Submode 1x
|
||||
* ------------------------------------
|
||||
* 0 XX Input pin - edge-sensitive status input, H2S is set on an asserted edge.
|
||||
* 1 X0 Output pin - negated, H2S is always cleared.
|
||||
* 1 X1 Output pin - asserted, H2S is always cleared.
|
||||
*/
|
||||
m_write_h2 (m_pacr & 0x08 ? 1 : 0); // TODO: Check mode and submodes
|
||||
break;
|
||||
|
||||
case PIT_68230_PBCR:
|
||||
m_pbcr = data;
|
||||
break;
|
||||
|
||||
case PIT_68230_PADR:
|
||||
m_padr = data;
|
||||
// callbacks
|
||||
m_write_pa ((offs_t)0, m_padr); // TODO: check PADDR
|
||||
break;
|
||||
|
||||
case PIT_68230_PSR:
|
||||
m_psr = data;
|
||||
break;
|
||||
|
||||
default:
|
||||
LOG (logerror ("unhandled register %02x", offset));
|
||||
}
|
||||
|
||||
LOG (if (offset != ow_ofs || data != ow_data || ow_cnt >= 1000) {
|
||||
logerror ("\npit68230_device::write: previous identical operation performed %02x times\n", ow_cnt);
|
||||
ow_cnt = 0;
|
||||
ow_data = data;
|
||||
ow_ofs = offset;
|
||||
logerror ("pit68230_device::write: offset=%02x data=%02x %lld\n", ow_ofs, ow_data, machine ().firstcpu->total_cycles ());
|
||||
}
|
||||
else
|
||||
ow_cnt++; )
|
||||
void pit68230_device::wr_pitreg_pgcr(UINT8 data)
|
||||
{
|
||||
LOG(("%s(%02x) \"%s\": %s - %02x\n", FUNCNAME, data, m_owner->tag(), FUNCNAME, data));
|
||||
m_pgcr = data;
|
||||
}
|
||||
|
||||
LOG (static INT32 or_cnt = 0)
|
||||
LOG (static INT32 or_data = 0)
|
||||
LOG (static INT32 or_ofs = 0)
|
||||
void pit68230_device::wr_pitreg_psrr(UINT8 data)
|
||||
{
|
||||
LOG(("%s(%02x) \"%s\": %s - %02x\n", FUNCNAME, data, m_owner->tag(), FUNCNAME, data));
|
||||
m_psrr = data;
|
||||
}
|
||||
|
||||
void pit68230_device::wr_pitreg_paddr(UINT8 data)
|
||||
{
|
||||
LOG(("%s(%02x) \"%s\": %s - %02x\n", FUNCNAME, data, m_owner->tag(), FUNCNAME, data));
|
||||
m_paddr = data;
|
||||
}
|
||||
|
||||
void pit68230_device::wr_pitreg_pbddr(UINT8 data)
|
||||
{
|
||||
LOG(("%s(%02x) \"%s\": %s - %02x\n", FUNCNAME, data, m_owner->tag(), FUNCNAME, data));
|
||||
m_pbddr = data;
|
||||
}
|
||||
|
||||
void pit68230_device::wr_pitreg_pcddr(UINT8 data)
|
||||
{
|
||||
LOG(("%s(%02x) \"%s\": %s - %02x\n", FUNCNAME, data, m_owner->tag(), FUNCNAME, data));
|
||||
m_pcddr = data;
|
||||
}
|
||||
|
||||
void pit68230_device::wr_pitreg_pacr(UINT8 data)
|
||||
{
|
||||
LOG(("%s(%02x) \"%s\": %s - %02x\n", FUNCNAME, data, m_owner->tag(), FUNCNAME, data));
|
||||
m_pacr = data;
|
||||
// callbacks
|
||||
/*PACR in Mode 0
|
||||
* 5 43 H2 Control in Submode 00 && 01
|
||||
* ------------------------------------
|
||||
* 0 XX Input pin - edge-sensitive status input, H2S is set on an asserted edge.
|
||||
* 1 00 Output pin - negated, H2S is always clear.
|
||||
* 1 01 Output pin - asserted, H2S is always clear.
|
||||
* 1 10 Output pin - interlocked input handshake protocol, H2S is always clear.
|
||||
* 1 11 Output pin - pulsed input handshake protocol, H2S is always clear.
|
||||
*
|
||||
* 5 43 H2 Control in Submode 1x
|
||||
* ------------------------------------
|
||||
* 0 XX Input pin - edge-sensitive status input, H2S is set on an asserted edge.
|
||||
* 1 X0 Output pin - negated, H2S is always cleared.
|
||||
* 1 X1 Output pin - asserted, H2S is always cleared.
|
||||
*/
|
||||
m_h2_out_cb (m_pacr & 0x08 ? 1 : 0); // TODO: Check mode and submodes
|
||||
}
|
||||
|
||||
void pit68230_device::wr_pitreg_pbcr(UINT8 data)
|
||||
{
|
||||
LOG(("%s(%02x) \"%s\": %s - %02x\n", FUNCNAME, data, m_owner->tag(), FUNCNAME, data));
|
||||
m_pbcr = data;
|
||||
}
|
||||
|
||||
void pit68230_device::wr_pitreg_padr(UINT8 data)
|
||||
{
|
||||
LOG(("%s(%02x) \"%s\": %s - %02x\n", FUNCNAME, data, m_owner->tag(), FUNCNAME, data));
|
||||
m_padr = data;
|
||||
// callbacks
|
||||
m_pa_out_cb ((offs_t)0, m_padr); // TODO: check PADDR
|
||||
}
|
||||
|
||||
void pit68230_device::wr_pitreg_psr(UINT8 data)
|
||||
{
|
||||
LOG(("%s(%02x) \"%s\": %s - %02x\n", FUNCNAME, data, m_owner->tag(), FUNCNAME, data));
|
||||
m_psr = data;
|
||||
}
|
||||
|
||||
/* The timer control register (TCR) determines all operations of the timer. Bits 7-5 configure the PC3/TOUT
|
||||
and PC7/TIACKpins for port C, square wave, vectored interrupt, or autovectored interrupt operation bit
|
||||
4 specifies whether the counter receives data from the counter preload register or continues counting when
|
||||
zero detect is reached ; bit 3 is unused and is read as zero bits 2 and 1 configure the path from the CLK
|
||||
and TINpins to the counter controller ; and bit 0 ena-bles the timer. This register is readable and writable
|
||||
at all times. All bits are cleared to zero when the RESET pin is asserted.
|
||||
|
||||
TCR bits
|
||||
7 6 5 TOUT/TIACK Control
|
||||
----------------------------
|
||||
0 0 X The dual-function pins PC3/TOUT and PC7/TIACK carry the port C function.
|
||||
0 1 X The dual-function pinPC3/TOUT carries the TOUT function. In the run state it is used as a squarewave
|
||||
output and is toggled on zero detect. The TOUT pin is high while in the halt state. The dualfunction
|
||||
pin PC7/TIACK carries the PC7 function.
|
||||
1 0 0 The dual-function pin PC3/TOUT carries the TOUT function. In the run or halt state it is used as
|
||||
a timer interrupt request output. The timer interrupt is disabled, thus, the pin is always three stated.
|
||||
The dual-function pin PC7/TIACK carries the TIACK function ; however, since interrupt request is
|
||||
negated, the PI/T produces no response (i.e., no data or DTACK) to an asserted TIACK. Refer to
|
||||
5.1.3. Timer Interrupt Acknowledge Cycles for details.
|
||||
1 0 1 The dual-function pin PC3/TOUT carries the TOUTfunction and is used as a timer interrupt request
|
||||
output. The timer interrupt is enabled ; thus, the pin is low when the timer ZDS status bit is one.
|
||||
The dual-function pin PC7/TIACK carries the TIACK function and is used as a timer interrupt acknowledge
|
||||
input. Refer to the5.1.3. Timer InterruptAcknowledge Cycles fordetails. Thiscombination
|
||||
supports vectored timer interrupts.
|
||||
1 1 0 The dual-function pin PC3/TOUT function. In the run or halt state it is used as a timer interrupt
|
||||
request output. The timer interrupt is disabled ; thus, the pin is always three-stated. The dual-function
|
||||
pin PC7/TIACK carries the PC7 function.
|
||||
1 1 1 The dual-function pin PC3/TOUT carries the TOUTfunction and is used as a timer interrupt request
|
||||
output. The timer interrupt is enabled ; thus, the pin is low when the timer ZDS status bit is one.
|
||||
The dual-function pin PC7/TIACK carries the PC7 function and autovectored interrupts are supported.
|
||||
|
||||
TCR bit 4 - Zero Detect Control
|
||||
0 The counter is loaded fromthe counter preload register on the first clock to the 24-bit counter after
|
||||
zero detect, then resumes counting.
|
||||
1 The counter rolls over on zero detect, then continues counting.
|
||||
|
||||
TCR bit 3 - Unused and is always read as zero.
|
||||
|
||||
TCR bits
|
||||
2 1 Clock Control
|
||||
0 0 The PC2/TIN input pin carries the port C function, and the CLK pin and prescaler are used. The
|
||||
prescaler is decremented on the falling transition of the CLKpin ; the 24-bit counter is decremented,
|
||||
rolls over, or is loaded from the counter preload registers when the prescaler rolls over from $OO
|
||||
to $1F. The timer enable bit determines whether the timer is in the run or halt state.
|
||||
0 1 The PC2/TIN pin serves as a timer input, and the CLK pin and prescaler are used. The prescaler
|
||||
is decremented on the falling transition of the CLK pin ; the 24-bit counter is decremented, rolls
|
||||
over, or is loaded from the counter preload registers when the prescaler rolls over from $00 to $1F.
|
||||
The timer is in the run state when the timer enable bit is one and the TIN pin is high ; otherwise,
|
||||
the timer is in the halt state.
|
||||
1 0 The PC2/TIN pin serves as a timer input and the prescaler is used. The prescaler is decremented
|
||||
following the rising transition of the TIN pin after being synchronized with the internal clock. The
|
||||
24-bit counter is decremented, rolls over, or is loaded from the counter preload registers when the
|
||||
prescaler rolls over from $00 to $1F. The timer enable bit determines whether the timer is in the
|
||||
run or halt state.
|
||||
1 1 The PC2/TIN pin serves as a timer input and the prescaler is not used. The 24-bit counter is decremented,
|
||||
rolls over, or is loaded from the counter preload registers following the rising edge of
|
||||
the TIN pin after being synchronized with the internal clock. The timer enable bit determines whether
|
||||
the timer is in the run or halt state.
|
||||
TCR bit 0 - Timer Enable
|
||||
0 Disabled
|
||||
1 Enabled
|
||||
*/
|
||||
void pit68230_device::wr_pitreg_tcr(UINT8 data)
|
||||
{
|
||||
LOG(("%s(%02x) \"%s\": %s - %02x Timer %s\n",
|
||||
FUNCNAME, data, m_owner->tag(), FUNCNAME, data, data & REG_TCR_ENABLE ? "enabled" : "disabled"));
|
||||
m_tcr = data;
|
||||
}
|
||||
|
||||
void pit68230_device::wr_pitreg_cprh(UINT8 data)
|
||||
{
|
||||
LOG(("%s(%02x) \"%s\": %s - %02x\n", FUNCNAME, data, m_owner->tag(), FUNCNAME, data));
|
||||
m_cpr &= ~0xff0000;
|
||||
m_cpr |= ((data << 16) & 0xff0000);
|
||||
// m_cprh = data;
|
||||
}
|
||||
|
||||
void pit68230_device::wr_pitreg_cprm(UINT8 data)
|
||||
{
|
||||
LOG(("%s(%02x) \"%s\": %s - %02x\n", FUNCNAME, data, m_owner->tag(), FUNCNAME, data));
|
||||
m_cpr &= ~0x00ff00;
|
||||
m_cpr |= ((data << 8) & 0x00ff00);
|
||||
// m_cprm = data;
|
||||
}
|
||||
|
||||
void pit68230_device::wr_pitreg_cprl(UINT8 data)
|
||||
{
|
||||
LOG(("%s(%02x) \"%s\": %s - %02x\n", FUNCNAME, data, m_owner->tag(), FUNCNAME, data));
|
||||
m_cpr &= ~0x0000ff;
|
||||
m_cpr |= ((data << 0) & 0x0000ff);
|
||||
// m_cprl = data;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER (pit68230_device::write)
|
||||
{
|
||||
LOG(("%s %s \n",tag(), FUNCNAME));
|
||||
switch (offset) {
|
||||
case PIT_68230_PGCR: wr_pitreg_pgcr(data); break;
|
||||
case PIT_68230_PSRR: wr_pitreg_psrr(data); break;
|
||||
case PIT_68230_PADDR: wr_pitreg_paddr(data); break;
|
||||
case PIT_68230_PBDDR: wr_pitreg_pbddr(data); break;
|
||||
case PIT_68230_PCDDR: wr_pitreg_pcddr(data); break;
|
||||
case PIT_68230_PACR: wr_pitreg_pacr(data); break;
|
||||
case PIT_68230_PBCR: wr_pitreg_pbcr(data); break;
|
||||
case PIT_68230_PADR: wr_pitreg_padr(data); break;
|
||||
case PIT_68230_PAAR: break; // RO register so ignored
|
||||
case PIT_68230_PBAR: break; // RO register so ignored
|
||||
case PIT_68230_PSR: wr_pitreg_psr(data); break;
|
||||
case PIT_68230_TCR: wr_pitreg_tcr(data); break;
|
||||
case PIT_68230_CPRH: wr_pitreg_cprh(data); break;
|
||||
case PIT_68230_CPRM: wr_pitreg_cprm(data); break;
|
||||
case PIT_68230_CPRL: wr_pitreg_cprl(data); break;
|
||||
default:
|
||||
LOG (("Unhandled Write of %02x to register %02x", data, offset));
|
||||
}
|
||||
|
||||
#if VERBOSE > 2
|
||||
if (offset != ow_ofs || data != ow_data || ow_cnt >= 1000) {
|
||||
logerror ("\npit68230_device::write: previous identical operation performed %02x times\n", ow_cnt);
|
||||
ow_cnt = 0;
|
||||
ow_data = data;
|
||||
ow_ofs = offset;
|
||||
logerror ("pit68230_device::write: offset=%02x data=%02x %lld\n", ow_ofs, ow_data, machine ().firstcpu->total_cycles ());
|
||||
}
|
||||
else
|
||||
ow_cnt++;
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
#if VERBOSE > 2
|
||||
static INT32 or_cnt = 0;
|
||||
static INT32 or_data = 0;
|
||||
static INT32 or_ofs = 0;
|
||||
#endif
|
||||
|
||||
UINT8 pit68230_device::rr_pitreg_pgcr()
|
||||
{
|
||||
LOGR(("%s %s <- %02x\n",tag(), FUNCNAME, m_pgcr));
|
||||
return m_pgcr;
|
||||
}
|
||||
|
||||
UINT8 pit68230_device::rr_pitreg_psrr()
|
||||
{
|
||||
LOGR(("%s %s <- %02x\n",tag(), FUNCNAME, m_psrr));
|
||||
return m_psrr;
|
||||
}
|
||||
|
||||
UINT8 pit68230_device::rr_pitreg_paddr()
|
||||
{
|
||||
LOGR(("%s %s <- %02x\n",tag(), FUNCNAME, m_paddr));
|
||||
return m_paddr;
|
||||
}
|
||||
|
||||
UINT8 pit68230_device::rr_pitreg_pbddr()
|
||||
{
|
||||
LOGR(("%s %s <- %02x\n",tag(), FUNCNAME, m_pbddr));
|
||||
return m_pbddr;
|
||||
}
|
||||
|
||||
UINT8 pit68230_device::rr_pitreg_pcddr()
|
||||
{
|
||||
LOGR(("%s %s <- %02x\n",tag(), FUNCNAME, m_pcddr));
|
||||
return m_pcddr;
|
||||
}
|
||||
|
||||
UINT8 pit68230_device::rr_pitreg_pacr()
|
||||
{
|
||||
LOGR(("%s %s <- %02x\n",tag(), FUNCNAME, m_pacr));
|
||||
return m_pacr;
|
||||
}
|
||||
|
||||
UINT8 pit68230_device::rr_pitreg_pbcr()
|
||||
{
|
||||
LOGR(("%s %s <- %02x\n",tag(), FUNCNAME, m_pbcr));
|
||||
return m_pbcr;
|
||||
}
|
||||
|
||||
UINT8 pit68230_device::rr_pitreg_padr()
|
||||
{
|
||||
LOGR(("%s %s <- %02x\n",tag(), FUNCNAME, m_padr));
|
||||
return m_padr;
|
||||
}
|
||||
|
||||
/* 4.6.2. PORT B DATA REGISTER (PBDR). The port B data register is a holding
|
||||
* register for moving data to and from port B pins. The port B data direction
|
||||
* register determines whether each pin is an input (zero) or an output (one).
|
||||
* This register is readable and writable at all times. Depending on the chosen
|
||||
* mode/submode, reading or writing may affect the double-buffered handshake
|
||||
* mechanism. The port B data register is not affected by the assertion of the
|
||||
* RESET pin. PB0-PB7 sits on pins 17-24 on a 48 pin DIP package */
|
||||
UINT8 pit68230_device::rr_pitreg_pbdr()
|
||||
{
|
||||
LOGR(("%s %s <- %02x\n",tag(), FUNCNAME, m_pbdr));
|
||||
return m_pbdr;
|
||||
}
|
||||
|
||||
/* The port A alternate register is an alternate register for reading the port A pins.
|
||||
It is a read-only address and no other PI/T condition is affected. In all modes,
|
||||
the instantaneous pin level is read and no input latching is performed except at the
|
||||
data bus interface. Writes to this address are answered with DTACK, but the data is ignored.*/
|
||||
UINT8 pit68230_device::rr_pitreg_paar()
|
||||
{
|
||||
// NOTE: no side effect emulated so using ..padr
|
||||
UINT8 ret;
|
||||
ret = m_pa_in_cb();
|
||||
LOGR(("%s %s <- %02x\n",tag(), FUNCNAME, ret));
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* The port B alternate register is an alternate register for reading the port B pins.
|
||||
It is a read-only address and no other PI/T condition is affected. In all modes,
|
||||
the instantaneous pin level is read and no input latching is performed except at the
|
||||
data bus interface.Writes to this address are answered with DTACK, but the data is ignored.*/
|
||||
UINT8 pit68230_device::rr_pitreg_pbar()
|
||||
{
|
||||
// NOTE: no side effect emulated so using ..pbdr
|
||||
UINT8 ret;
|
||||
ret = m_pb_in_cb();
|
||||
LOGR(("%s %s <- %02x\n",tag(), FUNCNAME, ret));
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* 4.8. PORT STATUS REGISTER (PSR) The port status register contains information about
|
||||
* handshake pin activity. Bits 7-4 show the instantaneous level of the respective handshake
|
||||
* pin, and are independent of the handshake pin sense bits in the port general control
|
||||
* register. Bits 3-0 are the respective status bits referred to throughout this document.
|
||||
* Their interpretation depends on the programmed mode/submode of the PI/T. For bits
|
||||
* 3-0 a one is the active or asserted state. */
|
||||
UINT8 pit68230_device::rr_pitreg_psr()
|
||||
{
|
||||
LOGR(("%s %s <- %02x\n",tag(), FUNCNAME, m_psr));
|
||||
return m_psr;
|
||||
}
|
||||
|
||||
UINT8 pit68230_device::rr_pitreg_cntrh()
|
||||
{
|
||||
LOGR(("%s %s <- %02x\n",tag(), FUNCNAME, (m_cntr >> 16) & 0xff));
|
||||
return (m_cntr >> 16) & 0xff;
|
||||
}
|
||||
|
||||
UINT8 pit68230_device::rr_pitreg_cntrm()
|
||||
{
|
||||
LOGR(("%s %s <- %02x\n",tag(), FUNCNAME, (m_cntr >> 8) & 0xff));
|
||||
return (m_cntr >> 8) & 0xff;
|
||||
}
|
||||
|
||||
UINT8 pit68230_device::rr_pitreg_cntrl()
|
||||
{
|
||||
LOGR(("%s %s <- %02x\n",tag(), FUNCNAME, (m_cntr >> 0) & 0xff));
|
||||
return (m_cntr >> 0) & 0xff;
|
||||
}
|
||||
|
||||
READ8_MEMBER (pit68230_device::read){
|
||||
UINT8 data;
|
||||
UINT8 data;
|
||||
|
||||
switch (offset) {
|
||||
case PIT_68230_PGCR:
|
||||
data = m_pgcr;
|
||||
break;
|
||||
switch (offset) {
|
||||
case PIT_68230_PGCR: data = rr_pitreg_pgcr(); break;
|
||||
case PIT_68230_PSRR: data = rr_pitreg_psrr(); break;
|
||||
case PIT_68230_PADDR: data = rr_pitreg_paddr(); break;
|
||||
case PIT_68230_PBDDR: data = rr_pitreg_pbddr(); break;
|
||||
case PIT_68230_PCDDR: data = rr_pitreg_pcddr(); break;
|
||||
case PIT_68230_PACR: data = rr_pitreg_pacr(); break;
|
||||
case PIT_68230_PBCR: data = rr_pitreg_pbcr(); break;
|
||||
case PIT_68230_PADR: data = rr_pitreg_padr(); break;
|
||||
case PIT_68230_PBDR: data = rr_pitreg_pbdr(); break;
|
||||
case PIT_68230_PAAR: data = rr_pitreg_paar(); break;
|
||||
case PIT_68230_PBAR: data = rr_pitreg_pbar(); break;
|
||||
case PIT_68230_PSR: data = rr_pitreg_psr(); break;
|
||||
case PIT_68230_CNTRH: data = rr_pitreg_cntrh(); break;
|
||||
case PIT_68230_CNTRM: data = rr_pitreg_cntrm(); break;
|
||||
case PIT_68230_CNTRL: data = rr_pitreg_cntrl(); break;
|
||||
default:
|
||||
LOG (("Unhandled read register %02x\n", offset));
|
||||
data = 0;
|
||||
}
|
||||
|
||||
case PIT_68230_PSRR:
|
||||
data = m_psrr;
|
||||
break;
|
||||
#if VERBOSE > 2
|
||||
if (offset != or_ofs || data != or_data || or_cnt >= 1000) {
|
||||
logerror ("\npit68230_device::read: previous identical operation performed %02x times\n", or_cnt);
|
||||
or_cnt = 0;
|
||||
or_data = data;
|
||||
or_ofs = offset;
|
||||
logerror ("pit68230_device::read: offset=%02x data=%02x %lld\n", or_ofs, or_data, machine ().firstcpu->total_cycles ());
|
||||
}
|
||||
else
|
||||
or_cnt++;
|
||||
#endif
|
||||
|
||||
case PIT_68230_PADDR:
|
||||
data = m_paddr;
|
||||
break;
|
||||
|
||||
case PIT_68230_PBDDR:
|
||||
data = m_pbddr;
|
||||
break;
|
||||
|
||||
case PIT_68230_PCDDR:
|
||||
data = m_pcddr;
|
||||
break;
|
||||
|
||||
case PIT_68230_PACR:
|
||||
data = m_pacr;
|
||||
break;
|
||||
|
||||
case PIT_68230_PBCR:
|
||||
data = m_pbcr;
|
||||
break;
|
||||
|
||||
case PIT_68230_PADR:
|
||||
data = m_padr;
|
||||
break;
|
||||
|
||||
case PIT_68230_PBDR:
|
||||
/* 4.6.2. PORT B DATA REGISTER (PBDR). The port B data register is a holding
|
||||
* register for moving data to and from port B pins. The port B data direction
|
||||
* register determines whether each pin is an input (zero) or an output (one).
|
||||
* This register is readable and writable at all times. Depending on the chosen
|
||||
* mode/submode, reading or writing may affect the double-buffered handshake
|
||||
* mechanism. The port B data register is not affected by the assertion of the
|
||||
* RESET pin. PB0-PB7 sits on pins 17-24 on a 48 pin DIP package */
|
||||
data = m_pbdr;
|
||||
break;
|
||||
|
||||
case PIT_68230_PSR:
|
||||
/* 4.8. PORT STATUS REGISTER (PSR) The port status register contains information about
|
||||
* handshake pin activity. Bits 7-4 show the instantaneous level of the respective handshake
|
||||
* pin, and are independent of the handshake pin sense bits in the port general control
|
||||
* register. Bits 3-0 are the respective status bits referred to throughout this document.
|
||||
* Their interpretation depends on the programmed mode/submode of the PI/T. For bits
|
||||
* 3-0 a one is the active or asserted state. */
|
||||
data = m_psr;
|
||||
break;
|
||||
|
||||
default:
|
||||
LOG (logerror ("unhandled register %02x", offset));
|
||||
data = 0;
|
||||
}
|
||||
|
||||
LOG (if (offset != or_ofs || data != or_data || or_cnt >= 1000) {
|
||||
logerror ("\npit68230_device::read: previous identical operation performed %02x times\n", or_cnt);
|
||||
or_cnt = 0;
|
||||
or_data = data;
|
||||
or_ofs = offset;
|
||||
logerror ("pit68230_device::read: offset=%02x data=%02x %lld\n", or_ofs, or_data, machine ().firstcpu->total_cycles ());
|
||||
}
|
||||
else
|
||||
or_cnt++; )
|
||||
|
||||
return data;
|
||||
return data;
|
||||
}
|
||||
|
||||
@ -43,14 +43,35 @@
|
||||
// INTERFACE CONFIGURATION MACROS
|
||||
//**************************************************************************
|
||||
|
||||
#define MCFG_PIT68230_PA_OUTPUT_CALLBACK(_write) \
|
||||
devcb = &pit68230_device::set_pa_wr_callback (*device, DEVCB_ ## _write);
|
||||
#define MCFG_PIT68230_PA_INPUT_CB(_devcb) \
|
||||
devcb = &pit68230_device::set_pa_in_callback (*device, DEVCB_##_devcb);
|
||||
|
||||
#define MCFG_PIT68230_PB_OUTPUT_CALLBACK(_write) \
|
||||
devcb = &pit68230_device::set_pb_wr_callback (*device, DEVCB_ ## _write);
|
||||
#define MCFG_PIT68230_PA_OUTPUT_CB(_devcb) \
|
||||
devcb = &pit68230_device::set_pa_out_callback (*device, DEVCB_##_devcb);
|
||||
|
||||
#define MCFG_PIT68230_H2_CALLBACK(_write) \
|
||||
devcb = &pit68230_device::set_h2_wr_callback (*device, DEVCB_ ## _write);
|
||||
#define MCFG_PIT68230_PB_INPUT_CB(_devcb) \
|
||||
devcb = &pit68230_device::set_pb_in_callback (*device, DEVCB_##_devcb);
|
||||
|
||||
#define MCFG_PIT68230_PB_OUTPUT_CB(_devcb) \
|
||||
devcb = &pit68230_device::set_pb_out_callback (*device, DEVCB_##_devcb);
|
||||
|
||||
#define MCFG_PIT68230_PC_INPUT_CB(_devcb) \
|
||||
devcb = &pit68230_device::set_pc_in_callback (*device, DEVCB_##_devcb);
|
||||
|
||||
#define MCFG_PIT68230_PC_OUTPUT_CB(_devcb) \
|
||||
devcb = &pit68230_device::set_pc_out_callback (*device, DEVCB_##_devcb);
|
||||
|
||||
#define MCFG_PIT68230_H1_CB(_devcb) \
|
||||
devcb = &pit68230_device::set_h1_out_callback (*device, DEVCB_##_devcb);
|
||||
|
||||
#define MCFG_PIT68230_H2_CB(_devcb) \
|
||||
devcb = &pit68230_device::set_h2_out_callback (*device, DEVCB_##_devcb);
|
||||
|
||||
#define MCFG_PIT68230_H3_CB(_devcb) \
|
||||
devcb = &pit68230_device::set_h3_out_callback (*device, DEVCB_##_devcb);
|
||||
|
||||
#define MCFG_PIT68230_H4_CB(_devcb) \
|
||||
devcb = &pit68230_device::set_h4_out_callback (*device, DEVCB_##_devcb);
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Registers RS1-RS5 R/W Description
|
||||
@ -84,46 +105,100 @@
|
||||
//**************************************************************************
|
||||
class pit68230_device : public device_t, public device_execute_interface
|
||||
{
|
||||
public:
|
||||
// construction/destruction
|
||||
pit68230_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, UINT32 variant, const char *shortname, const char *source);
|
||||
pit68230_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
|
||||
template<class _Object> static devcb_base &set_pa_wr_callback (device_t &device, _Object object)
|
||||
{
|
||||
return downcast<pit68230_device &>(device).m_write_pa.set_callback (object);
|
||||
}
|
||||
template<class _Object> static devcb_base &set_h2_wr_callback (device_t &device, _Object object)
|
||||
{
|
||||
return downcast<pit68230_device &>(device).m_write_h2.set_callback (object);
|
||||
}
|
||||
public:
|
||||
// construction/destruction
|
||||
pit68230_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, UINT32 variant, const char *shortname, const char *source);
|
||||
pit68230_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
|
||||
template<class _Object> static devcb_base &set_pa_in_callback (device_t &device, _Object object){ return downcast<pit68230_device &>(device).m_pa_in_cb.set_callback (object); }
|
||||
template<class _Object> static devcb_base &set_pa_out_callback (device_t &device, _Object object){ return downcast<pit68230_device &>(device).m_pa_out_cb.set_callback (object); }
|
||||
template<class _Object> static devcb_base &set_pb_in_callback (device_t &device, _Object object){ return downcast<pit68230_device &>(device).m_pb_in_cb.set_callback (object); }
|
||||
template<class _Object> static devcb_base &set_pb_out_callback (device_t &device, _Object object){ return downcast<pit68230_device &>(device).m_pb_out_cb.set_callback (object); }
|
||||
template<class _Object> static devcb_base &set_pc_in_callback (device_t &device, _Object object){ return downcast<pit68230_device &>(device).m_pc_in_cb.set_callback (object); }
|
||||
template<class _Object> static devcb_base &set_pc_out_callback (device_t &device, _Object object){ return downcast<pit68230_device &>(device).m_pc_out_cb.set_callback (object); }
|
||||
template<class _Object> static devcb_base &set_h1_out_callback (device_t &device, _Object object){ return downcast<pit68230_device &>(device).m_h1_out_cb.set_callback (object); }
|
||||
template<class _Object> static devcb_base &set_h2_out_callback (device_t &device, _Object object){ return downcast<pit68230_device &>(device).m_h2_out_cb.set_callback (object); }
|
||||
template<class _Object> static devcb_base &set_h3_out_callback (device_t &device, _Object object){ return downcast<pit68230_device &>(device).m_h3_out_cb.set_callback (object); }
|
||||
template<class _Object> static devcb_base &set_h4_out_callback (device_t &device, _Object object){ return downcast<pit68230_device &>(device).m_h4_out_cb.set_callback (object); }
|
||||
|
||||
DECLARE_WRITE8_MEMBER (write);
|
||||
DECLARE_READ8_MEMBER (read);
|
||||
DECLARE_WRITE8_MEMBER (write);
|
||||
DECLARE_READ8_MEMBER (read);
|
||||
|
||||
void h1_set (UINT8 state);
|
||||
void portb_setbit (UINT8 bit, UINT8 state);
|
||||
void h1_set (UINT8 state);
|
||||
void portb_setbit (UINT8 bit, UINT8 state);
|
||||
|
||||
void wr_pitreg_pgcr(UINT8 data);
|
||||
void wr_pitreg_psrr(UINT8 data);
|
||||
void wr_pitreg_paddr(UINT8 data);
|
||||
void wr_pitreg_pbddr(UINT8 data);
|
||||
void wr_pitreg_pcddr(UINT8 data);
|
||||
void wr_pitreg_pacr(UINT8 data);
|
||||
void wr_pitreg_pbcr(UINT8 data);
|
||||
void wr_pitreg_padr(UINT8 data);
|
||||
void wr_pitreg_paar(UINT8 data);
|
||||
void wr_pitreg_pbar(UINT8 data);
|
||||
void wr_pitreg_psr(UINT8 data);
|
||||
void wr_pitreg_tcr(UINT8 data);
|
||||
void wr_pitreg_cprh(UINT8 data);
|
||||
void wr_pitreg_cprm(UINT8 data);
|
||||
void wr_pitreg_cprl(UINT8 data);
|
||||
|
||||
UINT8 rr_pitreg_pgcr();
|
||||
UINT8 rr_pitreg_psrr();
|
||||
UINT8 rr_pitreg_paddr();
|
||||
UINT8 rr_pitreg_pbddr();
|
||||
UINT8 rr_pitreg_pcddr();
|
||||
UINT8 rr_pitreg_pacr();
|
||||
UINT8 rr_pitreg_pbcr();
|
||||
UINT8 rr_pitreg_padr();
|
||||
UINT8 rr_pitreg_pbdr();
|
||||
UINT8 rr_pitreg_paar();
|
||||
UINT8 rr_pitreg_pbar();
|
||||
UINT8 rr_pitreg_psr();
|
||||
UINT8 rr_pitreg_cntrh();
|
||||
UINT8 rr_pitreg_cntrm();
|
||||
UINT8 rr_pitreg_cntrl();
|
||||
|
||||
protected:
|
||||
// device-level overrides
|
||||
virtual void device_start () override;
|
||||
virtual void device_reset () override;
|
||||
virtual void device_timer (emu_timer &timer, device_timer_id id, int param, void *ptr) override;
|
||||
virtual void execute_run () override;
|
||||
int m_icount;
|
||||
devcb_write8 m_write_pa;
|
||||
devcb_write_line m_write_h2;
|
||||
|
||||
// peripheral ports
|
||||
UINT8 m_pgcr; // Port General Control register
|
||||
UINT8 m_psrr; // Port Service Request register
|
||||
UINT8 m_paddr; // Port A Data Direction register
|
||||
UINT8 m_pbddr; // Port B Data Direction register
|
||||
UINT8 m_pcddr; // Port C Data Direction register
|
||||
UINT8 m_pacr; // Port A Control register
|
||||
UINT8 m_pbcr; // Port B Control register
|
||||
UINT8 m_padr; // Port A Data register
|
||||
UINT8 m_pbdr; // Port B Data register
|
||||
UINT8 m_psr; // Port Status Register
|
||||
enum {
|
||||
REG_TCR_ENABLE = 0x01
|
||||
};
|
||||
|
||||
// device-level overrides
|
||||
virtual void device_start () override;
|
||||
virtual void device_reset () override;
|
||||
virtual void device_timer (emu_timer &timer, device_timer_id id, int param, void *ptr) override;
|
||||
virtual void execute_run () override;
|
||||
int m_icount;
|
||||
|
||||
devcb_write8 m_pa_out_cb;
|
||||
devcb_read8 m_pa_in_cb;
|
||||
devcb_write8 m_pb_out_cb;
|
||||
devcb_read8 m_pb_in_cb;
|
||||
devcb_write8 m_pc_out_cb;
|
||||
devcb_read8 m_pc_in_cb;
|
||||
devcb_write_line m_h1_out_cb;
|
||||
devcb_write_line m_h2_out_cb;
|
||||
devcb_write_line m_h3_out_cb;
|
||||
devcb_write_line m_h4_out_cb;
|
||||
|
||||
// peripheral ports
|
||||
UINT8 m_pgcr; // Port General Control register
|
||||
UINT8 m_psrr; // Port Service Request register
|
||||
UINT8 m_paddr; // Port A Data Direction register
|
||||
UINT8 m_pbddr; // Port B Data Direction register
|
||||
UINT8 m_pcddr; // Port C Data Direction register
|
||||
UINT8 m_pacr; // Port A Control register
|
||||
UINT8 m_pbcr; // Port B Control register
|
||||
UINT8 m_padr; // Port A Data register
|
||||
UINT8 m_pbdr; // Port B Data register
|
||||
UINT8 m_psr; // Port Status Register
|
||||
UINT8 m_tcr; // Timer Control Register
|
||||
int m_cpr; // Counter Preload Registers (3 x 8 = 24 bits)
|
||||
// UINT8 m_cprh; // Counter Preload Register High
|
||||
// UINT8 m_cprm; // Counter Preload Register Mid
|
||||
// UINT8 m_cprl; // Counter Preload Register Low
|
||||
int m_cntr; // - The 24 bit Counter
|
||||
};
|
||||
|
||||
// device type definition
|
||||
|
||||
1793
src/devices/machine/scnxx562.cpp
Normal file
1793
src/devices/machine/scnxx562.cpp
Normal file
File diff suppressed because it is too large
Load Diff
698
src/devices/machine/scnxx562.h
Normal file
698
src/devices/machine/scnxx562.h
Normal file
@ -0,0 +1,698 @@
|
||||
// license:BSD-3-Clause
|
||||
// copyright-holders:Joakim Larsson Edstrom
|
||||
/***************************************************************************
|
||||
|
||||
Philips DUSCC - Dual Serial Communications Controller emulation
|
||||
|
||||
****************************************************************************
|
||||
|
||||
Chan B Chan A Chan B Chan A
|
||||
======= _____ _____ ======== ======= _____ _____ ========
|
||||
IACKN 1|* \_/ |48 VCC IACKN 1|* \_/ |48 VDD
|
||||
A3 2| |47 A4 A3 2| |47 A4
|
||||
A2 3| |46 A5 A2 3| |46 A5
|
||||
A1 4| |45 A6 A1 4| |45 A6
|
||||
RTxDAK/GPI1 5| |44 RTxDAK/GPI1 5| |44 RTxDAK/GP1
|
||||
IRQN 6| |43 X1/CLK IRQN 6| |43 X1/CLK
|
||||
RDYN 7| |42 X2 RESETN 7| |42 X2
|
||||
RTS/SYNOUT 8| |41 RTS/SYNOUT 8| |41 RTS/SYNOUT
|
||||
TRxC 9| |40 TRxC TRxC 9| |40 TRxC
|
||||
RTxC 10| |39 RTxC RTxC 10| |39 RTxC
|
||||
DCD/SYNI 11| |38 DCD/SYNI 11| |38 DCD/SYNI
|
||||
RxD 12| |37 RxD RxD 12| |37 RxD
|
||||
TxD 13| SCN26562 |36 TxD TxD 13| SCN68562 |36 TxD
|
||||
TxDAK/GPI2 14| SCN26C562 |35 TxDAK/GPI2 14| SCN68C562 |35 TxDAK/GPI2
|
||||
RTxDRQ/GPO1 15| |34 RTxDRQ/GPO1 15| |34 RTxDRQ/GPO1
|
||||
TxDRQ/RTS/GPO2 16| |33 TxDRQ/RTS/GPO2 16| |33 TxDRQ/RTS/GPO2
|
||||
CTS/LC 17| |32 CTS/LC CTS/LC 17| |32 CTS/LC
|
||||
D7 18| |31 D0 D7 18| |31 D0
|
||||
D6 19| |30 D1 D6 19| |30 D1
|
||||
D5 20| |29 D2 D5 20| |29 D2
|
||||
D4 21| |28 D3 D4 21| |28 D3
|
||||
RDN 22| |27 EOPN DTACKN 22| |27 DONEN
|
||||
RESETN 23| |26 WRN DTCN 23| |26 R/WN
|
||||
GND 24|_____________|25 CEN CND 24|_____________|25 CSN
|
||||
Intel Bus Motorola Bus
|
||||
|
||||
***************************************************************************/
|
||||
|
||||
#ifndef __SCNXX562_H__
|
||||
#define __SCNXX562_H__
|
||||
|
||||
#include "emu.h"
|
||||
|
||||
//**************************************************************************
|
||||
// DEVICE CONFIGURATION MACROS
|
||||
//**************************************************************************
|
||||
|
||||
#define LOCAL_BRG 0
|
||||
|
||||
/* Variant ADD macros - use the right one to enable the right feature set! */
|
||||
#define MCFG_DUSCC26562_ADD(_tag, _clock, _rxa, _txa, _rxb, _txb) \
|
||||
MCFG_DEVICE_ADD(_tag, DUSCC26562, _clock) \
|
||||
MCFG_DUSCC_OFFSETS(_rxa, _txa, _rxb, _txb)
|
||||
|
||||
#define MCFG_DUSCC26C562_ADD(_tag, _clock, _rxa, _txa, _rxb, _txb) \
|
||||
MCFG_DEVICE_ADD(_tag, DUSCC26C562, _clock) \
|
||||
MCFG_DUSCC_OFFSETS(_rxa, _txa, _rxb, _txb)
|
||||
|
||||
#define MCFG_DUSCC68562_ADD(_tag, _clock, _rxa, _txa, _rxb, _txb) \
|
||||
MCFG_DEVICE_ADD(_tag, DUSCC68562, _clock) \
|
||||
MCFG_DUSCC_OFFSETS(_rxa, _txa, _rxb, _txb)
|
||||
|
||||
#define MCFG_DUSCC68C562_ADD(_tag, _clock, _rxa, _txa, _rxb, _txb) \
|
||||
MCFG_DEVICE_ADD(_tag, DUSCC68C562, _clock) \
|
||||
MCFG_DUSCC_OFFSETS(_rxa, _txa, _rxb, _txb)
|
||||
|
||||
/* generic ADD macro - Avoid using it directly, see above for correct variant instead */
|
||||
#define MCFG_DUSCC_ADD(_tag, _clock, _rxa, _txa, _rxb, _txb) \
|
||||
MCFG_DEVICE_ADD(_tag, DUSCC, _clock) \
|
||||
MCFG_DUSCC_OFFSETS(_rxa, _txa, _rxb, _txb)
|
||||
|
||||
/* Generic macros */
|
||||
#define MCFG_DUSCC_OFFSETS(_rxa, _txa, _rxb, _txb) \
|
||||
duscc_device::configure_channels(*device, _rxa, _txa, _rxb, _txb);
|
||||
|
||||
// Port A callbacks
|
||||
#define MCFG_DUSCC_OUT_TXDA_CB(_devcb) \
|
||||
devcb = &duscc_device::set_out_txda_callback(*device, DEVCB_##_devcb);
|
||||
|
||||
#define MCFG_DUSCC_OUT_DTRA_CB(_devcb) \
|
||||
devcb = &duscc_device::set_out_dtra_callback(*device, DEVCB_##_devcb);
|
||||
|
||||
#define MCFG_DUSCC_OUT_RTSA_CB(_devcb) \
|
||||
devcb = &duscc_device::set_out_rtsa_callback(*device, DEVCB_##_devcb);
|
||||
|
||||
#define MCFG_DUSCC_OUT_SYNCA_CB(_devcb) \
|
||||
devcb = &duscc_device::set_out_synca_callback(*device, DEVCB_##_devcb);
|
||||
|
||||
// Port B callbacks
|
||||
#define MCFG_DUSCC_OUT_TXDB_CB(_devcb) \
|
||||
devcb = &duscc_device::set_out_txdb_callback(*device, DEVCB_##_devcb);
|
||||
|
||||
#define MCFG_DUSCC_OUT_DTRB_CB(_devcb) \
|
||||
devcb = &duscc_device::set_out_dtrb_callback(*device, DEVCB_##_devcb);
|
||||
|
||||
#define MCFG_DUSCC_OUT_RTSB_CB(_devcb) \
|
||||
devcb = &duscc_device::set_out_rtsb_callback(*device, DEVCB_##_devcb);
|
||||
|
||||
#define MCFG_DUSCC_OUT_SYNCB_CB(_devcb) \
|
||||
devcb = &duscc_device::set_out_syncb_callback(*device, DEVCB_##_devcb);
|
||||
|
||||
|
||||
|
||||
//**************************************************************************
|
||||
// TYPE DEFINITIONS
|
||||
//**************************************************************************
|
||||
|
||||
// ======================> duscc_channel
|
||||
|
||||
class duscc_device;
|
||||
|
||||
class duscc_channel : public device_t,
|
||||
public device_serial_interface
|
||||
{
|
||||
friend class duscc_device;
|
||||
|
||||
public:
|
||||
duscc_channel(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
|
||||
|
||||
// device-level overrides
|
||||
virtual void device_start() override;
|
||||
virtual void device_reset() override;
|
||||
virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr) override;
|
||||
|
||||
// device_serial_interface overrides
|
||||
virtual void tra_callback() override;
|
||||
virtual void tra_complete() override;
|
||||
virtual void rcv_callback() override;
|
||||
virtual void rcv_complete() override;
|
||||
|
||||
// read register handlers
|
||||
UINT8 do_dusccreg_cmr1_r();
|
||||
UINT8 do_dusccreg_cmr2_r();
|
||||
UINT8 do_dusccreg_s1r_r();
|
||||
UINT8 do_dusccreg_s2r_r();
|
||||
UINT8 do_dusccreg_tpr_r();
|
||||
UINT8 do_dusccreg_ttr_r();
|
||||
UINT8 do_dusccreg_rpr_r();
|
||||
UINT8 do_dusccreg_rtr_r();
|
||||
UINT8 do_dusccreg_ctprh_r();
|
||||
UINT8 do_dusccreg_ctprl_r();
|
||||
UINT8 do_dusccreg_ctcr_r();
|
||||
UINT8 do_dusccreg_omr_r();
|
||||
UINT8 do_dusccreg_cth_r();
|
||||
UINT8 do_dusccreg_ctl_r();
|
||||
UINT8 do_dusccreg_pcr_r();
|
||||
UINT8 do_dusccreg_ccr_r();
|
||||
UINT8 do_dusccreg_rxfifo_r();
|
||||
UINT8 do_dusccreg_rsr_r();
|
||||
UINT8 do_dusccreg_trsr_r();
|
||||
UINT8 do_dusccreg_ictsr_r();
|
||||
UINT8 do_dusccreg_gsr_r();
|
||||
UINT8 do_dusccreg_ier_r();
|
||||
UINT8 do_dusccreg_cid_r();
|
||||
UINT8 do_dusccreg_ivr_r();
|
||||
UINT8 do_dusccreg_icr_r();
|
||||
UINT8 do_dusccreg_ivrm_r();
|
||||
UINT8 do_dusccreg_mrr_r();
|
||||
UINT8 do_dusccreg_ier1_r();
|
||||
UINT8 do_dusccreg_ier2_r();
|
||||
UINT8 do_dusccreg_ier3_r();
|
||||
UINT8 do_dusccreg_trcr_r();
|
||||
UINT8 do_dusccreg_rflr_r();
|
||||
UINT8 do_dusccreg_ftlr_r();
|
||||
UINT8 do_dusccreg_trmsr_r();
|
||||
UINT8 do_dusccreg_telr_r();
|
||||
|
||||
// write register handlers
|
||||
void do_dusccreg_cmr1_w(UINT8 data);
|
||||
void do_dusccreg_cmr2_w(UINT8 data);
|
||||
void do_dusccreg_s1r_w(UINT8 data);
|
||||
void do_dusccreg_s2r_w(UINT8 data);
|
||||
void do_dusccreg_tpr_w(UINT8 data);
|
||||
void do_dusccreg_ttr_w(UINT8 data);
|
||||
void do_dusccreg_rpr_w(UINT8 data);
|
||||
void do_dusccreg_rtr_w(UINT8 data);
|
||||
void do_dusccreg_ctprh_w(UINT8 data);
|
||||
void do_dusccreg_ctprl_w(UINT8 data);
|
||||
void do_dusccreg_ctcr_w(UINT8 data);
|
||||
void do_dusccreg_omr_w(UINT8 data);
|
||||
void do_dusccreg_pcr_w(UINT8 data);
|
||||
void do_dusccreg_ccr_w(UINT8 data);
|
||||
void do_dusccreg_txfifo_w(UINT8 data);
|
||||
void do_dusccreg_rsr_w(UINT8 data);
|
||||
void do_dusccreg_trsr_w(UINT8 data);
|
||||
void do_dusccreg_ictsr_w(UINT8 data);
|
||||
void do_dusccreg_gsr_w(UINT8 data);
|
||||
void do_dusccreg_ier_w(UINT8 data);
|
||||
// void do_dusccreg_rea_w(UINT8 data); // Short cutted non complex feature
|
||||
void do_dusccreg_ivr_w(UINT8 data);
|
||||
void do_dusccreg_icr_w(UINT8 data);
|
||||
// void do_dusccreg_sea_w(UINT8 data); // Short cutted non complex feature
|
||||
void do_dusccreg_mrr_w(UINT8 data);
|
||||
void do_dusccreg_ier1_w(UINT8 data);
|
||||
void do_dusccreg_ier2_w(UINT8 data);
|
||||
void do_dusccreg_ier3_w(UINT8 data);
|
||||
void do_dusccreg_trcr_w(UINT8 data);
|
||||
void do_dusccreg_ftlr_w(UINT8 data);
|
||||
void do_dusccreg_trmsr_w(UINT8 data);
|
||||
|
||||
UINT8 read(offs_t &offset);
|
||||
void write(UINT8 data, offs_t &offset);
|
||||
|
||||
// UINT8 data_read();
|
||||
// void data_write(UINT8 data);
|
||||
|
||||
void receive_data(UINT8 data);
|
||||
void m_tx_fifo_rp_step();
|
||||
void m_rx_fifo_rp_step();
|
||||
UINT8 m_rx_fifo_rp_data();
|
||||
|
||||
DECLARE_WRITE_LINE_MEMBER( write_rx );
|
||||
DECLARE_WRITE_LINE_MEMBER( cts_w );
|
||||
DECLARE_WRITE_LINE_MEMBER( dcd_w );
|
||||
DECLARE_WRITE_LINE_MEMBER( ri_w );
|
||||
DECLARE_WRITE_LINE_MEMBER( rxc_w );
|
||||
DECLARE_WRITE_LINE_MEMBER( txc_w );
|
||||
DECLARE_WRITE_LINE_MEMBER( sync_w );
|
||||
|
||||
int m_rxc;
|
||||
int m_txc;
|
||||
int m_tra;
|
||||
int m_rcv;
|
||||
|
||||
// Register state
|
||||
UINT8 m_cmr1;
|
||||
UINT8 m_cmr2;
|
||||
UINT8 m_s1r;
|
||||
UINT8 m_s2r;
|
||||
UINT8 m_tpr;
|
||||
UINT8 m_ttr;
|
||||
UINT8 m_rpr;
|
||||
UINT8 m_rtr;
|
||||
UINT8 m_ctprh;
|
||||
UINT8 m_ctprl;
|
||||
UINT8 m_ctcr;
|
||||
UINT8 m_omr;
|
||||
UINT8 m_cth;
|
||||
UINT8 m_ctl;
|
||||
UINT8 m_pcr;
|
||||
UINT8 m_ccr;
|
||||
UINT8 m_txfifo[4];
|
||||
UINT8 m_rxfifo[4];
|
||||
UINT8 m_rsr;
|
||||
UINT8 m_trsr;
|
||||
UINT8 m_ictsr;
|
||||
UINT8 m_gsr;
|
||||
UINT8 m_ier;
|
||||
// UINT8 m_rea;
|
||||
UINT8 m_cid;
|
||||
UINT8 m_ivr;
|
||||
UINT8 m_icr;
|
||||
// UINT8 m_sea;
|
||||
UINT8 m_ivrm;
|
||||
UINT8 m_mrr;
|
||||
UINT8 m_ier1;
|
||||
UINT8 m_ier2;
|
||||
UINT8 m_ier3;
|
||||
UINT8 m_trcr;
|
||||
UINT8 m_rflr;
|
||||
UINT8 m_ftlr;
|
||||
UINT8 m_trmsr;
|
||||
UINT8 m_telr;
|
||||
|
||||
protected:
|
||||
enum
|
||||
{
|
||||
INT_TRANSMIT = 0,
|
||||
INT_EXTERNAL = 1,
|
||||
INT_RECEIVE = 2,
|
||||
INT_SPECIAL = 3
|
||||
};
|
||||
|
||||
enum
|
||||
{
|
||||
REG_CCR_RESET_TX = 0x00,
|
||||
REG_CCR_ENABLE_TX = 0x02,
|
||||
REG_CCR_DISABLE_TX = 0x03,
|
||||
REG_CCR_RESET_RX = 0x40,
|
||||
REG_CCR_ENABLE_RX = 0x42,
|
||||
REG_CCR_DISABLE_RX = 0x43
|
||||
};
|
||||
|
||||
enum
|
||||
{
|
||||
REG_CMR1_PARITY = 0x20,
|
||||
REG_CMR1_PMMODE_MASK = 0x18,
|
||||
REG_CMR1_PMMODE_NONE = 0x00,
|
||||
REG_CMR1_PMMODE_RES = 0x01,
|
||||
REG_CMR1_PMMODE_PARITY = 0x10,
|
||||
REG_CMR1_PMMODE_FORCED = 0x11,
|
||||
REG_CMR1_CPMODE_MASK = 0x07,
|
||||
REG_CMR1_CPMODE_ASYNC = 0x07
|
||||
};
|
||||
|
||||
enum
|
||||
{
|
||||
REG_CMR2_DTI_MASK = 0x38,
|
||||
REG_CMR2_DTI_NODMA = 0x38
|
||||
};
|
||||
|
||||
enum
|
||||
{
|
||||
REG_RPR_DATA_BITS_MASK = 0x03,
|
||||
REG_RPR_DATA_BITS_5BIT = 0x00,
|
||||
REG_RPR_DATA_BITS_6BIT = 0x01,
|
||||
REG_RPR_DATA_BITS_7BIT = 0x02,
|
||||
REG_RPR_DATA_BITS_8BIT = 0x03,
|
||||
REG_RPR_DCD = 0x04,
|
||||
REG_RPR_STRIP_PARITY = 0x08,
|
||||
REG_RPR_RTS = 0x10
|
||||
};
|
||||
|
||||
enum
|
||||
{
|
||||
REG_TPR_DATA_BITS_MASK = 0x03,
|
||||
REG_TPR_DATA_BITS_5BIT = 0x00,
|
||||
REG_TPR_DATA_BITS_6BIT = 0x01,
|
||||
REG_TPR_DATA_BITS_7BIT = 0x02,
|
||||
REG_TPR_DATA_BITS_8BIT = 0x03,
|
||||
REG_TPR_CTS = 0x04,
|
||||
REG_TPR_RTS = 0x08,
|
||||
REG_TPR_STOP_BITS_MASK = 0xf0
|
||||
};
|
||||
|
||||
enum
|
||||
{
|
||||
REG_TTR_EXT = 0x80,
|
||||
REG_TTR_TXCLK_MASK = 0x70,
|
||||
REG_TTR_TXCLK_1XEXT = 0x00,
|
||||
REG_TTR_TXCLK_16XEXT = 0x10,
|
||||
REG_TTR_TXCLK_DPLL = 0x20,
|
||||
REG_TTR_TXCLK_BRG = 0x30,
|
||||
REG_TTR_TXCLK_2X_OTHER = 0x40,
|
||||
REG_TTR_TXCLK_32X_OTHER = 0x50,
|
||||
REG_TTR_TXCLK_2X_OWN = 0x60,
|
||||
REG_TTR_TXCLK_32X_OWN = 0x70,
|
||||
REG_TTR_BRG_RATE_MASK = 0x0f,
|
||||
};
|
||||
|
||||
enum
|
||||
{
|
||||
REG_RTR_EXT = 0x80,
|
||||
REG_RTR_RXCLK_MASK = 0x70,
|
||||
REG_RTR_RXCLK_1XEXT = 0x00,
|
||||
REG_RTR_RXCLK_16XEXT = 0x10,
|
||||
REG_RTR_RXCLK_BRG = 0x20,
|
||||
REG_RTR_RXCLK_CT = 0x30,
|
||||
REG_RTR_RXCLK_DPLL_64X_X1 = 0x40,
|
||||
REG_RTR_RXCLK_DPLL_32X_EXT = 0x50,
|
||||
REG_RTR_RXCLK_DPLL_32X_BRG = 0x60,
|
||||
REG_RTR_RXCLK_DPLL_32X_CT = 0x70,
|
||||
REG_RTR_BRG_RATE_MASK = 0x0f,
|
||||
};
|
||||
|
||||
enum
|
||||
{
|
||||
REG_PCR_X2_IDC = 0x80,
|
||||
REG_PCR_GP02_RTS = 0x40,
|
||||
REG_PCR_SYNOUT_RTS = 0x20,
|
||||
REG_PCR_RTXC_MASK = 0x18,
|
||||
REG_PCR_RTXC_INPUT = 0x00,
|
||||
REG_PCR_RTXC_CNTR_OUT = 0x08,
|
||||
REG_PCR_RTXC_TXCLK_OUT = 0x10,
|
||||
REG_PCR_RTXC_RXCLK_OUT = 0x18,
|
||||
REG_PCR_TRXC_MASK = 0x07,
|
||||
REG_PCR_TRXC_INPUT = 0x00,
|
||||
REG_PCR_TRXC_CRYST_OUT = 0x01,
|
||||
REG_PCR_TRXC_DPLL_OUT = 0x02,
|
||||
REG_PCR_TRXC_CNTR_OUT = 0x03,
|
||||
REG_PCR_TRXC_TXBRG_OUT = 0x04,
|
||||
REG_PCR_TRXC_RXBRG_OUT = 0x05,
|
||||
REG_PCR_TRXC_TXCLK_OUT = 0x06,
|
||||
REG_PCR_TRXC_RXCLK_OUT = 0x07,
|
||||
};
|
||||
|
||||
enum
|
||||
{
|
||||
REG_OMR_TXRCL_MASK = 0xe0,
|
||||
REG_OMR_TXRCL_8BIT = 0xe0,
|
||||
REG_OMR_TXRDY_ACTIVATED = 0x10,
|
||||
REG_OMR_RXRDY_ACTIVATED = 0x08,
|
||||
REG_OMR_GP02 = 0x04,
|
||||
REG_OMR_GP01 = 0x02,
|
||||
REG_OMR_RTS = 0x01,
|
||||
};
|
||||
|
||||
enum
|
||||
{
|
||||
REG_RSR_OVERRUN_ERROR = 0x20,
|
||||
};
|
||||
|
||||
enum
|
||||
{
|
||||
REG_ICTSR_DELTA_CTS = 0x10,
|
||||
REG_ICTSR_DCD = 0x08,
|
||||
REG_ICTSR_CTS = 0x04,
|
||||
};
|
||||
|
||||
enum
|
||||
{
|
||||
REG_GSR_CHAN_A_RXREADY = 0x01,
|
||||
REG_GSR_CHAN_B_RXREADY = 0x10,
|
||||
REG_GSR_CHAN_A_TXREADY = 0x02,
|
||||
REG_GSR_CHAN_B_TXREADY = 0x20,
|
||||
};
|
||||
|
||||
// Register offsets, stripped from channel bit 0x20 but including A7 bit
|
||||
enum
|
||||
{
|
||||
REG_CMR1 = 0x00,
|
||||
REG_CMR2 = 0x01,
|
||||
REG_S1R = 0x02,
|
||||
REG_S2R = 0x03,
|
||||
REG_TPR = 0x04,
|
||||
REG_TTR = 0x05,
|
||||
REG_RPR = 0x06,
|
||||
REG_RTR = 0x07,
|
||||
REG_CTPRH = 0x08,
|
||||
REG_CTPRL = 0x09,
|
||||
REG_CTCR = 0x0a,
|
||||
REG_OMR = 0x0b,
|
||||
REG_CTH = 0x0c,
|
||||
REG_CTL = 0x0d,
|
||||
REG_PCR = 0x0e,
|
||||
REG_CCR = 0x0f,
|
||||
REG_TXFIFO_0= 0x10,
|
||||
REG_TXFIFO_1= 0x11,
|
||||
REG_TXFIFO_2= 0x12,
|
||||
REG_TXFIFO_3= 0x13,
|
||||
REG_RXFIFO_0= 0x14,
|
||||
REG_RXFIFO_1= 0x15,
|
||||
REG_RXFIFO_2= 0x16,
|
||||
REG_RXFIFO_3= 0x17,
|
||||
REG_RSR = 0x18,
|
||||
REG_TRSR = 0x19,
|
||||
REG_ICTSR = 0x1a,
|
||||
REG_GSR = 0x1b,
|
||||
REG_IER = 0x1c,
|
||||
REG_REA = 0x1d,
|
||||
REG_CID = 0x1d,
|
||||
REG_IVR = 0x1e,
|
||||
REG_ICR = 0x1f,
|
||||
REG_SEA = 0x1d,
|
||||
REG_IVRM = 0x1e,
|
||||
REG_MRR = 0x1f,
|
||||
REG_IER1 = 0x42,
|
||||
REG_IER2 = 0x43,
|
||||
REG_IER3 = 0x45,
|
||||
REG_TRCR = 0x47,
|
||||
REG_RFLR = 0x4e,
|
||||
REG_FTLR = 0x5c,
|
||||
REG_TRMSR = 0x5e,
|
||||
REG_TELR = 0x5f,
|
||||
};
|
||||
|
||||
enum
|
||||
{
|
||||
TIMER_ID_BAUD,
|
||||
TIMER_ID_XTAL,
|
||||
TIMER_ID_RTXC,
|
||||
TIMER_ID_TRXC
|
||||
};
|
||||
|
||||
UINT16 m_brg_rx_rate;
|
||||
UINT16 m_brg_tx_rate;
|
||||
UINT16 m_brg_const;
|
||||
|
||||
// TODO: Implement the 14.4K, 56K and 64K bauds available on the CDUSCC
|
||||
static unsigned int get_baudrate(unsigned int br)
|
||||
{
|
||||
switch (br)
|
||||
{
|
||||
case 0x00: return 50; break;
|
||||
case 0x01: return 75; break;
|
||||
case 0x02: return 110; break;
|
||||
case 0x03: return 134; break;
|
||||
case 0x04: return 150; break;
|
||||
case 0x05: return 200; break;
|
||||
case 0x06: return 300; break;
|
||||
case 0x07: return 600; break;
|
||||
case 0x08: return 1050; break;
|
||||
case 0x09: return 1200; break;
|
||||
case 0x0a: return 2000; break;
|
||||
case 0x0b: return 2400; break;
|
||||
case 0x0c: return 4800; break;
|
||||
case 0x0d: return 9600; break;
|
||||
case 0x0e: return 19200; break;
|
||||
case 0x0f: return 38400; break;
|
||||
};
|
||||
return 0;
|
||||
}
|
||||
|
||||
void update_serial();
|
||||
void set_dtr(int state);
|
||||
void set_rts(int state);
|
||||
|
||||
int get_tx_clock_mode();
|
||||
int get_rx_clock_mode();
|
||||
stop_bits_t get_stop_bits();
|
||||
int get_rx_word_length();
|
||||
int get_tx_word_length();
|
||||
|
||||
/* FIFOs and rx/tx status */
|
||||
/* Receiver */
|
||||
UINT8 m_rx_data_fifo[16]; // data FIFO
|
||||
UINT8 m_rx_error_fifo[16]; // error FIFO
|
||||
int m_rx_fifo_rp; // FIFO read pointer
|
||||
int m_rx_fifo_wp; // FIFO write pointer
|
||||
int m_rx_fifo_sz; // FIFO size
|
||||
UINT8 m_rx_error; // current error
|
||||
|
||||
/* Transmitter */
|
||||
UINT8 m_tx_data_fifo[16]; // data FIFO
|
||||
UINT8 m_tx_error_fifo[16]; // error FIFO
|
||||
int m_tx_fifo_rp; // FIFO read pointer
|
||||
int m_tx_fifo_wp; // FIFO write pointer
|
||||
int m_tx_fifo_sz; // FIFO size
|
||||
UINT8 m_tx_error; // current error
|
||||
|
||||
int m_rx_clock; // receive clock pulse count
|
||||
int m_rx_first; // first character received
|
||||
int m_rx_break; // receive break condition
|
||||
// UINT8 m_rx_rr0_latch; // read register 0 latched
|
||||
|
||||
int m_rxd;
|
||||
int m_ri; // ring indicator latch
|
||||
int m_cts; // clear to send latch
|
||||
int m_dcd; // data carrier detect latch
|
||||
|
||||
// transmitter state
|
||||
UINT8 m_tx_data; // transmit data register
|
||||
int m_tx_clock; // transmit clock pulse count
|
||||
|
||||
int m_dtr; // data terminal ready
|
||||
int m_rts; // request to send
|
||||
|
||||
// synchronous state
|
||||
UINT16 m_sync; // sync character
|
||||
|
||||
int m_rcv_mode;
|
||||
int m_index;
|
||||
duscc_device *m_uart;
|
||||
|
||||
// CDUSCC specifics
|
||||
int m_a7; // Access additional registers
|
||||
};
|
||||
|
||||
|
||||
// ======================> duscc_device
|
||||
|
||||
|
||||
class duscc_device : public device_t
|
||||
// ,public device_z80daisy_interface
|
||||
{
|
||||
friend class duscc_channel;
|
||||
|
||||
public:
|
||||
// construction/destruction
|
||||
duscc_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, UINT32 variant, const char *shortname, const char *source);
|
||||
duscc_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
|
||||
|
||||
template<class _Object> static devcb_base &set_out_txda_callback(device_t &device, _Object object) { return downcast<duscc_device &>(device).m_out_txda_cb.set_callback(object); }
|
||||
template<class _Object> static devcb_base &set_out_dtra_callback(device_t &device, _Object object) { return downcast<duscc_device &>(device).m_out_dtra_cb.set_callback(object); }
|
||||
template<class _Object> static devcb_base &set_out_rtsa_callback(device_t &device, _Object object) { return downcast<duscc_device &>(device).m_out_rtsa_cb.set_callback(object); }
|
||||
template<class _Object> static devcb_base &set_out_synca_callback(device_t &device, _Object object) { return downcast<duscc_device &>(device).m_out_synca_cb.set_callback(object); }
|
||||
|
||||
template<class _Object> static devcb_base &set_out_txdb_callback(device_t &device, _Object object) { return downcast<duscc_device &>(device).m_out_txdb_cb.set_callback(object); }
|
||||
template<class _Object> static devcb_base &set_out_dtrb_callback(device_t &device, _Object object) { return downcast<duscc_device &>(device).m_out_dtrb_cb.set_callback(object); }
|
||||
template<class _Object> static devcb_base &set_out_rtsb_callback(device_t &device, _Object object) { return downcast<duscc_device &>(device).m_out_rtsb_cb.set_callback(object); }
|
||||
template<class _Object> static devcb_base &set_out_syncb_callback(device_t &device, _Object object) { return downcast<duscc_device &>(device).m_out_syncb_cb.set_callback(object); }
|
||||
|
||||
static void configure_channels(device_t &device, int rxa, int txa, int rxb, int txb)
|
||||
{
|
||||
#if 0 // TODO: Fix this, need a way to set external rx/tx clocks for the channels
|
||||
duscc_device &dev = downcast<duscc_device &>(device);
|
||||
dev.m_chanA->m_rxc = rxa;
|
||||
dev.m_chanA->m_txc = txa;
|
||||
dev.m_chanB->m_rxc = rxb;
|
||||
dev.m_chanB->m_txc = txb;
|
||||
#endif
|
||||
}
|
||||
|
||||
DECLARE_READ8_MEMBER( read );
|
||||
DECLARE_WRITE8_MEMBER( write );
|
||||
|
||||
// interrupt acknowledge
|
||||
// int m1_r();
|
||||
|
||||
DECLARE_WRITE_LINE_MEMBER( rxa_w ) { m_chanA->write_rx(state); }
|
||||
DECLARE_WRITE_LINE_MEMBER( rxb_w ) { m_chanB->write_rx(state); }
|
||||
DECLARE_WRITE_LINE_MEMBER( ctsa_w ) { m_chanA->cts_w(state); }
|
||||
DECLARE_WRITE_LINE_MEMBER( ctsb_w ) { m_chanB->cts_w(state); }
|
||||
DECLARE_WRITE_LINE_MEMBER( dcda_w ) { m_chanA->dcd_w(state); }
|
||||
DECLARE_WRITE_LINE_MEMBER( dcdb_w ) { m_chanB->dcd_w(state); }
|
||||
DECLARE_WRITE_LINE_MEMBER( ria_w ) { m_chanA->ri_w(state); }
|
||||
DECLARE_WRITE_LINE_MEMBER( rib_w ) { m_chanB->ri_w(state); }
|
||||
#if 0
|
||||
DECLARE_WRITE_LINE_MEMBER( rxca_w ) { m_chanA->rxc_w(state); }
|
||||
DECLARE_WRITE_LINE_MEMBER( rxcb_w ) { m_chanB->rxc_w(state); }
|
||||
DECLARE_WRITE_LINE_MEMBER( txca_w ) { m_chanA->txc_w(state); }
|
||||
DECLARE_WRITE_LINE_MEMBER( txcb_w ) { m_chanB->txc_w(state); }
|
||||
DECLARE_WRITE_LINE_MEMBER( rxtxcb_w ) { m_chanB->rxc_w(state); m_chanB->txc_w(state); }
|
||||
#endif
|
||||
DECLARE_WRITE_LINE_MEMBER( synca_w ) { m_chanA->sync_w(state); }
|
||||
DECLARE_WRITE_LINE_MEMBER( syncb_w ) { m_chanB->sync_w(state); }
|
||||
|
||||
protected:
|
||||
// device-level overrides
|
||||
virtual void device_start() override;
|
||||
virtual void device_reset() override;
|
||||
virtual machine_config_constructor device_mconfig_additions() const override;
|
||||
|
||||
// internal interrupt management
|
||||
void check_interrupts();
|
||||
void reset_interrupts();
|
||||
UINT8 modify_vector(UINT8 vect, int i, UINT8 src);
|
||||
void trigger_interrupt(int index, int state);
|
||||
int get_channel_index(duscc_channel *ch) { return (ch == m_chanA) ? 0 : 1; }
|
||||
|
||||
// Variants in the DUSCC family
|
||||
enum
|
||||
{
|
||||
TYPE_DUSCC = 0x001,
|
||||
TYPE_DUSCC26562 = 0x002,
|
||||
TYPE_DUSCC26C562 = 0x004,
|
||||
TYPE_DUSCC68562 = 0x008,
|
||||
TYPE_DUSCC68C562 = 0x010,
|
||||
};
|
||||
|
||||
#define SET_NMOS ( duscc_device::TYPE_DUSCC26562 | duscc_device::TYPE_DUSCC68562 )
|
||||
#define SET_CMOS ( duscc_device::TYPE_DUSCC26C562 | duscc_device::TYPE_DUSCC68C562 )
|
||||
|
||||
enum
|
||||
{
|
||||
CHANNEL_A = 0,
|
||||
CHANNEL_B
|
||||
};
|
||||
|
||||
required_device<duscc_channel> m_chanA;
|
||||
required_device<duscc_channel> m_chanB;
|
||||
|
||||
// internal state
|
||||
#if 0
|
||||
int m_rxca;
|
||||
int m_txca;
|
||||
int m_rxcb;
|
||||
int m_txcb;
|
||||
#endif
|
||||
|
||||
devcb_write_line m_out_txda_cb;
|
||||
devcb_write_line m_out_dtra_cb;
|
||||
devcb_write_line m_out_rtsa_cb;
|
||||
devcb_write_line m_out_synca_cb;
|
||||
|
||||
devcb_write_line m_out_txdb_cb;
|
||||
devcb_write_line m_out_dtrb_cb;
|
||||
devcb_write_line m_out_rtsb_cb;
|
||||
devcb_write_line m_out_syncb_cb;
|
||||
|
||||
int m_int_state[6]; // interrupt state
|
||||
|
||||
int m_variant;
|
||||
};
|
||||
|
||||
// device type definition
|
||||
extern const device_type DUSCC;
|
||||
extern const device_type DUSCC_CHANNEL;
|
||||
extern const device_type DUSCC26562;
|
||||
extern const device_type DUSCC26C562;
|
||||
extern const device_type DUSCC68562;
|
||||
extern const device_type DUSCC68C562;
|
||||
|
||||
class duscc26562_device : public duscc_device
|
||||
{
|
||||
public :
|
||||
duscc26562_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
|
||||
};
|
||||
|
||||
class duscc26C562_device : public duscc_device
|
||||
{
|
||||
public :
|
||||
duscc26C562_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
|
||||
};
|
||||
|
||||
class duscc68562_device : public duscc_device
|
||||
{
|
||||
public :
|
||||
duscc68562_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
|
||||
};
|
||||
|
||||
class duscc68C562_device : public duscc_device
|
||||
{
|
||||
public :
|
||||
duscc68C562_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
|
||||
};
|
||||
|
||||
#endif // __SCNXX562_H__
|
||||
802
src/mame/drivers/fccpu30.cpp
Normal file
802
src/mame/drivers/fccpu30.cpp
Normal file
@ -0,0 +1,802 @@
|
||||
// license:BSD-3-Clause
|
||||
// copyright-holders:Joakim Larsson Edstrom
|
||||
/***************************************************************************
|
||||
*
|
||||
* Force SYS68K CPU-30 VME SBC drivers
|
||||
*
|
||||
* 21/05/2016
|
||||
*
|
||||
* Thanks to Al Kossow his site http://www.bitsavers.org/ I got the information
|
||||
* required to start the work with this driver.
|
||||
*
|
||||
* The driver is currently starting up and the Boot ROM asks for input do start FGA-002
|
||||
* diagnostics and do SRAM setup, which it does. After that it jumps to zeroed memory
|
||||
* and crashes so needs some more work to be useful
|
||||
*
|
||||
*
|
||||
* ||
|
||||
* || || CPU-30
|
||||
* ||||--||_____________________________________________________________
|
||||
* ||||--|| |
|
||||
* || || _ |__
|
||||
* || | | |
|
||||
* || | | |
|
||||
* || | | |
|
||||
* || | | |
|
||||
* || | | |
|
||||
* || | | |
|
||||
* || | |VME|
|
||||
* || | | |
|
||||
* || | |P1 |
|
||||
* || | | |
|
||||
* || | | |
|
||||
* || | | |
|
||||
* || | | |
|
||||
* || | | |
|
||||
* || | | |
|
||||
* || |_| |
|
||||
* || |___|
|
||||
* || |
|
||||
* || |
|
||||
* || |
|
||||
* || |
|
||||
* || |
|
||||
* || |
|
||||
* || |
|
||||
* || |
|
||||
* || |___
|
||||
* || _| |
|
||||
* || | | |
|
||||
* || | | |
|
||||
* || | | |
|
||||
* || | | |
|
||||
* || | |VME|
|
||||
* || | | |
|
||||
* || | |P2 |
|
||||
* || | | |
|
||||
* || | | |
|
||||
* || | | |
|
||||
* || | | |
|
||||
* || | | |
|
||||
* || | | |
|
||||
* || | | |
|
||||
* || | | |
|
||||
* || |_| |
|
||||
* || |___|
|
||||
* || || +
|
||||
* ||||--|| |
|
||||
* ||||--||--------------------------------------------------------------+
|
||||
* ||
|
||||
*
|
||||
* History of Force Computers
|
||||
*---------------------------
|
||||
*
|
||||
* Misc links about Force Computes and this board:
|
||||
*------------------------------------------------
|
||||
* http://bitsavers.trailing-edge.com/pdf/forceComputers/CPU30/204030_CPU-30_R4_Technical_Reference_Oct96.pdf
|
||||
* http://www.artisantg.com/info/P_wUovN.pdf
|
||||
*
|
||||
* Description(s)
|
||||
* -------------
|
||||
* CPU-30 has the following feature set
|
||||
* - 16.7 or 25 MHz MC68030 enhanced 32-bit microprocessor
|
||||
* - 16.7 or 25 MHz MC68882 floating-point coprocessor
|
||||
* - 32-512 Kb of SRAM with battery backup
|
||||
* - 4, 8, 16, or 32MB of shared DRAM, with byte parity
|
||||
* - Up to 8Mb Flash memory
|
||||
* - 128,256 or 512 Mb boot flash or upto 1Mb of boot OTP PROM
|
||||
* - Double High (6U) VMEmodule
|
||||
* - A32/D32 VMEbus master/slave interface with system controller function (VMEchip ASIC)
|
||||
* - Ethernet transceiver interface (AM79C90)
|
||||
* - SCSI bus interface with independent data bus on P2 connector (MB87033/34)
|
||||
* - Flopyy disk interface on P2 connector (FCD37C65C)
|
||||
* - Four serial ports (DUSCC SCN68562 x 2)
|
||||
* - 20 bit digital i/o for user applications( 2 x 68230 PI/T )
|
||||
* - Real-Time Clock with interrupt (72423)
|
||||
* - 4-level requester, 7-level interrupter, and 7-level interrupt handler for VMEbus (VMEchip ASIC)
|
||||
*
|
||||
* NOTE: This driver currently mimics the CPU-30xyz configuration: 16MHz, 4Mb RAM, no parity, no ethernet (See TODO)
|
||||
*
|
||||
* Address Map
|
||||
* --------------------------------------------------------------------------
|
||||
* Range Decscription
|
||||
* --------------------------------------------------------------------------
|
||||
* 00000000-0xxFFFFF Shared DRAM D8-D32 xx=0x1F-0x03 for 32Mb-4Mb
|
||||
* 0yy00000-FAFFFFFF VME A32 D8-D32 yy=xx+1
|
||||
* FB000000-FBFEFFFF VME A24 D8-D32
|
||||
* FBFF0000-FBFFFFFF VME A16 D8-D32
|
||||
* FC000000-FCFEFFFF VME A24 D8-D16
|
||||
* FCFF0000-FCFFFFFF VME A16 D8-D16
|
||||
* FD000000-FEEFFFFF Reserved
|
||||
* FEF00000-FEF7FFFF LAN RAM D8-D32
|
||||
* FEF80000-FEFFFFFF LAN Controller D16 (AM79C90)
|
||||
* FF000000-FF7FFFFF System PROM D8-D32 (read) D32 (flash write)
|
||||
* FF800000-FF800BFF Reserved
|
||||
* FF800C00-FF800DFF PIT1 D8 (68230)
|
||||
* FF800E00-FF800FFF PIT2 D8 (68230)
|
||||
* FF801000-FF801FFF Reserved
|
||||
* FF802000-FF8021FF DUSCC1 D8 (SCN68562)
|
||||
* FF802200-FF8023FF DUSCC2 D8 (SCN68562)
|
||||
* FF802400-FF802FFF Reserved
|
||||
* FF803000-FF8031FF RTC (72423) D8
|
||||
* FF803200-FF8033FF Reserved
|
||||
* FF803400-FF8035FF SCSI controller (MB87033/34) D8
|
||||
* FF803600-FF8037FF Reserved
|
||||
* FF803800-FF80397F Floppy controller (FDC37C65C) D8
|
||||
* FF803980-FF8039FF Slot 1 status register (read) D8
|
||||
* FFC00000-FFCFFFFF Local SRAM D8-D32
|
||||
* FFD00000-FFDFFFFF FGA-002 Gate Array D8-D32
|
||||
* FFE00000-FFEFFFFF Boot PROM D8-D32
|
||||
* FFF00000-FFFFFFFF Reserved
|
||||
* --------------------------------------------------------------------------
|
||||
*
|
||||
* Interrupt sources MVME
|
||||
* ----------------------------------------------------------
|
||||
* Description Device Lvl IRQ VME board
|
||||
* /Board Vector Address
|
||||
* ----------------------------------------------------------
|
||||
* On board Sources
|
||||
*
|
||||
* Off board Sources (other VME boards)
|
||||
*
|
||||
* ----------------------------------------------------------
|
||||
*
|
||||
* DMAC Channel Assignments
|
||||
* ----------------------------------------------------------
|
||||
* Channel MVME147
|
||||
* ----------------------------------------------------------
|
||||
*
|
||||
*
|
||||
* TODO:
|
||||
* - Investigate and fix crash
|
||||
* - Add VxWorks proms
|
||||
* - Add more devices
|
||||
* - Write VME device
|
||||
* - Add variants of boards
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#include "emu.h"
|
||||
#include "cpu/m68000/m68000.h"
|
||||
#include "machine/scnxx562.h"
|
||||
#include "machine/68230pit.h"
|
||||
#include "machine/nvram.h"
|
||||
#include "bus/rs232/rs232.h"
|
||||
#include "machine/clock.h"
|
||||
//#include "machine/timekpr.h"
|
||||
|
||||
#define VERBOSE 0
|
||||
|
||||
#define LOG(x) do { if (VERBOSE) logerror x; } while (0)
|
||||
#if VERBOSE >= 2
|
||||
#define logerror printf
|
||||
#endif
|
||||
|
||||
#ifdef _MSC_VER
|
||||
#define FUNCNAME __func__
|
||||
#else
|
||||
#define FUNCNAME __PRETTY_FUNCTION__
|
||||
#endif
|
||||
|
||||
#define DUSCC_CLOCK XTAL_14_7456MHz /* Verified */
|
||||
|
||||
class fccpu30_state : public driver_device
|
||||
{
|
||||
public:
|
||||
fccpu30_state(const machine_config &mconfig, device_type type, const char *tag) :
|
||||
driver_device (mconfig, type, tag),
|
||||
m_maincpu (*this, "maincpu")
|
||||
,m_dusccterm(*this, "duscc")
|
||||
,m_pit1 (*this, "pit1")
|
||||
,m_pit2 (*this, "pit2")
|
||||
{
|
||||
}
|
||||
|
||||
DECLARE_READ32_MEMBER (bootvect_r);
|
||||
DECLARE_WRITE32_MEMBER (bootvect_w);
|
||||
/* FGA-002 - Force Gate Array */
|
||||
DECLARE_READ8_MEMBER (fga8_r);
|
||||
DECLARE_WRITE8_MEMBER (fga8_w);
|
||||
|
||||
/* Rotary switch PIT input */
|
||||
DECLARE_READ8_MEMBER (rotary_rd);
|
||||
DECLARE_READ8_MEMBER (board_mem_id_rd);
|
||||
|
||||
/* VME bus accesses */
|
||||
//DECLARE_READ16_MEMBER (vme_a24_r);
|
||||
//DECLARE_WRITE16_MEMBER (vme_a24_w);
|
||||
//DECLARE_READ16_MEMBER (vme_a16_r);
|
||||
//DECLARE_WRITE16_MEMBER (vme_a16_w);
|
||||
virtual void machine_start () override;
|
||||
virtual void machine_reset () override;
|
||||
protected:
|
||||
|
||||
private:
|
||||
required_device<cpu_device> m_maincpu;
|
||||
required_device<duscc68562_device> m_dusccterm;
|
||||
|
||||
required_device<pit68230_device> m_pit1;
|
||||
required_device<pit68230_device> m_pit2;
|
||||
|
||||
// Pointer to System ROMs needed by bootvect_r and masking RAM buffer for post reset accesses
|
||||
UINT32 *m_sysrom;
|
||||
UINT32 m_sysram[2];
|
||||
|
||||
// FGA-002
|
||||
UINT8 m_fga002[0x500];
|
||||
};
|
||||
|
||||
static ADDRESS_MAP_START (fccpu30_mem, AS_PROGRAM, 32, fccpu30_state)
|
||||
ADDRESS_MAP_UNMAP_HIGH
|
||||
AM_RANGE (0x00000000, 0x00000007) AM_ROM AM_READ (bootvect_r) /* ROM mirror just during reset */
|
||||
AM_RANGE (0x00000000, 0x00000007) AM_RAM AM_WRITE (bootvect_w) /* After first write we act as RAM */
|
||||
AM_RANGE (0x00000008, 0x003fffff) AM_RAM /* 4 Mb RAM */
|
||||
AM_RANGE (0xff000000, 0xff7fffff) AM_ROM AM_REGION("maincpu", 0xff000000)
|
||||
AM_RANGE (0xff802000, 0xff8021ff) AM_DEVREADWRITE8("duscc", duscc68562_device, read, write, 0xffffffff) /* Port 1&2 - Dual serial port DUSCC */
|
||||
AM_RANGE (0xff800c00, 0xff800dff) AM_DEVREADWRITE8("pit1", pit68230_device, read, write, 0xffffffff)
|
||||
AM_RANGE (0xff800e00, 0xff800fff) AM_DEVREADWRITE8("pit2", pit68230_device, read, write, 0xffffffff)
|
||||
AM_RANGE (0xffc00000, 0xffcfffff) AM_RAM AM_SHARE ("nvram") /* On-board SRAM with battery backup (nvram) */
|
||||
AM_RANGE (0xffd00000, 0xffd004ff) AM_READWRITE8(fga8_r, fga8_w, 0xffffffff) /* FGA-002 Force Gate Array */
|
||||
AM_RANGE (0xffe00000, 0xffefffff) AM_ROM AM_REGION("maincpu", 0xffe00000)
|
||||
|
||||
//AM_RANGE(0x100000, 0xfeffff) AM_READWRITE(vme_a24_r, vme_a24_w) /* VMEbus Rev B addresses (24 bits) - not verified */
|
||||
//AM_RANGE(0xff0000, 0xffffff) AM_READWRITE(vme_a16_r, vme_a16_w) /* VMEbus Rev B addresses (16 bits) - not verified */
|
||||
ADDRESS_MAP_END
|
||||
|
||||
/* Input ports */
|
||||
static INPUT_PORTS_START (fccpu30)
|
||||
INPUT_PORTS_END
|
||||
|
||||
#define FGA_ICRMBOX0 0x0000
|
||||
#define FGA_ICRMBOX1 0x0004
|
||||
#define FGA_ICRMBOX2 0x0008
|
||||
#define FGA_ICRMBOX3 0x000c
|
||||
#define FGA_ICRMBOX4 0x0010
|
||||
#define FGA_ICRMBOX5 0x0014
|
||||
#define FGA_ICRMBOX6 0x0018
|
||||
#define FGA_ICRMBOX7 0x001C
|
||||
#define FGA_VMEPAGE 0x0200
|
||||
#define FGA_ICRVME1 0x0204
|
||||
#define FGA_ICRVME2 0x0208
|
||||
#define FGA_ICRVME3 0x020c
|
||||
#define FGA_ICRVME4 0x0210
|
||||
#define FGA_ICRVME5 0x0214
|
||||
#define FGA_ICRVME6 0x0218
|
||||
#define FGA_ICRVME7 0x021c
|
||||
#define FGA_ICRTIM0 0x0220
|
||||
#define FGA_ICRDMANORM 0x0230
|
||||
#define FGA_ICRDMAERR 0x0234
|
||||
#define FGA_CTL1 0x0238
|
||||
#define FGA_CTL2 0x023c
|
||||
#define FGA_ICRFMB0REF 0x0240
|
||||
#define FGA_ICRFMB1REF 0x0244
|
||||
#define FGA_ICRFMB0MES 0x0248
|
||||
#define FGA_ICRFMB1MES 0x024c
|
||||
#define FGA_CTL3 0x0250
|
||||
#define FGA_CTL4 0x0254
|
||||
#define FGA_ICRPARITY 0x0258
|
||||
#define FGA_AUXPINCTL 0x0260
|
||||
#define FGA_CTL5 0x0264
|
||||
#define FGA_AUXFIFWEX 0x0268
|
||||
#define FGA_AUXFIFREX 0x026c
|
||||
#define FGA_CTL6 0x0270
|
||||
#define FGA_CTL7 0x0274
|
||||
#define FGA_CTL8 0x0278
|
||||
#define FGA_CTL9 0x027c
|
||||
#define FGA_ICRABORT 0x0280
|
||||
#define FGA_ICRACFAIL 0x0284
|
||||
#define FGA_ICRSYSFAIL 0x0288
|
||||
#define FGA_ICRLOCAL0 0x028c
|
||||
#define FGA_ICRLOCAL1 0x0290
|
||||
#define FGA_ICRLOCAL2 0x0294
|
||||
#define FGA_ICRLOCAL3 0x0298
|
||||
#define FGA_ICRLOCAL4 0x029c
|
||||
#define FGA_ICRLOCAL5 0x02a0
|
||||
#define FGA_ICRLOCAL6 0x02a4
|
||||
#define FGA_ICRLOCAL7 0x02a8
|
||||
#define FGA_ENAMCODE 0x02b4
|
||||
#define FGA_CTL10 0x02c0
|
||||
#define FGA_CTL11 0x02c4
|
||||
#define FGA_MAINUM 0x02c8
|
||||
#define FGA_MAINUU 0x02cc
|
||||
#define FGA_BOTTOMPAGEU 0x02d0
|
||||
#define FGA_BOTTOMPAGEL 0x02d4
|
||||
#define FGA_TOPPAGEU 0x02d8
|
||||
#define FGA_TOPPAGEL 0x02dc
|
||||
#define FGA_MYVMEPAGE 0x02fc
|
||||
#define FGA_TIM0PRELOAD 0x0300
|
||||
#define FGA_TIM0CTL 0x0310
|
||||
#define FGA_DMASRCATT 0x0320
|
||||
#define FGA_DMADSTATT 0x0324
|
||||
#define FGA_DMA_GENERAL 0x0328
|
||||
#define FGA_CTL12 0x032c
|
||||
#define FGA_LIOTIMING 0x0330
|
||||
#define FGA_LOCALIACK 0x0334
|
||||
#define FGA_FMBCTL 0x0338
|
||||
#define FGA_FMBAREA 0x033c
|
||||
#define FGA_AUXSRCSTART 0x0340
|
||||
#define FGA_AUXDSTSTART 0x0344
|
||||
#define FGA_AUXSRCTERM 0x0348
|
||||
#define FGA_AUXDSTTERM 0x034c
|
||||
#define FGA_CTL13 0x0350
|
||||
#define FGA_CTL14 0x0354
|
||||
#define FGA_CTL15 0x0358
|
||||
#define FGA_CTL16 0x035c
|
||||
#define FGA_SPECIALENA 0x0424
|
||||
#define FGA_ISTIM0 0x04a0
|
||||
#define FGA_ISDMANORM 0x04b0
|
||||
#define FGA_ISDMAERR 0x04b4
|
||||
#define FGA_ISFMB0REF 0x04b8
|
||||
#define FGA_ISFMB1REF 0x04bc
|
||||
#define FGA_ISPARITY 0x04c0
|
||||
#define FGA_DMARUNCTL 0x04c4
|
||||
#define FGA_ISABORT 0x04c8
|
||||
#define FGA_ISACFAIL 0x04cc
|
||||
#define FGA_ISFMB0MES 0x04e0
|
||||
#define FGA_ISFMB1MES 0x04e4
|
||||
#define FGA_ISSYSFAIL 0x04d0
|
||||
#define FGA_ABORTPIN 0x04d4
|
||||
#define FGA_RSVMECALL 0x04f0
|
||||
#define FGA_RSKEYRES 0x04f4
|
||||
#define FGA_RSCPUCALL 0x04f8
|
||||
#define FGA_RSLOCSW 0x04fc
|
||||
|
||||
/* Start it up */
|
||||
void fccpu30_state::machine_start ()
|
||||
{
|
||||
LOG(("--->%s\n", FUNCNAME));
|
||||
|
||||
save_pointer (NAME (m_sysrom), sizeof(m_sysrom));
|
||||
save_pointer (NAME (m_sysram), sizeof(m_sysram));
|
||||
save_pointer (NAME (m_fga002), sizeof(m_fga002));
|
||||
|
||||
/* Setup pointer to bootvector in ROM for bootvector handler bootvect_r */
|
||||
m_sysrom = (UINT32*)(memregion ("maincpu")->base () + 0xffe00000);
|
||||
}
|
||||
|
||||
void fccpu30_state::machine_reset ()
|
||||
{
|
||||
LOG(("--->%s\n", FUNCNAME));
|
||||
|
||||
/* Reset pointer to bootvector in ROM for bootvector handler bootvect_r */
|
||||
if (m_sysrom == &m_sysram[0]) /* Condition needed because memory map is not setup first time */
|
||||
m_sysrom = (UINT32*)(memregion ("maincpu")->base () + 0xffe00000);
|
||||
|
||||
/* Reset values for the FGA-002 */
|
||||
memset(&m_fga002[0], 0, sizeof(m_fga002));
|
||||
m_fga002[FGA_RSVMECALL] = 0x80;
|
||||
m_fga002[FGA_RSKEYRES] = 0x80;
|
||||
m_fga002[FGA_RSCPUCALL] = 0x80;
|
||||
m_fga002[FGA_RSLOCSW] = 0x80;
|
||||
m_fga002[FGA_ISTIM0] = 0x80;
|
||||
m_fga002[FGA_ISDMANORM] = 0x80;
|
||||
m_fga002[FGA_ISDMAERR] = 0x80;
|
||||
m_fga002[FGA_ISFMB0REF] = 0x80;
|
||||
m_fga002[FGA_ISFMB1REF] = 0x80;
|
||||
m_fga002[FGA_ISPARITY] = 0x80;
|
||||
m_fga002[FGA_ISABORT] = 0x80;
|
||||
m_fga002[FGA_ISACFAIL] = 0x80;
|
||||
m_fga002[FGA_ISSYSFAIL] = 0x80;
|
||||
m_fga002[FGA_ISFMB0MES] = 0x80;
|
||||
m_fga002[FGA_ISFMB1MES] = 0x80;
|
||||
}
|
||||
|
||||
/* Boot vector handler, the PCB hardwires the first 8 bytes from 0xff800000 to 0x0 at reset*/
|
||||
READ32_MEMBER (fccpu30_state::bootvect_r){
|
||||
return m_sysrom[offset];
|
||||
}
|
||||
|
||||
WRITE32_MEMBER (fccpu30_state::bootvect_w){
|
||||
m_sysram[offset % sizeof(m_sysram)] &= ~mem_mask;
|
||||
m_sysram[offset % sizeof(m_sysram)] |= (data & mem_mask);
|
||||
m_sysrom = &m_sysram[0]; // redirect all upcomming accesses to masking RAM until reset.
|
||||
}
|
||||
|
||||
/*
|
||||
* FGA-002 driver, might deserve its own driver but will rest here until another board wants it
|
||||
*
|
||||
The FGA-002 gate array is a high speed CMOS device manufactured in 1.2 micron technology and
|
||||
containing 24,000 gates in a 281 pin PGA package. It provides interfaces to the 68020/30 microprocessor
|
||||
as well as a VMEbus compatible interface. The auxilary interface of the gate array is a high speed data
|
||||
channel used by the internal 32 bit DMA controller. The interface allows data transfer rates of up to
|
||||
6 MByte/second. The timing of the local I/O interface is programmable and provides easy interfacing of
|
||||
local I/O devices. All control, address and data lines of the CPU and the VMEbus are either directly
|
||||
connected or connected via buffers to the gate array allowing easy implementation and usage.
|
||||
The gate array registers are programmed by the local CPU.
|
||||
|
||||
FEATURES:
|
||||
- Programmable decoding for CPU and VME access to the local main memory
|
||||
- Interrupt management for internal and external interrupt sources
|
||||
- 32 bit multi-port DMA Controller
|
||||
- FORCE Message Broadcast slave interface with 2 message channels
|
||||
- 8 interrupt capable MAILBOXES
|
||||
- 8 bit TIMER with 16 selectable internal source clocks
|
||||
*/
|
||||
WRITE8_MEMBER (fccpu30_state::fga8_w){
|
||||
LOG(("%s[%04x] <- %02x - ", FUNCNAME, offset, data));
|
||||
switch(offset)
|
||||
{
|
||||
case FGA_SPECIALENA : LOG(("FGA_SPECIALENA - not implemented\n")); m_fga002[FGA_SPECIALENA] = data; break;
|
||||
case FGA_RSVMECALL : LOG(("FGA_RSVMECALL - not implemented\n")); m_fga002[FGA_RSVMECALL] = data; break;
|
||||
case FGA_RSKEYRES : LOG(("FGA_RSKEYRES - not implemented\n")); m_fga002[FGA_RSKEYRES] = data; break;
|
||||
case FGA_RSCPUCALL : LOG(("FGA_RSCPUCALL - not implemented\n")); m_fga002[FGA_RSCPUCALL] = data; break;
|
||||
case FGA_RSLOCSW : LOG(("FGA_RSLOCSW - not implemented\n")); m_fga002[FGA_RSLOCSW] = data; break;
|
||||
case FGA_ICRMBOX0 : LOG(("FGA_ICRMBOX0 - not implemented\n")); m_fga002[FGA_ICRMBOX0] = data; break;
|
||||
case FGA_ICRMBOX1 : LOG(("FGA_ICRMBOX1 - not implemented\n")); m_fga002[FGA_ICRMBOX1] = data; break;
|
||||
case FGA_ICRMBOX2 : LOG(("FGA_ICRMBOX2 - not implemented\n")); m_fga002[FGA_ICRMBOX2] = data; break;
|
||||
case FGA_ICRMBOX3 : LOG(("FGA_ICRMBOX3 - not implemented\n")); m_fga002[FGA_ICRMBOX3] = data; break;
|
||||
case FGA_ICRMBOX4 : LOG(("FGA_ICRMBOX4 - not implemented\n")); m_fga002[FGA_ICRMBOX4] = data; break;
|
||||
case FGA_ICRMBOX5 : LOG(("FGA_ICRMBOX5 - not implemented\n")); m_fga002[FGA_ICRMBOX5] = data; break;
|
||||
case FGA_ICRMBOX6 : LOG(("FGA_ICRMBOX6 - not implemented\n")); m_fga002[FGA_ICRMBOX6] = data; break;
|
||||
case FGA_ICRMBOX7 : LOG(("FGA_ICRMBOX7 - not implemented\n")); m_fga002[FGA_ICRMBOX7] = data; break;
|
||||
case FGA_VMEPAGE : LOG(("FGA_VMEPAGE - not implemented\n")); m_fga002[FGA_VMEPAGE ] = data; break;
|
||||
case FGA_ICRVME1 : LOG(("FGA_ICRVME1 - not implemented\n")); m_fga002[FGA_ICRVME1] = data; break;
|
||||
case FGA_ICRVME2 : LOG(("FGA_ICRVME2 - not implemented\n")); m_fga002[FGA_ICRVME2] = data; break;
|
||||
case FGA_ICRVME3 : LOG(("FGA_ICRVME3 - not implemented\n")); m_fga002[FGA_ICRVME3] = data; break;
|
||||
case FGA_ICRVME4 : LOG(("FGA_ICRVME4 - not implemented\n")); m_fga002[FGA_ICRVME4] = data; break;
|
||||
case FGA_ICRVME5 : LOG(("FGA_ICRVME5 - not implemented\n")); m_fga002[FGA_ICRVME5] = data; break;
|
||||
case FGA_ICRVME6 : LOG(("FGA_ICRVME6 - not implemented\n")); m_fga002[FGA_ICRVME6] = data; break;
|
||||
case FGA_ICRVME7 : LOG(("FGA_ICRVME7 - not implemented\n")); m_fga002[FGA_ICRVME7] = data; break;
|
||||
case FGA_ICRTIM0 : LOG(("FGA_ICRTIM0 - not implemented\n")); m_fga002[FGA_ICRTIM0] = data; break;
|
||||
case FGA_ICRDMANORM : LOG(("FGA_ICRDMANORM - not implemented\n")); m_fga002[FGA_ICRDMANORM] = data; break;
|
||||
case FGA_ICRDMAERR : LOG(("FGA_ICRDMAERR - not implemented\n")); m_fga002[FGA_ICRDMAERR] = data; break;
|
||||
case FGA_CTL1 : LOG(("FGA_CTL1 - not implemented\n")); m_fga002[FGA_CTL1] = data; break;
|
||||
case FGA_CTL2 : LOG(("FGA_CTL2 - not implemented\n")); m_fga002[FGA_CTL2] = data; break;
|
||||
case FGA_ICRFMB0REF : LOG(("FGA_ICRFMB0REF - not implemented\n")); m_fga002[FGA_ICRFMB0REF] = data; break;
|
||||
case FGA_ICRFMB1REF : LOG(("FGA_ICRFMB1REF - not implemented\n")); m_fga002[FGA_ICRFMB1REF] = data; break;
|
||||
case FGA_ICRFMB0MES : LOG(("FGA_ICRFMB0MES - not implemented\n")); m_fga002[FGA_ICRFMB0MES] = data; break;
|
||||
case FGA_ICRFMB1MES : LOG(("FGA_ICRFMB1MES - not implemented\n")); m_fga002[FGA_ICRFMB1MES] = data; break;
|
||||
case FGA_CTL3 : LOG(("FGA_CTL3 - not implemented\n")); m_fga002[FGA_CTL3] = data; break;
|
||||
case FGA_CTL4 : LOG(("FGA_CTL4 - not implemented\n")); m_fga002[FGA_CTL4] = data; break;
|
||||
case FGA_ICRPARITY : LOG(("FGA_ICRPARITY - not implemented\n")); m_fga002[FGA_ICRPARITY] = data; break;
|
||||
case FGA_AUXPINCTL : LOG(("FGA_AUXPINCTL - not implemented\n")); m_fga002[FGA_AUXPINCTL] = data; break;
|
||||
case FGA_CTL5 : LOG(("FGA_CTL5 - not implemented\n")); m_fga002[FGA_CTL5] = data; break;
|
||||
case FGA_AUXFIFWEX : LOG(("FGA_AUXFIFWEX - not implemented\n")); m_fga002[FGA_AUXFIFWEX] = data; break;
|
||||
case FGA_AUXFIFREX : LOG(("FGA_AUXFIFREX - not implemented\n")); m_fga002[FGA_AUXFIFREX] = data; break;
|
||||
case FGA_CTL6 : LOG(("FGA_CTL6 - not implemented\n")); m_fga002[FGA_CTL6] = data; break;
|
||||
case FGA_CTL7 : LOG(("FGA_CTL7 - not implemented\n")); m_fga002[FGA_CTL7] = data; break;
|
||||
case FGA_CTL8 : LOG(("FGA_CTL8 - not implemented\n")); m_fga002[FGA_CTL8] = data; break;
|
||||
case FGA_CTL9 : LOG(("FGA_CTL9 - not implemented\n")); m_fga002[FGA_CTL9] = data; break;
|
||||
case FGA_ICRABORT : LOG(("FGA_ICRABORT - not implemented\n")); m_fga002[FGA_ICRABORT] = data; break;
|
||||
case FGA_ICRACFAIL : LOG(("FGA_ICRACFAIL - not implemented\n")); m_fga002[FGA_ICRACFAIL] = data; break;
|
||||
case FGA_ICRSYSFAIL : LOG(("FGA_ICRSYSFAIL - not implemented\n")); m_fga002[FGA_ICRSYSFAIL] = data; break;
|
||||
case FGA_ICRLOCAL0 : LOG(("FGA_ICRLOCAL0 - not implemented\n")); m_fga002[FGA_ICRLOCAL0] = data; break;
|
||||
case FGA_ICRLOCAL1 : LOG(("FGA_ICRLOCAL1 - not implemented\n")); m_fga002[FGA_ICRLOCAL1] = data; break;
|
||||
case FGA_ICRLOCAL2 : LOG(("FGA_ICRLOCAL2 - not implemented\n")); m_fga002[FGA_ICRLOCAL2] = data; break;
|
||||
case FGA_ICRLOCAL3 : LOG(("FGA_ICRLOCAL3 - not implemented\n")); m_fga002[FGA_ICRLOCAL3] = data; break;
|
||||
case FGA_ICRLOCAL4 : LOG(("FGA_ICRLOCAL4 - not implemented\n")); m_fga002[FGA_ICRLOCAL4] = data; break;
|
||||
case FGA_ICRLOCAL5 : LOG(("FGA_ICRLOCAL5 - not implemented\n")); m_fga002[FGA_ICRLOCAL5] = data; break;
|
||||
case FGA_ICRLOCAL6 : LOG(("FGA_ICRLOCAL6 - not implemented\n")); m_fga002[FGA_ICRLOCAL6] = data; break;
|
||||
case FGA_ICRLOCAL7 : LOG(("FGA_ICRLOCAL7 - not implemented\n")); m_fga002[FGA_ICRLOCAL7] = data; break;
|
||||
case FGA_ENAMCODE : LOG(("FGA_ENAMCODE - not implemented\n")); m_fga002[FGA_ENAMCODE] = data; break;
|
||||
case FGA_CTL10 : LOG(("FGA_CTL10 - not implemented\n")); m_fga002[FGA_CTL10] = data; break;
|
||||
case FGA_CTL11 : LOG(("FGA_CTL11 - not implemented\n")); m_fga002[FGA_CTL11] = data; break;
|
||||
case FGA_MAINUM : LOG(("FGA_MAINUM - not implemented\n")); m_fga002[FGA_MAINUM] = data; break;
|
||||
case FGA_MAINUU : LOG(("FGA_MAINUU - not implemented\n")); m_fga002[FGA_MAINUU] = data; break;
|
||||
case FGA_BOTTOMPAGEU : LOG(("FGA_BOTTOMPAGEU - not implemented\n")); m_fga002[FGA_BOTTOMPAGEU] = data; break;
|
||||
case FGA_BOTTOMPAGEL : LOG(("FGA_BOTTOMPAGEL - not implemented\n")); m_fga002[FGA_BOTTOMPAGEL] = data; break;
|
||||
case FGA_TOPPAGEU : LOG(("FGA_TOPPAGEU - not implemented\n")); m_fga002[FGA_TOPPAGEU] = data; break;
|
||||
case FGA_TOPPAGEL : LOG(("FGA_TOPPAGEL - not implemented\n")); m_fga002[FGA_TOPPAGEL] = data; break;
|
||||
case FGA_MYVMEPAGE : LOG(("FGA_MYVMEPAGE - not implemented\n")); m_fga002[FGA_MYVMEPAGE] = data; break;
|
||||
case FGA_TIM0PRELOAD : LOG(("FGA_TIM0PRELOAD - not implemented\n")); m_fga002[FGA_TIM0PRELOAD] = data; break;
|
||||
case FGA_TIM0CTL : LOG(("FGA_TIM0CTL - not implemented\n")); m_fga002[FGA_TIM0CTL] = data; break;
|
||||
case FGA_DMASRCATT : LOG(("FGA_DMASRCATT - not implemented\n")); m_fga002[FGA_DMASRCATT] = data; break;
|
||||
case FGA_DMADSTATT : LOG(("FGA_DMADSTATT - not implemented\n")); m_fga002[FGA_DMADSTATT] = data; break;
|
||||
case FGA_DMA_GENERAL : LOG(("FGA_DMA_GENERAL - not implemented\n")); m_fga002[FGA_DMA_GENERAL] = data; break;
|
||||
case FGA_CTL12 : LOG(("FGA_CTL12 - not implemented\n")); m_fga002[FGA_CTL12] = data; break;
|
||||
case FGA_LIOTIMING : LOG(("FGA_LIOTIMING - not implemented\n")); m_fga002[FGA_LIOTIMING] = data; break;
|
||||
case FGA_LOCALIACK : LOG(("FGA_LOCALIACK - not implemented\n")); m_fga002[FGA_LOCALIACK] = data; break;
|
||||
case FGA_FMBCTL : LOG(("FGA_FMBCTL - not implemented\n")); m_fga002[FGA_FMBCTL] = data; break;
|
||||
case FGA_FMBAREA : LOG(("FGA_FMBAREA - not implemented\n")); m_fga002[FGA_FMBAREA] = data; break;
|
||||
case FGA_AUXSRCSTART : LOG(("FGA_AUXSRCSTART - not implemented\n")); m_fga002[FGA_AUXSRCSTART] = data; break;
|
||||
case FGA_AUXDSTSTART : LOG(("FGA_AUXDSTSTART - not implemented\n")); m_fga002[FGA_AUXDSTSTART] = data; break;
|
||||
case FGA_AUXSRCTERM : LOG(("FGA_AUXSRCTERM - not implemented\n")); m_fga002[FGA_AUXSRCTERM] = data; break;
|
||||
case FGA_AUXDSTTERM : LOG(("FGA_AUXDSTTERM - not implemented\n")); m_fga002[FGA_AUXDSTTERM] = data; break;
|
||||
case FGA_CTL13 : LOG(("FGA_CTL13 - not implemented\n")); m_fga002[FGA_CTL13] = data; break;
|
||||
case FGA_CTL14 : LOG(("FGA_CTL14 - not implemented\n")); m_fga002[FGA_CTL14] = data; break;
|
||||
case FGA_CTL15 : LOG(("FGA_CTL15 - not implemented\n")); m_fga002[FGA_CTL15] = data; break;
|
||||
case FGA_CTL16 : LOG(("FGA_CTL16 - not implemented\n")); m_fga002[FGA_CTL16] = data; break;
|
||||
case FGA_ISTIM0 : LOG(("FGA_ISTIM0 - not implemented\n")); m_fga002[FGA_ISTIM0] = data; break;
|
||||
case FGA_ISDMANORM : LOG(("FGA_ISDMANORM - not implemented\n")); m_fga002[FGA_ISDMANORM] = data; break;
|
||||
case FGA_ISDMAERR : LOG(("FGA_ISDMAERR - not implemented\n")); m_fga002[FGA_ISDMAERR] = data; break;
|
||||
case FGA_ISFMB0REF : LOG(("FGA_ISFMB0REF - not implemented\n")); m_fga002[FGA_ISFMB0REF] = data; break;
|
||||
case FGA_ISFMB1REF : LOG(("FGA_ISFMB1REF - not implemented\n")); m_fga002[FGA_ISFMB1REF] = data; break;
|
||||
case FGA_ISPARITY : LOG(("FGA_ISPARITY - not implemented\n")); m_fga002[FGA_ISPARITY] = data; break;
|
||||
case FGA_DMARUNCTL : LOG(("FGA_DMARUNCTL - not implemented\n")); m_fga002[FGA_DMARUNCTL] = data; break;
|
||||
case FGA_ISABORT : LOG(("FGA_ISABORT - not implemented\n")); m_fga002[FGA_ISABORT] = data; break;
|
||||
case FGA_ISFMB0MES : LOG(("FGA_ISFMB0MES - not implemented\n")); m_fga002[FGA_ISFMB0MES] = data; break;
|
||||
case FGA_ISFMB1MES : LOG(("FGA_ISFMB1MES - not implemented\n")); m_fga002[FGA_ISFMB1MES] = data; break;
|
||||
case FGA_ABORTPIN : LOG(("FGA_ABORTPIN - not implemented\n")); m_fga002[FGA_ABORTPIN] = data; break;
|
||||
default:
|
||||
LOG(("Unsupported register %04x\n", offset));
|
||||
}
|
||||
}
|
||||
|
||||
READ8_MEMBER (fccpu30_state::fga8_r){
|
||||
|
||||
UINT8 ret = 0;
|
||||
|
||||
LOG(("%s[%04x] ", FUNCNAME, offset));
|
||||
switch(offset)
|
||||
{
|
||||
case FGA_SPECIALENA : ret = m_fga002[FGA_SPECIALENA]; LOG(("FGA_SPECIALENA returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_RSVMECALL : ret = m_fga002[FGA_RSVMECALL]; LOG(("FGA_RSVMECALL returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_RSKEYRES : ret = m_fga002[FGA_RSKEYRES]; LOG(("FGA_RSKEYRES returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_RSCPUCALL : ret = m_fga002[FGA_RSCPUCALL]; LOG(("FGA_RSCPUCALL returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_RSLOCSW : ret = m_fga002[FGA_RSLOCSW]; LOG(("FGA_RSLOCSW returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_ICRMBOX0 : ret = m_fga002[FGA_ICRMBOX0]; LOG(("FGA_ICRMBOX0 returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_ICRMBOX1 : ret = m_fga002[FGA_ICRMBOX1]; LOG(("FGA_ICRMBOX1 returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_ICRMBOX2 : ret = m_fga002[FGA_ICRMBOX2]; LOG(("FGA_ICRMBOX2 returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_ICRMBOX3 : ret = m_fga002[FGA_ICRMBOX3]; LOG(("FGA_ICRMBOX3 returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_ICRMBOX4 : ret = m_fga002[FGA_ICRMBOX4]; LOG(("FGA_ICRMBOX4 returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_ICRMBOX5 : ret = m_fga002[FGA_ICRMBOX5]; LOG(("FGA_ICRMBOX5 returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_ICRMBOX6 : ret = m_fga002[FGA_ICRMBOX6]; LOG(("FGA_ICRMBOX6 returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_ICRMBOX7 : ret = m_fga002[FGA_ICRMBOX7]; LOG(("FGA_ICRMBOX7 returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_VMEPAGE : ret = m_fga002[FGA_VMEPAGE]; LOG(("FGA_VMEPAGE returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_ICRVME1 : ret = m_fga002[FGA_ICRVME1]; LOG(("FGA_ICRVME1 returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_ICRVME2 : ret = m_fga002[FGA_ICRVME2]; LOG(("FGA_ICRVME2 returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_ICRVME3 : ret = m_fga002[FGA_ICRVME3]; LOG(("FGA_ICRVME3 returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_ICRVME4 : ret = m_fga002[FGA_ICRVME4]; LOG(("FGA_ICRVME4 returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_ICRVME5 : ret = m_fga002[FGA_ICRVME5]; LOG(("FGA_ICRVME5 returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_ICRVME6 : ret = m_fga002[FGA_ICRVME6]; LOG(("FGA_ICRVME6 returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_ICRVME7 : ret = m_fga002[FGA_ICRVME7]; LOG(("FGA_ICRVME7 returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_ICRTIM0 : ret = m_fga002[FGA_ICRTIM0]; LOG(("FGA_ICRTIM0 returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_ICRDMANORM : ret = m_fga002[FGA_ICRDMANORM]; LOG(("FGA_ICRDMANORM returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_ICRDMAERR : ret = m_fga002[FGA_ICRDMAERR]; LOG(("FGA_ICRDMAERR returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_CTL1 : ret = m_fga002[FGA_CTL1]; LOG(("FGA_CTL1 returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_CTL2 : ret = m_fga002[FGA_CTL2]; LOG(("FGA_CTL2 returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_ICRFMB0REF : ret = m_fga002[FGA_ICRFMB0REF]; LOG(("FGA_ICRFMB0REF returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_ICRFMB1REF : ret = m_fga002[FGA_ICRFMB1REF]; LOG(("FGA_ICRFMB1REF returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_ICRFMB0MES : ret = m_fga002[FGA_ICRFMB0MES]; LOG(("FGA_ICRFMB0MES returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_ICRFMB1MES : ret = m_fga002[FGA_ICRFMB1MES]; LOG(("FGA_ICRFMB1MES returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_CTL3 : ret = m_fga002[FGA_CTL3]; LOG(("FGA_CTL3 returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_CTL4 : ret = m_fga002[FGA_CTL4]; LOG(("FGA_CTL4 returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_ICRPARITY : ret = m_fga002[FGA_ICRPARITY]; LOG(("FGA_ICRPARITY returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_AUXPINCTL : ret = m_fga002[FGA_AUXPINCTL]; LOG(("FGA_AUXPINCTL returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_CTL5 : ret = m_fga002[FGA_CTL5]; LOG(("FGA_CTL5 returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_AUXFIFWEX : ret = m_fga002[FGA_AUXFIFWEX]; LOG(("FGA_AUXFIFWEX returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_AUXFIFREX : ret = m_fga002[FGA_AUXFIFREX]; LOG(("FGA_AUXFIFREX returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_CTL6 : ret = m_fga002[FGA_CTL6]; LOG(("FGA_CTL6 returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_CTL7 : ret = m_fga002[FGA_CTL7]; LOG(("FGA_CTL7 returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_CTL8 : ret = m_fga002[FGA_CTL8]; LOG(("FGA_CTL8 returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_CTL9 : ret = m_fga002[FGA_CTL9]; LOG(("FGA_CTL9 returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_ICRABORT : ret = m_fga002[FGA_ICRABORT]; LOG(("FGA_ICRABORT returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_ICRACFAIL : ret = m_fga002[FGA_ICRACFAIL]; LOG(("FGA_ICRACFAIL returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_ICRSYSFAIL : ret = m_fga002[FGA_ICRSYSFAIL]; LOG(("FGA_ICRSYSFAIL returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_ICRLOCAL0 : ret = m_fga002[FGA_ICRLOCAL0]; LOG(("FGA_ICRLOCAL0 returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_ICRLOCAL1 : ret = m_fga002[FGA_ICRLOCAL1]; LOG(("FGA_ICRLOCAL1 returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_ICRLOCAL2 : ret = m_fga002[FGA_ICRLOCAL2]; LOG(("FGA_ICRLOCAL2 returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_ICRLOCAL3 : ret = m_fga002[FGA_ICRLOCAL3]; LOG(("FGA_ICRLOCAL3 returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_ICRLOCAL4 : ret = m_fga002[FGA_ICRLOCAL4]; LOG(("FGA_ICRLOCAL4 returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_ICRLOCAL5 : ret = m_fga002[FGA_ICRLOCAL5]; LOG(("FGA_ICRLOCAL5 returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_ICRLOCAL6 : ret = m_fga002[FGA_ICRLOCAL6]; LOG(("FGA_ICRLOCAL6 returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_ICRLOCAL7 : ret = m_fga002[FGA_ICRLOCAL7]; LOG(("FGA_ICRLOCAL7 returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_ENAMCODE : ret = m_fga002[FGA_ENAMCODE]; LOG(("FGA_ENAMCODE returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_CTL10 : ret = m_fga002[FGA_CTL10]; LOG(("FGA_CTL10 returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_CTL11 : ret = m_fga002[FGA_CTL11]; LOG(("FGA_CTL11 returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_MAINUM : ret = m_fga002[FGA_MAINUM]; LOG(("FGA_MAINUM returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_MAINUU : ret = m_fga002[FGA_MAINUU]; LOG(("FGA_MAINUU returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_BOTTOMPAGEU : ret = m_fga002[FGA_BOTTOMPAGEU]; LOG(("FGA_BOTTOMPAGEU returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_BOTTOMPAGEL : ret = m_fga002[FGA_BOTTOMPAGEL]; LOG(("FGA_BOTTOMPAGEL returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_TOPPAGEU : ret = m_fga002[FGA_TOPPAGEU]; LOG(("FGA_TOPPAGEU returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_TOPPAGEL : ret = m_fga002[FGA_TOPPAGEL]; LOG(("FGA_TOPPAGEL returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_MYVMEPAGE : ret = m_fga002[FGA_MYVMEPAGE]; LOG(("FGA_MYVMEPAGE returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_TIM0PRELOAD : ret = m_fga002[FGA_TIM0PRELOAD]; LOG(("FGA_TIM0PRELOAD returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_TIM0CTL : ret = m_fga002[FGA_TIM0CTL]; LOG(("FGA_TIM0CTL returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_DMASRCATT : ret = m_fga002[FGA_DMASRCATT]; LOG(("FGA_DMASRCATT returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_DMADSTATT : ret = m_fga002[FGA_DMADSTATT]; LOG(("FGA_DMADSTATT returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_DMA_GENERAL : ret = m_fga002[FGA_DMA_GENERAL]; LOG(("FGA_DMA_GENERAL returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_CTL12 : ret = m_fga002[FGA_CTL12]; LOG(("FGA_CTL12 returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_LIOTIMING : ret = m_fga002[FGA_LIOTIMING]; LOG(("FGA_LIOTIMING returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_LOCALIACK : ret = m_fga002[FGA_LOCALIACK]; LOG(("FGA_LOCALIACK returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_FMBCTL : ret = m_fga002[FGA_FMBCTL]; LOG(("FGA_FMBCTL returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_FMBAREA : ret = m_fga002[FGA_FMBAREA]; LOG(("FGA_FMBAREA returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_AUXSRCSTART : ret = m_fga002[FGA_AUXSRCSTART]; LOG(("FGA_AUXSRCSTART returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_AUXDSTSTART : ret = m_fga002[FGA_AUXDSTSTART]; LOG(("FGA_AUXDSTSTART returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_AUXSRCTERM : ret = m_fga002[FGA_AUXSRCTERM]; LOG(("FGA_AUXSRCTERM returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_AUXDSTTERM : ret = m_fga002[FGA_AUXDSTTERM]; LOG(("FGA_AUXDSTTERM returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_CTL13 : ret = m_fga002[FGA_CTL13]; LOG(("FGA_CTL13 returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_CTL14 : ret = m_fga002[FGA_CTL14]; LOG(("FGA_CTL14 returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_CTL15 : ret = m_fga002[FGA_CTL15]; LOG(("FGA_CTL15 returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_CTL16 : ret = m_fga002[FGA_CTL16]; LOG(("FGA_CTL16 returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_ISTIM0 : ret = m_fga002[FGA_ISTIM0]; LOG(("FGA_ISTIM0 returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_ISDMANORM : ret = m_fga002[FGA_ISDMANORM]; LOG(("FGA_ISDMANORM returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_ISDMAERR : ret = m_fga002[FGA_ISDMAERR]; LOG(("FGA_ISDMAERR returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_ISFMB0REF : ret = m_fga002[FGA_ISFMB0REF]; LOG(("FGA_ISFMB0REF returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_ISFMB1REF : ret = m_fga002[FGA_ISFMB1REF]; LOG(("FGA_ISFMB1REF returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_ISPARITY : ret = m_fga002[FGA_ISPARITY]; LOG(("FGA_ISPARITY returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_DMARUNCTL : ret = m_fga002[FGA_DMARUNCTL]; LOG(("FGA_DMARUNCTL returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_ISABORT : ret = m_fga002[FGA_ISABORT]; LOG(("FGA_ISABORT returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_ISFMB0MES : ret = m_fga002[FGA_ISFMB0MES]; LOG(("FGA_ISFMB0MES returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_ISFMB1MES : ret = m_fga002[FGA_ISFMB1MES]; LOG(("FGA_ISFMB1MES returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_ABORTPIN : ret = m_fga002[FGA_ABORTPIN]; LOG(("FGA_ABORTPIN returns %02x - not implemented\n", ret)); break;
|
||||
default:
|
||||
LOG(("Unsupported register %04x\n", offset));
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*
|
||||
* Rotary Switches - to configure the board
|
||||
*
|
||||
* Table 25: PI/T #1 Interface Signals
|
||||
* Pin Function In/Out
|
||||
* PA0-PA3 SW1 In
|
||||
* PA4 PA7 SW2 In
|
||||
*
|
||||
* Table 38: Upper Rotary Switch (SW2)
|
||||
* Bit 3: This bit indicates whether the RAM disk should be initialized after reset. If this bit is set to "0" (settings 0-7),
|
||||
* the RAM disk is initialized as defined by bit 0 and 1. When the disk is initialized, all data on the disk is lost.
|
||||
* Bit 2: This bit defines the default data size on the VMEbus. If the bit is set to "0", 16 bits are selected, if it is set
|
||||
* to "1", 32 bits are selected.
|
||||
* Bit 1 and Bit 0: These two bits define the default RAM disk. See Table 40, "RAM Disk Usage," a detailed description.
|
||||
* If AUTOBOOT is set by bit 2 and 3 of SW1, bit 1 and 0 of SW2 define which operating system will be booted. See Table 42,
|
||||
* "Boot an Operating System (if AUTOBOOT is selected)," on page 129 for detailed description.
|
||||
*
|
||||
* Table 39: Lower Rotary Switch (SW1)
|
||||
* Bit 3 and Bit 2: These two bits define which program is to be invoked after reset. Please refer
|
||||
* to Table 41, "Program After Reset," on page 129 for a detailed description.
|
||||
* Bit 1: If this switch is "0" (settings 0,1,4,5,8,9,C,D), VMEPROM tries to execute a start-up file after reset. The default
|
||||
* filename is SY$STRT. If the bit is "1", VMEPROM comes up with the default banner.
|
||||
* Bit 0: If this switch is set to "0" (settings 0,2,4,6,8,A,C,E), VMEPROM checks the VMEbus for available hardware after reset.
|
||||
* In addition VMEPROM waits for SYSFAIL to disappear from the VMEbus. The following hardware can be detected:
|
||||
* - Contiguous memory
|
||||
* - ASCU-1/2
|
||||
* - ISIO-1/2
|
||||
* - SIO-1/2
|
||||
* - ISCSI-1
|
||||
* - WFC-1
|
||||
*
|
||||
* Table 40: RAM Disk Usage
|
||||
* Bit 1 Bit 0 Upper Switch (SW 2) selected on
|
||||
* 1 1 RAM DISK AT TOP OF MEMORY (32 Kbytes) 3,7,B,F
|
||||
* 1 0 RAM DISK AT 0xFC80 0000 (512 Kbytes) 2,6,A,E
|
||||
* 0 1 RAM DISK AT 0x4070 0000 (512 Kbytes) 1,5,9,D
|
||||
* 0 0 RAM DISK AT 0x4080 0000 (512 Kbytes) 0,4,8,C
|
||||
*
|
||||
* Table 41: Program After Reset
|
||||
* Bit 3 Bit 2 Lower Switch (SW 1) selected on
|
||||
* 1 1 VMEPROM C,D,E,F
|
||||
* 1 0 USER PROGRAM AT 0x4070 0000 8,9,A,B
|
||||
* 0 1 AUTOBOOT SYSTEM 4,5,6,7
|
||||
* 0 0 USER PROGRAM AT 4080.000016 0,1,2,3
|
||||
*
|
||||
* Table 42: Boot an Operating System (if AUTOBOOT is selected)
|
||||
* Bit 1 Bit 0 Upper Switch (SW 2) selected on
|
||||
* 1 1 reserved 3,7,B,F
|
||||
* 1 0 Boot UNIX/PDOS 4.x 2,6,A,E
|
||||
* 0 1 Boot another operating system 1,5,9,D
|
||||
* 0 0 Setup for UNIX mailbox driver 0,4,8,C
|
||||
*
|
||||
* "To start VMEPROM, the rotary switches must both be set to 'F':" Hmm...
|
||||
*/
|
||||
READ8_MEMBER (fccpu30_state::rotary_rd){
|
||||
LOG(("%s\n", FUNCNAME));
|
||||
return 0xff; // TODO: make this configurable from commandline or artwork
|
||||
}
|
||||
|
||||
/*
|
||||
* PI/T #2 Factory settings
|
||||
* B0-B2 Shared Memory Size - From these lines, the on-board Shared RAM capacity can be read in by software.
|
||||
* 0 0 0 32 Mb
|
||||
* 0 0 1 16 Mb
|
||||
* 0 1 0 8 Mb
|
||||
* 0 1 1 4 Mb
|
||||
* 1 x x Reserved
|
||||
* B3-B7 Board ID(s) - From these lines, the CPU board identification number can be read in by
|
||||
* 0 1 0 1 0 CPU-30 R4 software. Every CPU board has a unique number. Different versions of
|
||||
* (fill in more) one CPU board (i.e. different speeds, capacity of memory, or modules)
|
||||
* contain the same identification number. In the case of the CPU-30 R4, the
|
||||
* number is ten ("10" decimal or 0A16 hexadecimal "01010" binary).
|
||||
*/
|
||||
READ8_MEMBER (fccpu30_state::board_mem_id_rd){
|
||||
LOG(("%s\n", FUNCNAME));
|
||||
return 0x6A; // CPU-30 R4 with 4Mb of shared RAM. TODO: make this configurable from commandline or artwork
|
||||
}
|
||||
|
||||
#if 0
|
||||
/* Dummy VME access methods until the VME bus device is ready for use */
|
||||
READ16_MEMBER (fccpu30_state::vme_a24_r){
|
||||
LOG (logerror ("vme_a24_r\n"));
|
||||
return (UINT16) 0;
|
||||
}
|
||||
|
||||
WRITE16_MEMBER (fccpu30_state::vme_a24_w){
|
||||
LOG (logerror ("vme_a24_w\n"));
|
||||
}
|
||||
|
||||
READ16_MEMBER (fccpu30_state::vme_a16_r){
|
||||
LOG (logerror ("vme_16_r\n"));
|
||||
return (UINT16) 0;
|
||||
}
|
||||
|
||||
WRITE16_MEMBER (fccpu30_state::vme_a16_w){
|
||||
LOG (logerror ("vme_a16_w\n"));
|
||||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Machine configuration
|
||||
*/
|
||||
static MACHINE_CONFIG_START (fccpu30, fccpu30_state)
|
||||
/* basic machine hardware */
|
||||
MCFG_CPU_ADD ("maincpu", M68030, XTAL_16MHz)
|
||||
MCFG_CPU_PROGRAM_MAP (fccpu30_mem)
|
||||
MCFG_NVRAM_ADD_0FILL("nvram")
|
||||
|
||||
/* Terminal Port config */
|
||||
MCFG_DUSCC68562_ADD("duscc", DUSCC_CLOCK, 0, 0, 0, 0 )
|
||||
MCFG_DUSCC_OUT_TXDA_CB(DEVWRITELINE("rs232trm", rs232_port_device, write_txd))
|
||||
MCFG_DUSCC_OUT_DTRA_CB(DEVWRITELINE("rs232trm", rs232_port_device, write_dtr))
|
||||
MCFG_DUSCC_OUT_RTSA_CB(DEVWRITELINE("rs232trm", rs232_port_device, write_rts))
|
||||
|
||||
MCFG_RS232_PORT_ADD ("rs232trm", default_rs232_devices, "terminal")
|
||||
MCFG_RS232_RXD_HANDLER (DEVWRITELINE ("duscc", duscc68562_device, rxa_w))
|
||||
MCFG_RS232_CTS_HANDLER (DEVWRITELINE ("duscc", duscc68562_device, ctsa_w))
|
||||
|
||||
// MCFG_DUSCC68562_ADD("duscc2", DUSCC_CLOCK, 0, 0, 0, 0 )
|
||||
|
||||
/* PIT Parallel Interface and Timer device, assuming strapped for on board clock */
|
||||
MCFG_DEVICE_ADD ("pit1", PIT68230, XTAL_16MHz / 2)
|
||||
MCFG_PIT68230_PA_INPUT_CB(READ8(fccpu30_state, rotary_rd))
|
||||
MCFG_DEVICE_ADD ("pit2", PIT68230, XTAL_16MHz / 2)
|
||||
MCFG_PIT68230_PB_INPUT_CB(READ8(fccpu30_state, board_mem_id_rd))
|
||||
MACHINE_CONFIG_END
|
||||
|
||||
/* ROM definitions */
|
||||
ROM_START (fccpu30)
|
||||
ROM_REGION32_BE(0xfff00000, "maincpu", 0)
|
||||
|
||||
ROM_LOAD16_BYTE("CPU30LO.BIN", 0xff000000, 0x20000, CRC (fefa88ed) SHA1 (71a9ad807c0c2da5c6f6a6dc68c73ad8b52f3ea9))
|
||||
ROM_LOAD16_BYTE("CPU30UP.BIN", 0xff000001, 0x20000, CRC (dfed1f68) SHA1 (71478a77d5ab5da0fabcd78e69537919b560e3b8))
|
||||
ROM_LOAD("PGA-002.BIN", 0xffe00000, 0x10000, CRC (faa38972) SHA1 (651dfc2f9a865fc6adf49dad90f9e705f2889919))
|
||||
|
||||
/*
|
||||
* System ROM information
|
||||
*
|
||||
* FGA-002 Bootprom version 3.1 is released May 28, 1990, coprighted by FORCE Computers Gmbh
|
||||
*
|
||||
* Bootprom PIT setup sequence
|
||||
* 0a 00 <- read port A without side effects
|
||||
* 0b 00 <- read port B without side effects
|
||||
* 10 00 -> TCR - Timer Control register: Disable timer
|
||||
* 13 ff -> CPRH - Counter Preload Regsiter High
|
||||
* 14 ff -> CPRM - Counter Preload Regsiter Mid
|
||||
* 15 ff -> CPRL - Counter Preload Regsiter Low
|
||||
* 10 01 -> TCR - Timer Control register: Enable timer
|
||||
* ------ init ends -------- clock: 4217
|
||||
*
|
||||
* To start VMEPROM, the rotary switches must both be set to 'F' (PI/T #1 port A)
|
||||
*
|
||||
* ------ next config -------- clock: 1964222
|
||||
* 10 00 -> TCR - Timer Control register: Disable timer
|
||||
* 17 00 -> CRH - Counter Register High
|
||||
* 18 00 -> CRM - Counter Register Medium
|
||||
* 19 00 -> CRL - Counter Register Low
|
||||
*
|
||||
* DUSCC #1 channel A setup sequence
|
||||
* 0f 00 -> REG_CCR - reset Tx Command
|
||||
* 0f 40 -> REG_CCR - reset Rx Command
|
||||
* 00 07 -> REG_CMR1 - Async mode
|
||||
* 01 38 -> REG_CMR2 - Normal polled or interrupt mode, no DMA
|
||||
* 04 7f -> REG_TPR - Tx 8 bits, CTS and RTS, 1 STOP bit
|
||||
* 06 1b -> REG_RPR - Rx RTS, 8 bits, no DCD, no parity
|
||||
* 05 3d -> REG_TTR - Tx BRG 9600 (assuming a 14.7456 crystal)
|
||||
* 07 2d -> REG_RTR - Rx BRG 9600 (assuming a 14.7456 crystal)
|
||||
* 0e 27 -> REG_PCR - TRxC = RxCLK 1x, RTxC is input, RTS, GPO2, crystal oscillator connected to X2
|
||||
* 0b f1 -> REG_OMR - RTS low, OUT1 = OUT2 = high, RxRdy asserted for each character,
|
||||
* TxRdy asserted on threshold, Same Tx Residual Character Length as for REG_TPR
|
||||
* 0f 00 -> REG_CCR - reset Tx Command
|
||||
* 0f 40 -> REG_CCR - reset Rx Command
|
||||
* 0f 02 -> REG_CCR - enable Tx Command
|
||||
* 0f 42 -> REG_CCR - enable Rx Command
|
||||
*--- end of setup sequence ---
|
||||
* loop:
|
||||
* read <- REG_GSR
|
||||
* until something needs attention
|
||||
*/
|
||||
ROM_END
|
||||
|
||||
/* Driver */
|
||||
/* YEAR NAME PARENT COMPAT MACHINE INPUT CLASS INIT COMPANY FULLNAME FLAGS */
|
||||
COMP (1990, fccpu30, 0, 0, fccpu30, fccpu30, driver_device, 0, "Force Computers Gmbh", "SYS68K/CPU-30", MACHINE_NOT_WORKING | MACHINE_NO_SOUND_HW | MACHINE_TYPE_COMPUTER )
|
||||
@ -470,8 +470,8 @@ MCFG_DEVICE_ADD ("rtc", MM58167, XTAL_32_768kHz)
|
||||
|
||||
/* PIT Parallel Interface and Timer device, assuming strapped for on board clock */
|
||||
MCFG_DEVICE_ADD ("pit", PIT68230, XTAL_16MHz / 2)
|
||||
MCFG_PIT68230_PA_OUTPUT_CALLBACK (DEVWRITE8 ("cent_data_out", output_latch_device, write))
|
||||
MCFG_PIT68230_H2_CALLBACK (DEVWRITELINE ("centronics", centronics_device, write_strobe))
|
||||
MCFG_PIT68230_PA_OUTPUT_CB (DEVWRITE8 ("cent_data_out", output_latch_device, write))
|
||||
MCFG_PIT68230_H2_CB (DEVWRITELINE ("centronics", centronics_device, write_strobe))
|
||||
|
||||
// centronics
|
||||
MCFG_CENTRONICS_ADD ("centronics", centronics_devices, "printer")
|
||||
|
||||
@ -12069,6 +12069,9 @@ fb01 // 1986 FB-01
|
||||
@source:fc100.cpp
|
||||
fc100 //
|
||||
|
||||
@source:fccpu30.cpp
|
||||
fccpu30 //
|
||||
|
||||
@source:fcscsi.cpp
|
||||
fcscsi1 //
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user