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https://github.com/holub/mame
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smc91c9x: Refactor code. WIP. (nw)
This commit is contained in:
Ted Green
parent
4f38e6cc54
commit
bd8d63a3a3
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@ -4,13 +4,15 @@
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SMC91C9X ethernet controller implementation
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by Aaron Giles, Jean-François DEL NERO
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by Aaron Giles, Ted Green
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**************************************************************************/
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#ifndef MAME_MACHINE_SMC91C9X_H
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#define MAME_MACHINE_SMC91C9X_H
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#pragma once
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/***************************************************************************
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TYPE DEFINITIONS
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***************************************************************************/
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@ -22,39 +24,205 @@ public:
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DECLARE_READ16_MEMBER( read );
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DECLARE_WRITE16_MEMBER( write );
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TIMER_CALLBACK_MEMBER(send_frame);
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virtual void recv_cb(uint8_t *data, int length) override;
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void set_link_connected(bool connected) { m_link_unconnected = !connected; };
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protected:
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smc91c9x_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock);
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enum class dev_type {
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SMC91C94,
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SMC91C96
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};
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smc91c9x_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, dev_type device_type);
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// device-level overrides
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virtual void device_start() override;
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virtual void device_reset() override;
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virtual void device_pre_save(void) override;
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virtual void device_post_load(void) override;
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// device_network_interface overrides
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virtual void send_complete_cb(int result) override;
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virtual int recv_start_cb(u8 *buf, int length) override;
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virtual void recv_complete_cb(int result) override;
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void dump_bytes(u8 *buf, int length);
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int address_filter(u8 *buf);
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int receive(u8 *buf, int length);
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TIMER_CALLBACK_MEMBER(tx_poll);
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const dev_type m_device_type;
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unsigned m_num_ebuf;
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private:
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static constexpr unsigned ETHER_BUFFER_SIZE = 2048;
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// TODO: 96 device is larger
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static constexpr unsigned ETHER_BUFFERS = 16;
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static constexpr unsigned ETHERNET_ADDR_SIZE = 6;
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// Ethernet registers - bank 0
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enum bank0_addr : u8 {
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B0_TCR = (0 * 8 + 0),
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B0_EPH_STATUS = (0 * 8 + 1),
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B0_RCR = (0 * 8 + 2),
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B0_COUNTER = (0 * 8 + 3),
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B0_MIR = (0 * 8 + 4),
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B0_MCR = (0 * 8 + 5),
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B0_BANK = (0 * 8 + 7)
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};
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// external network is present
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bool m_network_available;
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// Ethernet registers - bank 1
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enum bank1_addr : u8 {
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B1_CONFIG = (1 * 8 + 0),
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B1_BASE = (1 * 8 + 1),
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B1_IA0_1 = (1 * 8 + 2),
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B1_IA2_3 = (1 * 8 + 3),
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B1_IA4_5 = (1 * 8 + 4),
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B1_GENERAL_PURP = (1 * 8 + 5),
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B1_CONTROL = (1 * 8 + 6)
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};
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// Ethernet registers - bank 2
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enum bank2_addr : u8 {
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B2_MMU_COMMAND = (2 * 8 + 0),
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B2_PNR_ARR = (2 * 8 + 1),
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B2_FIFO_PORTS = (2 * 8 + 2),
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B2_POINTER = (2 * 8 + 3),
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B2_DATA_0 = (2 * 8 + 4),
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B2_DATA_1 = (2 * 8 + 5),
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B2_INTERRUPT = (2 * 8 + 6)
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};
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// Ethernet registers - bank 3
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enum bank3_addr : u8 {
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B3_MT0_1 = (3 * 8 + 0),
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B3_MT2_3 = (3 * 8 + 1),
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B3_MT4_5 = (3 * 8 + 2),
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B3_MT6_7 = (3 * 8 + 3),
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B3_MGMT = (3 * 8 + 4),
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B3_REVISION = (3 * 8 + 5),
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B3_ERCV = (3 * 8 + 6)
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};
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// Ethernet MMU commands
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enum mmu_cmd : u8 {
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ECMD_NOP = 0,
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ECMD_ALLOCATE = 2,
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ECMD_RESET_MMU = 4,
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ECMD_REMOVE_TOPFRAME_RX = 6,
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ECMD_REMOVE_TOPFRAME_TX = 7,
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ECMD_REMOVE_RELEASE_TOPFRAME_RX = 8,
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ECMD_RELEASE_PACKET = 10,
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ECMD_ENQUEUE_PACKET = 12,
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ECMD_RESET_FIFOS = 14
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};
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// Ethernet interrupt bits
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enum eint_def : u8 {
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EINT_RCV = 0x01,
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EINT_TX = 0x02,
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EINT_TX_EMPTY = 0x04,
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EINT_ALLOC = 0x08,
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EINT_RX_OVRN = 0x10,
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EINT_EPH = 0x20,
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EINT_ERCV = 0x40, // 91c92 only
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EINT_TX_IDLE = 0x80 // 91c94 only
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};
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// Address filter return codes
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enum addr_filter_def : int {
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ADDR_NOMATCH = 0,
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ADDR_UNICAST = 1,
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ADDR_BROADCAST = 2,
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ADDR_MULTICAST = 3
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};
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// Rx/Tx control bits
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enum control_mask : u8 {
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EBUF_RX_ALWAYS = 0x40, // Always set on receive buffer control byte
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EBUF_ODD = 0x20, // Odd number of data payload bytes
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EBUF_CRC = 0x10 // Tx add CRC
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};
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// Receive buffer status
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enum rx_status_mask : u16 {
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ALGNERR = 0x8000,
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BRODCAST = 0x4000,
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BADCRC = 0x2000,
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ODDFRM = 0x1000,
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TOOLNG = 0x0800, // Received fram is longer than 1518 bytes on cable
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TOOSHORT = 0x0400, // Received fram is shorter than 64 bytes on cable
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HASHVALUE = 0x007e,
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MULTCAST = 0x0001
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};
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// EPH Status bits
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enum eph_mask : u16 {
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LINK_OK = 0x4000, // State of link integrity test
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CTR_ROL = 0x1000, // Counter roll Over
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EXC_DEF = 0x0800, // Excessive deferral
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LOST_CARR = 0x0400, // Lost carrier sense
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LATCOL = 0x0200, // Late collisions detected
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WAKEUP = 0x0100, // Magic packet received
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TX_DEFER = 0x0080, // Transmit deferred
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LTX_BRD = 0x0040, // Last transmit frame was a broadcast
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SQET = 0x0020, // Signal Quality Error Test
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E16COL = 0x0010, // 16 collisions reached
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LTX_MULT = 0x0008, // Last transmit frame was a multicast
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MULCOL = 0x0004, // Multiple collisions detected
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SNGLCOL = 0x0002, // Single collision detected
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TX_SUC = 0x0001 // Last transmit frame was successful
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};
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// CTR register bits
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enum ctr_mask : u16 {
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RCV_BAD = 0x4000, // Receive bad CRC packets
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PWRDN = 0x2000, // Power down ethernet
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WAKEUP_EN = 0x1000, // Enable magic packet wakeup
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AUTO_RELEASE = 0x0800, // Release transmit packets on good transmission
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LE_ENABLE = 0x0080, // Link Error enable
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CR_ENABLE = 0x0040, // Counter Roll over enable
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TE_ENABLE = 0x0020, // Transmit Error enable
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EEPROM_SEL = 0x0004, // EEPROM address
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RELOAD = 0x0002, // Reload config from EEPROM
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STORE = 0x0001 // Store config to EEPROM
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};
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// Transmit Control Register bits
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enum tcr_mask : u16 {
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FDSE = 0x8000,
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EPH_LOOP = 0x2000,
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STP_SQET = 0x1000,
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FDUPLX = 0x0800,
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MON_CSN = 0x0400,
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NOCRC = 0x0100,
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PAD_EN = 0x0080,
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FORCOL = 0x0004,
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LOOP = 0x0002,
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TXENA = 0x0001
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};
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// Receive Control Register bits
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enum rcr_mask : u16 {
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SOFT_RST = 0x8000,
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FILT_CAR = 0x4000,
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STRIP_CRC = 0x0200,
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RXEN = 0x0100,
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ALMUL = 0x0004,
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PRMS = 0x0002,
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RX_ABORT = 0x0001
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};
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// Pointer Register bits
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enum pointer_mask : u16 {
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RCV = 0x8000,
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AUTO_INCR = 0x4000,
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READ = 0x2000,
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PTR = 0x07ff
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};
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static constexpr unsigned ETHER_BUFFER_SIZE = 256 * 6;
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static const u8 ETH_BROADCAST[];
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// mmu
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// The bits in these vectors indicate a packet has been allocated
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u32 m_alloc_rx, m_alloc_tx;
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std::vector<u32> m_comp_tx, m_comp_rx;
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// Fifo for allocated (queued) transmit packets
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std::vector<u32> m_trans_tx;
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// Save vector data and sizes for proper save state restoration
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u32 m_comp_tx_data[ETHER_BUFFERS], m_comp_rx_data[ETHER_BUFFERS], m_trans_tx_data[ETHER_BUFFERS];
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u32 m_comp_tx_size, m_comp_rx_size, m_trans_tx_size;
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// Requests a packet allocation and returns true
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// and sets the packet number if successful
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bool alloc_req(const int tx, int &packet_num);
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@ -77,23 +245,56 @@ private:
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uint8_t m_irq_state;
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// Main memory
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uint8_t m_buffer[ETHER_BUFFER_SIZE * ETHER_BUFFERS];
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std::unique_ptr<u8[]> m_buffer;
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/* counters */
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uint32_t m_sent;
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uint32_t m_recd;
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emu_timer* m_tx_timer;
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emu_timer* m_tx_poll;
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int ethernet_packet_is_for_me(const uint8_t *mac_address);
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int is_broadcast(const uint8_t *mac_address);
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int m_tx_active;
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int m_rx_active;
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int m_tx_retry_count;
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u8 m_rx_hash;
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u8 m_loopback_result;
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void update_ethernet_irq();
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void update_stats();
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void process_command(uint16_t data);
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void clear_tx_fifo();
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void clear_rx_fifo();
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void reset_tx_fifos();
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// TODO: Make circular fifo a separate device
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// Simple circular FIFO, power of 2 size, no over/under run checking
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static constexpr unsigned FIFO_SIZE = 1 << 5;
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// FIFO for allocated (queued) transmit packets
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u8 m_queued_tx[FIFO_SIZE];
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int m_queued_tx_h, m_queued_tx_t;
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void reset_queued_tx() { m_queued_tx_t = m_queued_tx_h = 0; };
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void push_queued_tx(const u8 &data) { m_queued_tx[m_queued_tx_h++] = data; m_queued_tx_h &= FIFO_SIZE - 1; };
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u8 pop_queued_tx() { u8 val = m_queued_tx[m_queued_tx_t++]; m_queued_tx_t &= FIFO_SIZE - 1; return val; };
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bool empty_queued_tx() { return m_queued_tx_h == m_queued_tx_t; };
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u8 curr_queued_tx() { return m_queued_tx[m_queued_tx_t]; };
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// FIFO for completed transmit packets
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u8 m_completed_tx[FIFO_SIZE];
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int m_completed_tx_h, m_completed_tx_t;
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void reset_completed_tx() { m_completed_tx_t = m_completed_tx_h = 0; };
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void push_completed_tx(const u8 &data) { m_completed_tx[m_completed_tx_h++] = data; m_completed_tx_h &= FIFO_SIZE - 1; };
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u8 pop_completed_tx() { u8 val = m_completed_tx[m_completed_tx_t++]; m_completed_tx_t &= FIFO_SIZE - 1; return val; };
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bool empty_completed_tx() { return m_completed_tx_h == m_completed_tx_t; };
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u8 curr_completed_tx() { return m_completed_tx[m_completed_tx_t]; };
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// FIFO for completed receive packets
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u8 m_completed_rx[FIFO_SIZE];
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int m_completed_rx_h, m_completed_rx_t;
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void reset_completed_rx() { m_completed_rx_t = m_completed_rx_h = 0; };
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void push_completed_rx(const u8 &data) { m_completed_rx[m_completed_rx_h++] = data; m_completed_rx_h &= FIFO_SIZE - 1; };
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u8 pop_completed_rx() { u8 val = m_completed_rx[m_completed_rx_t++]; m_completed_rx_t &= FIFO_SIZE - 1; return val; };
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bool empty_completed_rx() { return m_completed_rx_h == m_completed_rx_t; };
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u8 curr_completed_rx() { return m_completed_rx[m_completed_rx_t]; };
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};
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