mirror of
https://github.com/holub/mame
synced 2025-07-04 17:38:08 +03:00
Started to remove via port read handlers, prematurely stopped because IEEE488 code derives the clock from the read handler being called [smf]
This commit is contained in:
smf-
parent
86e75fa9c1
commit
be9a5785e4
@ -299,6 +299,12 @@ static MC6845_UPDATE_ROW( victor9k_update_row )
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}
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}
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WRITE_LINE_MEMBER(victor9k_state::vert_w)
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{
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m_via2->write_pa7(state);
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m_pic->ir7_w(state);
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}
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static MC6845_INTERFACE( hd46505s_intf )
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{
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false,
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@ -309,7 +315,7 @@ static MC6845_INTERFACE( hd46505s_intf )
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DEVCB_NULL,
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DEVCB_NULL,
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DEVCB_NULL,
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DEVCB_DEVICE_LINE_MEMBER(I8259A_TAG, pic8259_device, ir7_w),
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DEVCB_DRIVER_LINE_MEMBER(victor9k_state, vert_w),
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NULL
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};
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@ -442,36 +448,16 @@ WRITE8_MEMBER( victor9k_state::via1_pa_w )
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m_ieee488->dio_w(data);
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}
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READ8_MEMBER( victor9k_state::via1_pb_r )
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DECLARE_WRITE_LINE_MEMBER( victor9k_state::write_nfrd )
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{
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/*
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m_via1->write_pb6(state);
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m_via1->write_ca1(state);
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}
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bit description
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PB0 DAV
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PB1 EOI
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PB2 REN
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PB3 ATN
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PB4 IFC
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PB5 SRQ
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PB6 NRFD
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PB7 NDAC
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*/
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UINT8 data = 0;
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// IEEE-488
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data |= m_ieee488->dav_r();
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data |= m_ieee488->eoi_r() << 1;
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data |= m_ieee488->ren_r() << 2;
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data |= m_ieee488->atn_r() << 3;
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data |= m_ieee488->ifc_r() << 4;
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data |= m_ieee488->srq_r() << 5;
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data |= m_ieee488->nrfd_r() << 6;
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data |= m_ieee488->ndac_r() << 7;
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return data;
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DECLARE_WRITE_LINE_MEMBER( victor9k_state::write_ndac )
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{
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m_via1->write_pb7(state);
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m_via1->write_ca2(state);
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}
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WRITE8_MEMBER( victor9k_state::via1_pb_w )
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@ -513,41 +499,6 @@ WRITE_LINE_MEMBER( victor9k_state::via1_irq_w )
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m_pic->ir3_w(m_ssda_irq || m_via1_irq || m_via2_irq || m_via3_irq || m_via4_irq || m_via5_irq || m_via6_irq);
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}
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READ8_MEMBER( victor9k_state::via2_pa_r )
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{
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/*
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bit description
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PA0
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PA1
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PA2 RIA
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PA3 DSRA
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PA4 RIB
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PA5 DSRB
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PA6 KBDATA
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PA7 VERT
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*/
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UINT8 data = 0;
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// serial
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data |= m_rs232a->ri_r() << 2;
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data |= m_rs232a->dsr_r() << 3;
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data |= m_rs232b->ri_r() << 4;
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data |= m_rs232b->dsr_r() << 5;
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// keyboard data
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data |= m_kb->kbdata_r() << 6;
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// vertical sync
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data |= m_crtc->vsync_r() << 7;
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return data;
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}
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WRITE8_MEMBER( victor9k_state::via2_pa_w )
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{
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/*
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@ -593,6 +544,21 @@ WRITE8_MEMBER( victor9k_state::via2_pb_w )
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m_cont = data >> 5;
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}
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WRITE_LINE_MEMBER( victor9k_state::write_ria )
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{
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m_upd7201->ria_w(state);
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m_via2->write_pa2(state);
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}
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WRITE_LINE_MEMBER( victor9k_state::write_rib )
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{
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m_upd7201->rib_w(state);
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m_via2->write_pa4(state);
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}
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WRITE_LINE_MEMBER( victor9k_state::via2_irq_w )
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{
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m_via2_irq = state;
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@ -601,81 +567,33 @@ WRITE_LINE_MEMBER( victor9k_state::via2_irq_w )
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}
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READ8_MEMBER( victor9k_state::via3_pa_r )
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{
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/*
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/*
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bit description
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bit description
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PA0 J5-16
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PA1 J5-18
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PA2 J5-20
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PA3 J5-22
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PA4 J5-24
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PA5 J5-26
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PA6 J5-28
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PA7 J5-30
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*/
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return 0;
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}
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WRITE8_MEMBER( victor9k_state::via3_pa_w )
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{
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/*
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bit description
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PA0 J5-16
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PA1 J5-18
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PA2 J5-20
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PA3 J5-22
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PA4 J5-24
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PA5 J5-26
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PA6 J5-28
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PA7 J5-30
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*/
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}
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READ8_MEMBER( victor9k_state::via3_pb_r )
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{
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/*
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bit description
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PB0 J5-32
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PB1 J5-34
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PB2 J5-36
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PB3 J5-38
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PB4 J5-40
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PB5 J5-42
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PB6 J5-44
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PB7 J5-46
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*/
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return 0;
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}
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PA0 J5-16
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PA1 J5-18
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PA2 J5-20
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PA3 J5-22
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PA4 J5-24
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PA5 J5-26
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PA6 J5-28
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PA7 J5-30
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PB0 J5-32
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PB1 J5-34
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PB2 J5-36
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PB3 J5-38
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PB4 J5-40
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PB5 J5-42
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PB6 J5-44
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PB7 J5-46
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CA1 J5-12
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CB1 J5-48
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CA2 J5-14
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CB2 J5-50
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*/
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WRITE8_MEMBER( victor9k_state::via3_pb_w )
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{
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/*
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bit description
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PB0 J5-32
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PB1 J5-34
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PB2 J5-36
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PB3 J5-38
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PB4 J5-40
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PB5 J5-42
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PB6 J5-44
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PB7 J5-46
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*/
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// codec clock output
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m_ssda->rx_clk_w(BIT(data, 7));
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m_ssda->tx_clk_w(BIT(data, 7));
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@ -743,25 +661,20 @@ WRITE_LINE_MEMBER( victor9k_state::via4_irq_w )
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}
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READ8_MEMBER( victor9k_state::via5_pa_r )
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{
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/*
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/*
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bit description
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bit description
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PA0 E0
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PA1 E1
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PA2 I1
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PA3 E2
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PA4 E4
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PA5 E5
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PA6 I7
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PA7 E6
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PA0 E0
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PA1 E1
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PA2 I1
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PA3 E2
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PA4 E4
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PA5 E5
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PA6 I7
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PA7 E6
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*/
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return 0;
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}
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*/
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WRITE8_MEMBER( victor9k_state::via5_pb_w )
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{
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@ -945,6 +858,11 @@ WRITE_LINE_MEMBER( victor9k_state::kbrdy_w )
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m_pic->ir6_w(state ? CLEAR_LINE : ASSERT_LINE);
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}
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WRITE_LINE_MEMBER( victor9k_state::kbdata_w )
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{
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m_via2->write_cb2(state);
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m_via2->write_pa6(state);
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}
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//-------------------------------------------------
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// SLOT_INTERFACE( victor9k_floppies )
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@ -1068,8 +986,15 @@ static MACHINE_CONFIG_START( victor9k, victor9k_state )
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// devices
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MCFG_IEEE488_BUS_ADD()
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MCFG_IEEE488_NRFD_CALLBACK(DEVWRITELINE(M6522_1_TAG, via6522_device, write_ca1))
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MCFG_IEEE488_NDAC_CALLBACK(DEVWRITELINE(M6522_1_TAG, via6522_device, write_ca2))
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MCFG_IEEE488_DAV_CALLBACK(DEVWRITELINE(M6522_1_TAG, via6522_device, write_pb0))
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MCFG_IEEE488_EOI_CALLBACK(DEVWRITELINE(M6522_1_TAG, via6522_device, write_pb1))
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MCFG_IEEE488_REN_CALLBACK(DEVWRITELINE(M6522_1_TAG, via6522_device, write_pb2))
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MCFG_IEEE488_ATN_CALLBACK(DEVWRITELINE(M6522_1_TAG, via6522_device, write_pb3))
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MCFG_IEEE488_IFC_CALLBACK(DEVWRITELINE(M6522_1_TAG, via6522_device, write_pb4))
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MCFG_IEEE488_SRQ_CALLBACK(DEVWRITELINE(M6522_1_TAG, via6522_device, write_pb5))
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MCFG_IEEE488_NRFD_CALLBACK(WRITELINE(victor9k_state, write_nfrd))
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MCFG_IEEE488_NDAC_CALLBACK(WRITELINE(victor9k_state, write_ndac))
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MCFG_PIC8259_ADD(I8259A_TAG, INPUTLINE(I8088_TAG, INPUT_LINE_IRQ0), VCC, NULL)
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MCFG_PIT8253_ADD(I8253_TAG, pit_intf)
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MCFG_UPD7201_ADD(UPD7201_TAG, XTAL_30MHz/30, mpsc_intf)
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@ -1077,26 +1002,17 @@ static MACHINE_CONFIG_START( victor9k, victor9k_state )
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MCFG_DEVICE_ADD(M6522_1_TAG, VIA6522, XTAL_30MHz/30)
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MCFG_VIA6522_READPA_HANDLER(DEVREAD8(IEEE488_TAG, ieee488_device, dio_r))
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MCFG_VIA6522_READPB_HANDLER(READ8(victor9k_state, via1_pb_r))
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MCFG_VIA6522_WRITEPA_HANDLER(WRITE8(victor9k_state, via1_pa_w))
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MCFG_VIA6522_WRITEPB_HANDLER(WRITE8(victor9k_state, via1_pb_w))
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MCFG_VIA6522_CB2_HANDLER(WRITELINE(victor9k_state, codec_vol_w))
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MCFG_VIA6522_IRQ_HANDLER(WRITELINE(victor9k_state, via1_irq_w))
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MCFG_DEVICE_ADD(M6522_2_TAG, VIA6522, XTAL_30MHz/30)
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MCFG_VIA6522_READPA_HANDLER(READ8(victor9k_state, via2_pa_r))
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MCFG_VIA6522_WRITEPA_HANDLER(WRITE8(victor9k_state, via2_pa_w))
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MCFG_VIA6522_WRITEPB_HANDLER(WRITE8(victor9k_state, via2_pb_w))
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MCFG_VIA6522_IRQ_HANDLER(WRITELINE(victor9k_state, via2_irq_w))
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MCFG_DEVICE_ADD(M6522_3_TAG, VIA6522, XTAL_30MHz/30)
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MCFG_VIA6522_READPA_HANDLER(READ8(victor9k_state, via3_pa_r))
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MCFG_VIA6522_READPB_HANDLER(READ8(victor9k_state, via3_pb_r))
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// CA1 J5-12
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// CB1 J5-48
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// CA2 J5-14
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// CB2 J5-50
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MCFG_VIA6522_WRITEPA_HANDLER(WRITE8(victor9k_state, via3_pa_w))
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MCFG_VIA6522_WRITEPB_HANDLER(WRITE8(victor9k_state, via3_pb_w))
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MCFG_VIA6522_IRQ_HANDLER(WRITELINE(victor9k_state, via3_irq_w))
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@ -1107,8 +1023,6 @@ static MACHINE_CONFIG_START( victor9k, victor9k_state )
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MCFG_VIA6522_IRQ_HANDLER(WRITELINE(victor9k_state, via4_irq_w))
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MCFG_DEVICE_ADD(M6522_5_TAG, VIA6522, XTAL_30MHz/30)
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MCFG_VIA6522_READPA_HANDLER(READ8(victor9k_state, via5_pa_r))
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MCFG_VIA6522_WRITEPB_HANDLER(WRITE8(victor9k_state, via5_pb_w))
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MCFG_VIA6522_IRQ_HANDLER(WRITELINE(victor9k_state, via5_irq_w))
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MCFG_DEVICE_ADD(M6522_6_TAG, VIA6522, XTAL_30MHz/30)
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@ -1126,18 +1040,20 @@ static MACHINE_CONFIG_START( victor9k, victor9k_state )
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MCFG_RS232_PORT_ADD(RS232_A_TAG, default_rs232_devices, NULL)
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MCFG_SERIAL_OUT_RX_HANDLER(DEVWRITELINE(UPD7201_TAG, z80dart_device, rxa_w))
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MCFG_RS232_OUT_DCD_HANDLER(DEVWRITELINE(UPD7201_TAG, z80dart_device, dcda_w))
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MCFG_RS232_OUT_RI_HANDLER(DEVWRITELINE(UPD7201_TAG, z80dart_device, ria_w))
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MCFG_RS232_OUT_RI_HANDLER(WRITELINE(victor9k_state, write_ria))
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MCFG_RS232_OUT_CTS_HANDLER(DEVWRITELINE(UPD7201_TAG, z80dart_device, ctsa_w))
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MCFG_RS232_OUT_DSR_HANDLER(DEVWRITELINE(M6522_2_TAG, via6522_device, write_pa3))
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MCFG_RS232_PORT_ADD(RS232_B_TAG, default_rs232_devices, NULL)
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MCFG_SERIAL_OUT_RX_HANDLER(DEVWRITELINE(UPD7201_TAG, z80dart_device, rxb_w))
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MCFG_RS232_OUT_DCD_HANDLER(DEVWRITELINE(UPD7201_TAG, z80dart_device, dcdb_w))
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MCFG_RS232_OUT_RI_HANDLER(DEVWRITELINE(UPD7201_TAG, z80dart_device, rib_w))
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MCFG_RS232_OUT_RI_HANDLER(WRITELINE(victor9k_state, write_ria))
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MCFG_RS232_OUT_CTS_HANDLER(DEVWRITELINE(UPD7201_TAG, z80dart_device, ctsb_w))
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MCFG_RS232_OUT_DSR_HANDLER(DEVWRITELINE(M6522_2_TAG, via6522_device, write_pa5))
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MCFG_DEVICE_ADD(VICTOR9K_KEYBOARD_TAG, VICTOR9K_KEYBOARD, 0)
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MCFG_VICTOR9K_KBRDY_HANDLER(WRITELINE(victor9k_state, kbrdy_w))
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MCFG_VICTOR9K_KBDATA_HANDLER(DEVWRITELINE(M6522_2_TAG, via6522_device, write_cb2))
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MCFG_VICTOR9K_KBDATA_HANDLER(WRITELINE(victor9k_state, kbdata_w))
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// internal ram
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MCFG_RAM_ADD(RAM_TAG)
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@ -62,6 +62,7 @@ public:
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m_fdc_cpu(*this, I8048_TAG),
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m_ieee488(*this, IEEE488_TAG),
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m_pic(*this, I8259A_TAG),
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m_upd7201(*this, UPD7201_TAG),
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m_ssda(*this, MC6852_TAG),
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m_via1(*this, M6522_1_TAG),
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m_via2(*this, M6522_2_TAG),
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@ -99,6 +100,7 @@ public:
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required_device<cpu_device> m_fdc_cpu;
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required_device<ieee488_device> m_ieee488;
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required_device<pic8259_device> m_pic;
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required_device<upd7201_device> m_upd7201;
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required_device<mc6852_device> m_ssda;
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required_device<via6522_device> m_via1;
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required_device<via6522_device> m_via2;
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@ -125,19 +127,18 @@ public:
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DECLARE_WRITE8_MEMBER( da_w );
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DECLARE_WRITE8_MEMBER( via1_pa_w );
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DECLARE_READ8_MEMBER( via1_pb_r );
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DECLARE_WRITE_LINE_MEMBER( write_nfrd );
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DECLARE_WRITE_LINE_MEMBER( write_ndac );
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DECLARE_WRITE8_MEMBER( via1_pb_w );
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DECLARE_WRITE_LINE_MEMBER( via1_irq_w );
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DECLARE_WRITE_LINE_MEMBER( codec_vol_w );
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DECLARE_READ8_MEMBER( via2_pa_r );
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DECLARE_WRITE8_MEMBER( via2_pa_w );
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DECLARE_WRITE8_MEMBER( via2_pb_w );
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DECLARE_WRITE_LINE_MEMBER( write_ria );
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DECLARE_WRITE_LINE_MEMBER( write_rib );
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DECLARE_WRITE_LINE_MEMBER( via2_irq_w );
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DECLARE_READ8_MEMBER( via3_pa_r );
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DECLARE_READ8_MEMBER( via3_pb_r );
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DECLARE_WRITE8_MEMBER( via3_pa_w );
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DECLARE_WRITE8_MEMBER( via3_pb_w );
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DECLARE_WRITE_LINE_MEMBER( via3_irq_w );
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@ -146,7 +147,6 @@ public:
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DECLARE_WRITE_LINE_MEMBER( mode_w );
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DECLARE_WRITE_LINE_MEMBER( via4_irq_w );
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DECLARE_READ8_MEMBER( via5_pa_r );
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DECLARE_WRITE8_MEMBER( via5_pb_w );
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DECLARE_WRITE_LINE_MEMBER( via5_irq_w );
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@ -157,6 +157,8 @@ public:
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DECLARE_WRITE_LINE_MEMBER( drw_w );
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DECLARE_WRITE_LINE_MEMBER( erase_w );
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DECLARE_WRITE_LINE_MEMBER( kbrdy_w );
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DECLARE_WRITE_LINE_MEMBER( kbdata_w );
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DECLARE_WRITE_LINE_MEMBER( vert_w );
|
||||
DECLARE_WRITE_LINE_MEMBER( via6_irq_w );
|
||||
|
||||
DECLARE_WRITE_LINE_MEMBER( ssda_irq_w );
|
||||
|
||||
Loading…
Reference in New Issue
Block a user