mirror of
https://github.com/holub/mame
synced 2025-04-25 09:50:04 +03:00
tmpz84c011c small cleanup.
note: if you want a handler for logging unmapped read/write, put it in the driver machine config, like we do with 8255, for example:
MCFG_I8255_OUT_PORTB_CB(LOGGER("PPI8255 - unmapped write port B", 0))
This commit is contained in:
Michaël Banaan Ananas
parent
f1f05fcb07
commit
bf43a3db23
@ -1,258 +1,83 @@
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/***************************************************************************
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Toshiba TMPZ84C011, TLCS-Z80 ASSP Family
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Z80 CPU, CTC, CGC(6/8MHz), I/O8x5
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TODO:
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- CGC (clock generator/controller)
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***************************************************************************/
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#include "tmpz84c011.h"
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// how do we actually install default handlers for logging?
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/*
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READ8_MEMBER(tmpz84c011_device::porta_default_r) { logerror("%s read port A but no handler assigned\n", machine().describe_context()); return 0xff; }
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READ8_MEMBER(tmpz84c011_device::portb_default_r) { logerror("%s read port B but no handler assigned\n", machine().describe_context()); return 0xff; }
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READ8_MEMBER(tmpz84c011_device::portc_default_r) { logerror("%s read port C but no handler assigned\n", machine().describe_context()); return 0xff; }
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READ8_MEMBER(tmpz84c011_device::portd_default_r) { logerror("%s read port D but no handler assigned\n", machine().describe_context()); return 0xff; }
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READ8_MEMBER(tmpz84c011_device::porte_default_r) { logerror("%s read port E but no handler assigned\n", machine().describe_context()); return 0xff; }
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WRITE8_MEMBER(tmpz84c011_device::porta_default_w) { logerror("%s write %02x to port A but no handler assigned\n", machine().describe_context(), data); }
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WRITE8_MEMBER(tmpz84c011_device::portb_default_w) { logerror("%s write %02x to port B but no handler assigned\n", machine().describe_context(), data); }
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WRITE8_MEMBER(tmpz84c011_device::portc_default_w) { logerror("%s write %02x to port C but no handler assigned\n", machine().describe_context(), data); }
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WRITE8_MEMBER(tmpz84c011_device::portd_default_w) { logerror("%s write %02x to port D but no handler assigned\n", machine().describe_context(), data); }
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WRITE8_MEMBER(tmpz84c011_device::porte_default_w) { logerror("%s write %02x to port E but no handler assigned\n", machine().describe_context(), data); }
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*/
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READ8_MEMBER(tmpz84c011_device::tmpz84c011_pio_r)
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{
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int portdata = 0xff;
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switch (offset)
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{
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case 0: /* PA_0 */
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portdata = m_inports0();
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break;
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case 1: /* PB_0 */
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portdata = m_inports1();
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break;
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case 2: /* PC_0 */
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portdata = m_inports2();
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break;
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case 3: /* PD_0 */
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portdata = m_inports3();
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break;
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case 4: /* PE_0 */
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portdata = m_inports4();
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break;
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}
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return portdata;
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}
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WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_pio_w)
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{
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switch (offset)
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{
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case 0: /* PA_0 */
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m_outports0(data);
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break;
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case 1: /* PB_0 */
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m_outports1(data);
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break;
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case 2: /* PC_0 */
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m_outports2(data);
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break;
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case 3: /* PD_0 */
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m_outports3(data);
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break;
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case 4: /* PE_0 */
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m_outports4(data);
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break;
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}
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}
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/* CPU interface */
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READ8_MEMBER(tmpz84c011_device::tmpz84c011_0_pa_r)
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{
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return (tmpz84c011_pio_r(space,0) & ~m_pio_dir[0]) | (m_pio_latch[0] & m_pio_dir[0]);
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}
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READ8_MEMBER(tmpz84c011_device::tmpz84c011_0_pb_r)
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{
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return (tmpz84c011_pio_r(space,1) & ~m_pio_dir[1]) | (m_pio_latch[1] & m_pio_dir[1]);
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}
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READ8_MEMBER(tmpz84c011_device::tmpz84c011_0_pc_r)
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{
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return (tmpz84c011_pio_r(space,2) & ~m_pio_dir[2]) | (m_pio_latch[2] & m_pio_dir[2]);
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}
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READ8_MEMBER(tmpz84c011_device::tmpz84c011_0_pd_r)
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{
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return (tmpz84c011_pio_r(space,3) & ~m_pio_dir[3]) | (m_pio_latch[3] & m_pio_dir[3]);
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}
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READ8_MEMBER(tmpz84c011_device::tmpz84c011_0_pe_r)
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{
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return (tmpz84c011_pio_r(space,4) & ~m_pio_dir[4]) | (m_pio_latch[4] & m_pio_dir[4]);
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}
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WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_0_pa_w)
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{
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m_pio_latch[0] = data;
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tmpz84c011_pio_w(space, 0, data);
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}
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WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_0_pb_w)
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{
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m_pio_latch[1] = data;
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tmpz84c011_pio_w(space, 1, data);
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}
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WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_0_pc_w)
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{
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m_pio_latch[2] = data;
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tmpz84c011_pio_w(space, 2, data);
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}
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WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_0_pd_w)
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{
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m_pio_latch[3] = data;
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tmpz84c011_pio_w(space, 3, data);
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}
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WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_0_pe_w)
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{
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m_pio_latch[4] = data;
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tmpz84c011_pio_w(space, 4, data);
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}
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READ8_MEMBER(tmpz84c011_device::tmpz84c011_0_dir_pa_r)
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{
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return m_pio_dir[0];
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}
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READ8_MEMBER(tmpz84c011_device::tmpz84c011_0_dir_pb_r)
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{
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return m_pio_dir[1];
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}
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READ8_MEMBER(tmpz84c011_device::tmpz84c011_0_dir_pc_r)
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{
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return m_pio_dir[2];
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}
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READ8_MEMBER(tmpz84c011_device::tmpz84c011_0_dir_pd_r)
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{
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return m_pio_dir[3];
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}
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READ8_MEMBER(tmpz84c011_device::tmpz84c011_0_dir_pe_r)
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{
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return m_pio_dir[4];
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}
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WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_0_dir_pa_w)
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{
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m_pio_dir[0] = data;
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}
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WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_0_dir_pb_w)
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{
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m_pio_dir[1] = data;
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}
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WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_0_dir_pc_w)
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{
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m_pio_dir[2] = data;
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}
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WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_0_dir_pd_w)
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{
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m_pio_dir[3] = data;
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}
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WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_0_dir_pe_w)
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{
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m_pio_dir[4] = data;
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}
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const device_type TMPZ84C011 = &device_creator<tmpz84c011_device>;
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static ADDRESS_MAP_START( tmpz84c011_internal_io_map, AS_IO, 8, tmpz84c011_device )
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AM_RANGE(0x10, 0x13) AM_DEVREADWRITE("ctc", z80ctc_device, read, write) AM_MIRROR(0xff00)
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AM_RANGE(0x50, 0x50) AM_READWRITE(tmpz84c011_0_pa_r, tmpz84c011_0_pa_w) AM_MIRROR(0xff00)
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AM_RANGE(0x51, 0x51) AM_READWRITE(tmpz84c011_0_pb_r, tmpz84c011_0_pb_w) AM_MIRROR(0xff00)
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AM_RANGE(0x52, 0x52) AM_READWRITE(tmpz84c011_0_pc_r, tmpz84c011_0_pc_w) AM_MIRROR(0xff00)
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AM_RANGE(0x30, 0x30) AM_READWRITE(tmpz84c011_0_pd_r, tmpz84c011_0_pd_w) AM_MIRROR(0xff00)
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AM_RANGE(0x40, 0x40) AM_READWRITE(tmpz84c011_0_pe_r, tmpz84c011_0_pe_w) AM_MIRROR(0xff00)
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AM_RANGE(0x54, 0x54) AM_READWRITE(tmpz84c011_0_dir_pa_r, tmpz84c011_0_dir_pa_w) AM_MIRROR(0xff00)
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AM_RANGE(0x55, 0x55) AM_READWRITE(tmpz84c011_0_dir_pb_r, tmpz84c011_0_dir_pb_w) AM_MIRROR(0xff00)
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AM_RANGE(0x56, 0x56) AM_READWRITE(tmpz84c011_0_dir_pc_r, tmpz84c011_0_dir_pc_w) AM_MIRROR(0xff00)
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AM_RANGE(0x34, 0x34) AM_READWRITE(tmpz84c011_0_dir_pd_r, tmpz84c011_0_dir_pd_w) AM_MIRROR(0xff00)
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AM_RANGE(0x44, 0x44) AM_READWRITE(tmpz84c011_0_dir_pe_r, tmpz84c011_0_dir_pe_w) AM_MIRROR(0xff00)
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AM_RANGE(0x50, 0x50) AM_READWRITE(tmpz84c011_pa_r, tmpz84c011_pa_w) AM_MIRROR(0xff00)
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AM_RANGE(0x51, 0x51) AM_READWRITE(tmpz84c011_pb_r, tmpz84c011_pb_w) AM_MIRROR(0xff00)
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AM_RANGE(0x52, 0x52) AM_READWRITE(tmpz84c011_pc_r, tmpz84c011_pc_w) AM_MIRROR(0xff00)
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AM_RANGE(0x30, 0x30) AM_READWRITE(tmpz84c011_pd_r, tmpz84c011_pd_w) AM_MIRROR(0xff00)
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AM_RANGE(0x40, 0x40) AM_READWRITE(tmpz84c011_pe_r, tmpz84c011_pe_w) AM_MIRROR(0xff00)
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AM_RANGE(0x54, 0x54) AM_READWRITE(tmpz84c011_dir_pa_r, tmpz84c011_dir_pa_w) AM_MIRROR(0xff00)
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AM_RANGE(0x55, 0x55) AM_READWRITE(tmpz84c011_dir_pb_r, tmpz84c011_dir_pb_w) AM_MIRROR(0xff00)
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AM_RANGE(0x56, 0x56) AM_READWRITE(tmpz84c011_dir_pc_r, tmpz84c011_dir_pc_w) AM_MIRROR(0xff00)
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AM_RANGE(0x34, 0x34) AM_READWRITE(tmpz84c011_dir_pd_r, tmpz84c011_dir_pd_w) AM_MIRROR(0xff00)
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AM_RANGE(0x44, 0x44) AM_READWRITE(tmpz84c011_dir_pe_r, tmpz84c011_dir_pe_w) AM_MIRROR(0xff00)
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ADDRESS_MAP_END
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tmpz84c011_device::tmpz84c011_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
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: z80_device(mconfig, TMPZ84C011, "TMPZ84C011", tag, owner, clock, "tmpz84c011", __FILE__),
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m_io_space_config( "io", ENDIANNESS_LITTLE, 8, 16, 0, ADDRESS_MAP_NAME( tmpz84c011_internal_io_map ) ),
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m_outports0(*this),
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m_outports1(*this),
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m_outports2(*this),
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m_outports3(*this),
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m_outports4(*this),
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m_inports0(*this),
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m_inports1(*this),
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m_inports2(*this),
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m_inports3(*this),
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m_inports4(*this),
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m_outportsa(*this),
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m_outportsb(*this),
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m_outportsc(*this),
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m_outportsd(*this),
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m_outportse(*this),
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m_inportsa(*this),
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m_inportsb(*this),
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m_inportsc(*this),
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m_inportsd(*this),
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m_inportse(*this),
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m_intr_cb(*this),
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m_zc0_cb(*this),
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m_zc1_cb(*this),
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m_zc2_cb(*this)
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{
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memset(m_pio_dir, 0, 5);
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memset(m_pio_latch, 0, 5);
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}
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WRITE_LINE_MEMBER( tmpz84c011_device::intr_cb_trampoline_w ) { m_intr_cb(state); }
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WRITE_LINE_MEMBER( tmpz84c011_device::zc0_cb_trampoline_w ) { m_zc0_cb(state); }
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WRITE_LINE_MEMBER( tmpz84c011_device::zc1_cb_trampoline_w ) { m_zc1_cb(state); }
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WRITE_LINE_MEMBER( tmpz84c011_device::zc2_cb_trampoline_w ) { m_zc2_cb(state); }
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const device_type TMPZ84C011 = &device_creator<tmpz84c011_device>;
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static MACHINE_CONFIG_FRAGMENT( tmpz84c011 )
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MCFG_DEVICE_ADD("ctc", Z80CTC, DERIVED_CLOCK(1,1) )
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MCFG_Z80CTC_INTR_CB(WRITELINE(tmpz84c011_device, intr_cb_trampoline_w))
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MCFG_Z80CTC_ZC0_CB(WRITELINE(tmpz84c011_device, zc0_cb_trampoline_w))
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MCFG_Z80CTC_ZC1_CB(WRITELINE(tmpz84c011_device, zc1_cb_trampoline_w))
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MCFG_Z80CTC_ZC2_CB(WRITELINE(tmpz84c011_device, zc2_cb_trampoline_w))
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MACHINE_CONFIG_END
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machine_config_constructor tmpz84c011_device::device_mconfig_additions() const
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{
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return MACHINE_CONFIG_NAME( tmpz84c011 );
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}
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//-------------------------------------------------
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// device_start - device-specific startup
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//-------------------------------------------------
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void tmpz84c011_device::device_start()
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{
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z80_device::device_start();
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m_outports0.resolve_safe();
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m_outports1.resolve_safe();
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m_outports2.resolve_safe();
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m_outports3.resolve_safe();
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m_outports4.resolve_safe();
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// resolve callbacks
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m_outportsa.resolve_safe();
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m_outportsb.resolve_safe();
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m_outportsc.resolve_safe();
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m_outportsd.resolve_safe();
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m_outportse.resolve_safe();
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m_inports0.resolve_safe(0);
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m_inports1.resolve_safe(0);
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m_inports2.resolve_safe(0);
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m_inports3.resolve_safe(0);
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m_inports4.resolve_safe(0);
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m_inportsa.resolve_safe(0);
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m_inportsb.resolve_safe(0);
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m_inportsc.resolve_safe(0);
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m_inportsd.resolve_safe(0);
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m_inportse.resolve_safe(0);
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m_intr_cb.resolve_safe();
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m_zc0_cb.resolve_safe();
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m_zc1_cb.resolve_safe();
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m_zc2_cb.resolve_safe();
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// register for save states
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save_item(NAME(m_pio_dir[0]));
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save_item(NAME(m_pio_latch[0]));
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save_item(NAME(m_pio_dir[1]));
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@ -263,20 +88,147 @@ void tmpz84c011_device::device_start()
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save_item(NAME(m_pio_latch[3]));
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save_item(NAME(m_pio_dir[4]));
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save_item(NAME(m_pio_latch[4]));
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}
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//-------------------------------------------------
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// device_reset - device-specific reset
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//-------------------------------------------------
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void tmpz84c011_device::device_reset()
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{
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z80_device::device_reset();
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// initialize TMPZ84C011 PIO
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for (int i = 0; i < 5; i++)
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{
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m_pio_dir[i] = m_pio_latch[i] = 0;
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tmpz84c011_pio_w(*m_io, i, 0);
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}
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tmpz84c011_dir_pa_w(*m_io, 0, 0); tmpz84c011_pa_w(*m_io, 0, 0xff);
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tmpz84c011_dir_pb_w(*m_io, 0, 0); tmpz84c011_pb_w(*m_io, 0, 0xff);
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tmpz84c011_dir_pc_w(*m_io, 0, 0); tmpz84c011_pc_w(*m_io, 0, 0xff);
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tmpz84c011_dir_pd_w(*m_io, 0, 0); tmpz84c011_pd_w(*m_io, 0, 0xff);
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tmpz84c011_dir_pe_w(*m_io, 0, 0); tmpz84c011_pe_w(*m_io, 0, 0xff);
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}
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/* CPU interface */
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READ8_MEMBER(tmpz84c011_device::tmpz84c011_pa_r)
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{
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return (m_inportsa() & ~m_pio_dir[0]) | (m_pio_latch[0] & m_pio_dir[0]);
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}
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READ8_MEMBER(tmpz84c011_device::tmpz84c011_pb_r)
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{
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return (m_inportsb() & ~m_pio_dir[1]) | (m_pio_latch[1] & m_pio_dir[1]);
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}
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READ8_MEMBER(tmpz84c011_device::tmpz84c011_pc_r)
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{
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return (m_inportsc() & ~m_pio_dir[2]) | (m_pio_latch[2] & m_pio_dir[2]);
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}
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READ8_MEMBER(tmpz84c011_device::tmpz84c011_pd_r)
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{
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return (m_inportsd() & ~m_pio_dir[3]) | (m_pio_latch[3] & m_pio_dir[3]);
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}
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READ8_MEMBER(tmpz84c011_device::tmpz84c011_pe_r)
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{
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||||
return (m_inportse() & ~m_pio_dir[4]) | (m_pio_latch[4] & m_pio_dir[4]);
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_pa_w)
|
||||
{
|
||||
m_pio_latch[0] = data;
|
||||
m_outportsa(data | ~m_pio_dir[0]);
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_pb_w)
|
||||
{
|
||||
m_pio_latch[1] = data;
|
||||
m_outportsb(data | ~m_pio_dir[1]);
|
||||
}
|
||||
WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_pc_w)
|
||||
{
|
||||
m_pio_latch[2] = data;
|
||||
m_outportsc(data | ~m_pio_dir[2]);
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_pd_w)
|
||||
{
|
||||
m_pio_latch[3] = data;
|
||||
m_outportsd(data | ~m_pio_dir[3]);
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_pe_w)
|
||||
{
|
||||
m_pio_latch[4] = data;
|
||||
m_outportse(data | ~m_pio_dir[4]);
|
||||
}
|
||||
|
||||
READ8_MEMBER(tmpz84c011_device::tmpz84c011_dir_pa_r)
|
||||
{
|
||||
return m_pio_dir[0];
|
||||
}
|
||||
|
||||
READ8_MEMBER(tmpz84c011_device::tmpz84c011_dir_pb_r)
|
||||
{
|
||||
return m_pio_dir[1];
|
||||
}
|
||||
|
||||
READ8_MEMBER(tmpz84c011_device::tmpz84c011_dir_pc_r)
|
||||
{
|
||||
return m_pio_dir[2];
|
||||
}
|
||||
|
||||
READ8_MEMBER(tmpz84c011_device::tmpz84c011_dir_pd_r)
|
||||
{
|
||||
return m_pio_dir[3];
|
||||
}
|
||||
|
||||
READ8_MEMBER(tmpz84c011_device::tmpz84c011_dir_pe_r)
|
||||
{
|
||||
return m_pio_dir[4];
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_dir_pa_w)
|
||||
{
|
||||
m_pio_dir[0] = data;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_dir_pb_w)
|
||||
{
|
||||
m_pio_dir[1] = data;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_dir_pc_w)
|
||||
{
|
||||
m_pio_dir[2] = data;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_dir_pd_w)
|
||||
{
|
||||
m_pio_dir[3] = data;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(tmpz84c011_device::tmpz84c011_dir_pe_w)
|
||||
{
|
||||
m_pio_dir[4] = data;
|
||||
}
|
||||
|
||||
|
||||
WRITE_LINE_MEMBER( tmpz84c011_device::intr_cb_trampoline_w ) { m_intr_cb(state); }
|
||||
WRITE_LINE_MEMBER( tmpz84c011_device::zc0_cb_trampoline_w ) { m_zc0_cb(state); }
|
||||
WRITE_LINE_MEMBER( tmpz84c011_device::zc1_cb_trampoline_w ) { m_zc1_cb(state); }
|
||||
WRITE_LINE_MEMBER( tmpz84c011_device::zc2_cb_trampoline_w ) { m_zc2_cb(state); }
|
||||
|
||||
|
||||
static MACHINE_CONFIG_FRAGMENT( tmpz84c011 )
|
||||
MCFG_DEVICE_ADD("ctc", Z80CTC, DERIVED_CLOCK(1,1) )
|
||||
MCFG_Z80CTC_INTR_CB(WRITELINE(tmpz84c011_device, intr_cb_trampoline_w))
|
||||
MCFG_Z80CTC_ZC0_CB(WRITELINE(tmpz84c011_device, zc0_cb_trampoline_w))
|
||||
MCFG_Z80CTC_ZC1_CB(WRITELINE(tmpz84c011_device, zc1_cb_trampoline_w))
|
||||
MCFG_Z80CTC_ZC2_CB(WRITELINE(tmpz84c011_device, zc2_cb_trampoline_w))
|
||||
MACHINE_CONFIG_END
|
||||
|
||||
machine_config_constructor tmpz84c011_device::device_mconfig_additions() const
|
||||
{
|
||||
return MACHINE_CONFIG_NAME( tmpz84c011 );
|
||||
}
|
||||
|
||||
@ -1,39 +1,48 @@
|
||||
/***************************************************************************
|
||||
|
||||
Toshiba TMPZ84C011, TLCS-Z80 ASSP Family
|
||||
Z80 CPU, CTC, CGC(6/8MHz), I/O8x5
|
||||
|
||||
***************************************************************************/
|
||||
|
||||
#include "emu.h"
|
||||
#include "z80.h"
|
||||
|
||||
|
||||
// TMPZ84C011 PIO callbacks
|
||||
#define MCFG_TMPZ84C011_PORTA_READ_CB(_devcb) \
|
||||
devcb = &tmpz84c011_device::set_inports0_cb(*device, DEVCB_##_devcb);
|
||||
devcb = &tmpz84c011_device::set_inportsa_cb(*device, DEVCB_##_devcb);
|
||||
|
||||
#define MCFG_TMPZ84C011_PORTB_READ_CB(_devcb) \
|
||||
devcb = &tmpz84c011_device::set_inports1_cb(*device, DEVCB_##_devcb);
|
||||
devcb = &tmpz84c011_device::set_inportsb_cb(*device, DEVCB_##_devcb);
|
||||
|
||||
#define MCFG_TMPZ84C011_PORTC_READ_CB(_devcb) \
|
||||
devcb = &tmpz84c011_device::set_inports2_cb(*device, DEVCB_##_devcb);
|
||||
devcb = &tmpz84c011_device::set_inportsc_cb(*device, DEVCB_##_devcb);
|
||||
|
||||
#define MCFG_TMPZ84C011_PORTD_READ_CB(_devcb) \
|
||||
devcb = &tmpz84c011_device::set_inports3_cb(*device, DEVCB_##_devcb);
|
||||
devcb = &tmpz84c011_device::set_inportsd_cb(*device, DEVCB_##_devcb);
|
||||
|
||||
#define MCFG_TMPZ84C011_PORTE_READ_CB(_devcb) \
|
||||
devcb = &tmpz84c011_device::set_inports4_cb(*device, DEVCB_##_devcb);
|
||||
devcb = &tmpz84c011_device::set_inportse_cb(*device, DEVCB_##_devcb);
|
||||
|
||||
|
||||
#define MCFG_TMPZ84C011_PORTA_WRITE_CB(_devcb) \
|
||||
devcb = &tmpz84c011_device::set_outports0_cb(*device, DEVCB_##_devcb);
|
||||
devcb = &tmpz84c011_device::set_outportsa_cb(*device, DEVCB_##_devcb);
|
||||
|
||||
#define MCFG_TMPZ84C011_PORTB_WRITE_CB(_devcb) \
|
||||
devcb = &tmpz84c011_device::set_outports1_cb(*device, DEVCB_##_devcb);
|
||||
devcb = &tmpz84c011_device::set_outportsb_cb(*device, DEVCB_##_devcb);
|
||||
|
||||
#define MCFG_TMPZ84C011_PORTC_WRITE_CB(_devcb) \
|
||||
devcb = &tmpz84c011_device::set_outports2_cb(*device, DEVCB_##_devcb);
|
||||
devcb = &tmpz84c011_device::set_outportsc_cb(*device, DEVCB_##_devcb);
|
||||
|
||||
#define MCFG_TMPZ84C011_PORTD_WRITE_CB(_devcb) \
|
||||
devcb = &tmpz84c011_device::set_outports3_cb(*device, DEVCB_##_devcb);
|
||||
devcb = &tmpz84c011_device::set_outportsd_cb(*device, DEVCB_##_devcb);
|
||||
|
||||
#define MCFG_TMPZ84C011_PORTE_WRITE_CB(_devcb) \
|
||||
devcb = &tmpz84c011_device::set_outports4_cb(*device, DEVCB_##_devcb);
|
||||
devcb = &tmpz84c011_device::set_outportse_cb(*device, DEVCB_##_devcb);
|
||||
|
||||
|
||||
// CTC callbacks
|
||||
#define MCFG_TMPZ84C011_Z80CTC_INTR_CB(_devcb) \
|
||||
devcb = &tmpz84c011_device::set_intr_callback(*device, DEVCB_##_devcb);
|
||||
|
||||
@ -52,58 +61,43 @@ class tmpz84c011_device : public z80_device
|
||||
public:
|
||||
tmpz84c011_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32);
|
||||
|
||||
template<class _Object> static devcb_base & set_outports0_cb(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_outports0.set_callback(object); }
|
||||
template<class _Object> static devcb_base & set_outports1_cb(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_outports1.set_callback(object); }
|
||||
template<class _Object> static devcb_base & set_outports2_cb(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_outports2.set_callback(object); }
|
||||
template<class _Object> static devcb_base & set_outports3_cb(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_outports3.set_callback(object); }
|
||||
template<class _Object> static devcb_base & set_outports4_cb(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_outports4.set_callback(object); }
|
||||
template<class _Object> static devcb_base & set_outportsa_cb(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_outportsa.set_callback(object); }
|
||||
template<class _Object> static devcb_base & set_outportsb_cb(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_outportsb.set_callback(object); }
|
||||
template<class _Object> static devcb_base & set_outportsc_cb(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_outportsc.set_callback(object); }
|
||||
template<class _Object> static devcb_base & set_outportsd_cb(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_outportsd.set_callback(object); }
|
||||
template<class _Object> static devcb_base & set_outportse_cb(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_outportse.set_callback(object); }
|
||||
|
||||
template<class _Object> static devcb_base & set_inports0_cb(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_inports0.set_callback(object); }
|
||||
template<class _Object> static devcb_base & set_inports1_cb(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_inports1.set_callback(object); }
|
||||
template<class _Object> static devcb_base & set_inports2_cb(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_inports2.set_callback(object); }
|
||||
template<class _Object> static devcb_base & set_inports3_cb(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_inports3.set_callback(object); }
|
||||
template<class _Object> static devcb_base & set_inports4_cb(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_inports4.set_callback(object); }
|
||||
template<class _Object> static devcb_base & set_inportsa_cb(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_inportsa.set_callback(object); }
|
||||
template<class _Object> static devcb_base & set_inportsb_cb(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_inportsb.set_callback(object); }
|
||||
template<class _Object> static devcb_base & set_inportsc_cb(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_inportsc.set_callback(object); }
|
||||
template<class _Object> static devcb_base & set_inportsd_cb(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_inportsd.set_callback(object); }
|
||||
template<class _Object> static devcb_base & set_inportse_cb(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_inportse.set_callback(object); }
|
||||
|
||||
template<class _Object> static devcb_base &set_intr_callback(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_intr_cb.set_callback(object); }
|
||||
template<class _Object> static devcb_base &set_zc0_callback(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_zc0_cb.set_callback(object); }
|
||||
template<class _Object> static devcb_base &set_zc1_callback(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_zc1_cb.set_callback(object); }
|
||||
template<class _Object> static devcb_base &set_zc2_callback(device_t &device, _Object object) { return downcast<tmpz84c011_device &>(device).m_zc2_cb.set_callback(object); }
|
||||
|
||||
|
||||
DECLARE_READ8_MEMBER(tmpz84c011_pio_r);
|
||||
DECLARE_WRITE8_MEMBER(tmpz84c011_pio_w);
|
||||
DECLARE_READ8_MEMBER(tmpz84c011_0_pa_r);
|
||||
DECLARE_READ8_MEMBER(tmpz84c011_0_pb_r);
|
||||
DECLARE_READ8_MEMBER(tmpz84c011_0_pc_r);
|
||||
DECLARE_READ8_MEMBER(tmpz84c011_0_pd_r);
|
||||
DECLARE_READ8_MEMBER(tmpz84c011_0_pe_r);
|
||||
DECLARE_WRITE8_MEMBER(tmpz84c011_0_pa_w);
|
||||
DECLARE_WRITE8_MEMBER(tmpz84c011_0_pb_w);
|
||||
DECLARE_WRITE8_MEMBER(tmpz84c011_0_pc_w);
|
||||
DECLARE_WRITE8_MEMBER(tmpz84c011_0_pd_w);
|
||||
DECLARE_WRITE8_MEMBER(tmpz84c011_0_pe_w);
|
||||
DECLARE_READ8_MEMBER(tmpz84c011_0_dir_pa_r);
|
||||
DECLARE_READ8_MEMBER(tmpz84c011_0_dir_pb_r);
|
||||
DECLARE_READ8_MEMBER(tmpz84c011_0_dir_pc_r);
|
||||
DECLARE_READ8_MEMBER(tmpz84c011_0_dir_pd_r);
|
||||
DECLARE_READ8_MEMBER(tmpz84c011_0_dir_pe_r);
|
||||
DECLARE_WRITE8_MEMBER(tmpz84c011_0_dir_pa_w);
|
||||
DECLARE_WRITE8_MEMBER(tmpz84c011_0_dir_pb_w);
|
||||
DECLARE_WRITE8_MEMBER(tmpz84c011_0_dir_pc_w);
|
||||
DECLARE_WRITE8_MEMBER(tmpz84c011_0_dir_pd_w);
|
||||
DECLARE_WRITE8_MEMBER(tmpz84c011_0_dir_pe_w);
|
||||
|
||||
DECLARE_READ8_MEMBER(porta_default_r);
|
||||
DECLARE_READ8_MEMBER(portb_default_r);
|
||||
DECLARE_READ8_MEMBER(portc_default_r);
|
||||
DECLARE_READ8_MEMBER(portd_default_r);
|
||||
DECLARE_READ8_MEMBER(porte_default_r);
|
||||
|
||||
DECLARE_WRITE8_MEMBER(porta_default_w);
|
||||
DECLARE_WRITE8_MEMBER(portb_default_w);
|
||||
DECLARE_WRITE8_MEMBER(portc_default_w);
|
||||
DECLARE_WRITE8_MEMBER(portd_default_w);
|
||||
DECLARE_WRITE8_MEMBER(porte_default_w);
|
||||
DECLARE_READ8_MEMBER(tmpz84c011_pa_r);
|
||||
DECLARE_READ8_MEMBER(tmpz84c011_pb_r);
|
||||
DECLARE_READ8_MEMBER(tmpz84c011_pc_r);
|
||||
DECLARE_READ8_MEMBER(tmpz84c011_pd_r);
|
||||
DECLARE_READ8_MEMBER(tmpz84c011_pe_r);
|
||||
DECLARE_WRITE8_MEMBER(tmpz84c011_pa_w);
|
||||
DECLARE_WRITE8_MEMBER(tmpz84c011_pb_w);
|
||||
DECLARE_WRITE8_MEMBER(tmpz84c011_pc_w);
|
||||
DECLARE_WRITE8_MEMBER(tmpz84c011_pd_w);
|
||||
DECLARE_WRITE8_MEMBER(tmpz84c011_pe_w);
|
||||
DECLARE_READ8_MEMBER(tmpz84c011_dir_pa_r);
|
||||
DECLARE_READ8_MEMBER(tmpz84c011_dir_pb_r);
|
||||
DECLARE_READ8_MEMBER(tmpz84c011_dir_pc_r);
|
||||
DECLARE_READ8_MEMBER(tmpz84c011_dir_pd_r);
|
||||
DECLARE_READ8_MEMBER(tmpz84c011_dir_pe_r);
|
||||
DECLARE_WRITE8_MEMBER(tmpz84c011_dir_pa_w);
|
||||
DECLARE_WRITE8_MEMBER(tmpz84c011_dir_pb_w);
|
||||
DECLARE_WRITE8_MEMBER(tmpz84c011_dir_pc_w);
|
||||
DECLARE_WRITE8_MEMBER(tmpz84c011_dir_pd_w);
|
||||
DECLARE_WRITE8_MEMBER(tmpz84c011_dir_pe_w);
|
||||
|
||||
DECLARE_WRITE_LINE_MEMBER(intr_cb_trampoline_w);
|
||||
DECLARE_WRITE_LINE_MEMBER(zc0_cb_trampoline_w);
|
||||
@ -127,28 +121,26 @@ protected:
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
private:
|
||||
UINT8 m_pio_dir[5];
|
||||
UINT8 m_pio_latch[5];
|
||||
|
||||
private:
|
||||
devcb_write8 m_outports0;
|
||||
devcb_write8 m_outports1;
|
||||
devcb_write8 m_outports2;
|
||||
devcb_write8 m_outports3;
|
||||
devcb_write8 m_outports4;
|
||||
devcb_write8 m_outportsa;
|
||||
devcb_write8 m_outportsb;
|
||||
devcb_write8 m_outportsc;
|
||||
devcb_write8 m_outportsd;
|
||||
devcb_write8 m_outportse;
|
||||
|
||||
devcb_read8 m_inports0;
|
||||
devcb_read8 m_inports1;
|
||||
devcb_read8 m_inports2;
|
||||
devcb_read8 m_inports3;
|
||||
devcb_read8 m_inports4;
|
||||
devcb_read8 m_inportsa;
|
||||
devcb_read8 m_inportsb;
|
||||
devcb_read8 m_inportsc;
|
||||
devcb_read8 m_inportsd;
|
||||
devcb_read8 m_inportse;
|
||||
|
||||
devcb_write_line m_intr_cb; // interrupt callback
|
||||
devcb_write_line m_zc0_cb; // channel 0 zero crossing callbacks
|
||||
devcb_write_line m_zc1_cb; // channel 1 zero crossing callbacks
|
||||
devcb_write_line m_zc2_cb; // channel 2 zero crossing callbacks
|
||||
|
||||
};
|
||||
|
||||
extern const device_type TMPZ84C011;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user