mirror of
https://github.com/holub/mame
synced 2025-05-28 16:43:04 +03:00
tms57002: significantly improved build speed on lower-end h/w [R. Belmont]
No-whatsnew explanation: this takes OPTIMIZE=3 compile time for this core from over 1 hour down to about 2 minutes on PS3 Linux. (Yes, the tms57002 itself took over an hour to compile before - the thing has 256 MB of RAM and a very slow HDD so when it hits swap, swap hits back).
This commit is contained in:
R. Belmont
parent
8e97bca711
commit
bf505cd350
2
.gitattributes
vendored
2
.gitattributes
vendored
@ -488,6 +488,8 @@ src/emu/cpu/tms34010/tms34010.h svneol=native#text/plain
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src/emu/cpu/tms57002/57002dsm.c svneol=native#text/plain
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src/emu/cpu/tms57002/tms57002.c svneol=native#text/plain
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src/emu/cpu/tms57002/tms57002.h svneol=native#text/plain
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src/emu/cpu/tms57002/tms57kdec.c svneol=native#text/plain
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src/emu/cpu/tms57002/tms57kpr.h svneol=native#text/plain
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src/emu/cpu/tms57002/tmsinstr.lst svneol=native#text/plain
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src/emu/cpu/tms57002/tmsmake.c svneol=native#text/plain
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src/emu/cpu/tms7000/7000dasm.c svneol=native#text/plain
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@ -1631,13 +1631,19 @@ $(CPUOBJ)/tms32051/tms32051.o: $(CPUSRC)/tms32051/tms32051.c \
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ifneq ($(filter TMS57002,$(CPUS)),)
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OBJDIRS += $(CPUOBJ)/tms57002
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CPUOBJS += $(CPUOBJ)/tms57002/tms57002.o
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CPUOBJS += $(CPUOBJ)/tms57002/tms57002.o $(CPUOBJ)/tms57002/tms57kdec.o
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DASMOBJS += $(CPUOBJ)/tms57002/57002dsm.o
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TMSMAKE += $(BUILDOUT)/tmsmake$(BUILD_EXE)
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endif
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$(CPUOBJ)/tms57002/tms57002.o: $(CPUSRC)/tms57002/tms57002.c \
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$(CPUSRC)/tms57002/tms57002.h \
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$(CPUSRC)/tms57002/tms57kpr.h \
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$(CPUOBJ)/tms57002/tms57002.inc
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$(CPUOBJ)/tms57002/tms57kdec.o: $(CPUSRC)/tms57002/tms57kdec.c \
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$(CPUSRC)/tms57002/tms57002.h \
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$(CPUSRC)/tms57002/tms57kpr.h \
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$(CPUOBJ)/tms57002/tms57002.inc
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$(CPUOBJ)/tms57002/57002dsm.o: $(CPUSRC)/tms57002/57002dsm.c \
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@ -1,113 +1,7 @@
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#include "emu.h"
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#include "debugger.h"
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#include "tms57002.h"
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CPU_DISASSEMBLE(tms57002);
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#ifdef __GNUC__
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#define noinline __attribute__((noinline))
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#else
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#define noinline /* */
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#endif
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enum {
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IN_PLOAD = 0x00000001,
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IN_CLOAD = 0x00000002,
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SU_CVAL = 0x00000004,
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SU_MASK = 0x00000018, SU_ST0 = 0x00, SU_ST1 = 0x08, SU_PRG = 0x10,
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S_IDLE = 0x00000020,
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S_READ = 0x00000040,
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S_WRITE = 0x00000080,
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S_BRANCH = 0x00000100,
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S_HOST = 0x00000200
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};
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enum {
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ST0_INCS = 0x000001,
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ST0_DIRI = 0x000002,
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ST0_FI = 0x000004,
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ST0_SIM = 0x000008,
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ST0_PLRI = 0x000020,
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ST0_PBCI = 0x000040,
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ST0_DIRO = 0x000080,
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ST0_FO = 0x000100,
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ST0_SOM = 0x000600,
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ST0_PLRO = 0x000800,
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ST0_PBCO = 0x001000,
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ST0_CNS = 0x002000,
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ST0_WORD = 0x004000,
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ST0_SEL = 0x008000,
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ST0_M = 0x030000, ST0_M_64K = 0x000000, ST0_M_256K = 0x010000, ST0_M_1M = 0x020000,
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ST0_SRAM = 0x200000,
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ST1_AOV = 0x000001,
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ST1_SFAI = 0x000002,
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ST1_SFAO = 0x000004,
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ST1_MOVM = 0x000020,
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ST1_MOV = 0x000040,
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ST1_SFMA = 0x000180, ST1_SFMA_SHIFT = 7,
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ST1_SFMO = 0x001800, ST1_SFMO_SHIFT = 11,
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ST1_RND = 0x038000, ST1_RND_SHIFT = 15,
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ST1_CRM = 0x0C0000, ST1_CRM_SHIFT = 18, ST1_CRM_32 = 0x000000, ST1_CRM_16H = 0x040000, ST1_CRM_16L = 0x080000,
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ST1_DBP = 0x100000,
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ST1_CAS = 0x200000,
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ST1_CACHE = ST1_SFAI|ST1_SFAO|ST1_MOVM|ST1_SFMA|ST1_SFMO|ST1_RND|ST1_CRM|ST1_DBP
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};
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enum { BR_UB, BR_CB, BR_IDLE };
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enum { IBS = 8192, HBS = 4096 };
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typedef struct {
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unsigned short op;
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short next;
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unsigned char param;
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} icd;
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typedef struct {
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unsigned int st1;
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short ipc;
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short next;
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} hcd;
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typedef struct {
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short hashbase[256];
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hcd hashnode[HBS];
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icd inst[IBS];
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int hused, iused;
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} cd;
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typedef struct {
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int branch;
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short hnode;
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short ipc;
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} cstate;
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typedef struct {
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INT64 macc;
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UINT32 cmem[256];
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UINT32 dmem0[256];
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UINT32 dmem1[32];
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UINT32 si[4], so[4];
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UINT32 st0, st1, sti;
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UINT32 aacc, xoa, xba, xwr, xrd, creg;
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UINT8 pc, ca, id, ba0, ba1, rptc, rptc_next, sa;
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UINT32 xm_adr;
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UINT8 host[4], hidx, allow_update;
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cd cache;
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address_space *program, *data;
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int icount;
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int unsupported_inst_warning;
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} tms57002_t;
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#include "tms57kpr.h"
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INLINE tms57002_t *get_safe_token(device_t *device)
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{
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@ -1018,61 +912,6 @@ void tms57002_execute(tms57002_t *s)
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}
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#endif
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INLINE int xmode(UINT32 opcode, char type)
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{
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if(((opcode & 0x400) && (type == 'c')) || (!(opcode & 0x400) && (type == 'd'))) {
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if(opcode & 0x100)
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return 0;
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else if(opcode & 0x80)
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return 2;
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else
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return 1;
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} else if(opcode & 0x200)
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return 2;
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return 1;
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}
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INLINE int sfao(UINT32 st1)
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{
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return st1 & ST1_SFAO ? 1 : 0;
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}
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INLINE int dbp(UINT32 st1)
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{
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return st1 & ST1_DBP ? 1 : 0;
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}
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INLINE int crm(UINT32 st1)
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{
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return (st1 & ST1_CRM) >> ST1_CRM_SHIFT;
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}
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INLINE int sfai(UINT32 st1)
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{
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return st1 & ST1_SFAI ? 1 : 0;
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}
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INLINE int sfmo(UINT32 st1)
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{
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return (st1 & ST1_SFMO) >> ST1_SFMO_SHIFT;
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}
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INLINE int rnd(UINT32 st1)
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{
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return (st1 & ST1_RND) >> ST1_RND_SHIFT;
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}
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INLINE int movm(UINT32 st1)
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{
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return st1 & ST1_MOVM ? 1 : 0;
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}
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INLINE int sfma(UINT32 st1)
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{
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return (st1 & ST1_SFMA) >> ST1_SFMA_SHIFT;
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}
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static void tms57002_cache_flush(tms57002_t *s)
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{
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int i;
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@ -1091,86 +930,6 @@ static void tms57002_cache_flush(tms57002_t *s)
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}
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}
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static void tms57002_decode_error(tms57002_t *s, UINT32 opcode)
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{
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char buf[256];
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UINT8 opr[3];
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if(s->unsupported_inst_warning)
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return;
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s->unsupported_inst_warning = 1;
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opr[0] = opcode;
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opr[1] = opcode >> 8;
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opr[2] = opcode >> 16;
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CPU_DISASSEMBLE_NAME(tms57002)(0, buf, s->pc, opr, opr, 0);
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popmessage("tms57002: %s - Contact Mamedev", buf);
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}
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static void tms57002_decode_cat1(tms57002_t *s, UINT32 opcode, unsigned short *op, cstate *cs)
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{
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switch(opcode >> 18) {
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case 0x00: // nop
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break;
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#define CDEC1
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#include "cpu/tms57002/tms57002.inc"
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#undef CDEC1
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default:
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tms57002_decode_error(s, opcode);
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break;
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}
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}
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static void tms57002_decode_cat2_pre(tms57002_t *s, UINT32 opcode, unsigned short *op, cstate *cs)
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{
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switch((opcode >> 11) & 0x7f) {
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case 0x00: // nop
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break;
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#define CDEC2A
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#include "cpu/tms57002/tms57002.inc"
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#undef CDEC2A
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default:
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tms57002_decode_error(s, opcode);
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break;
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}
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}
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static void tms57002_decode_cat2_post(tms57002_t *s, UINT32 opcode, unsigned short *op, cstate *cs)
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{
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switch((opcode >> 11) & 0x7f) {
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case 0x00: // nop
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break;
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#define CDEC2B
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#include "cpu/tms57002/tms57002.inc"
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#undef CDEC2B
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default:
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tms57002_decode_error(s, opcode);
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break;
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}
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}
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static void tms57002_decode_cat3(tms57002_t *s, UINT32 opcode, unsigned short *op, cstate *cs)
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{
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switch((opcode >> 11) & 0x7f) {
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case 0x00: // nop
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break;
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#define CDEC3
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#include "cpu/tms57002/tms57002.inc"
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#undef CDEC3
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default:
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tms57002_decode_error(s, opcode);
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break;
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}
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}
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static void tms57002_add_one(tms57002_t *s, cstate *cs, unsigned short op, UINT8 param)
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{
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short ipc = s->cache.iused++;
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91
src/emu/cpu/tms57002/tms57kdec.c
Normal file
91
src/emu/cpu/tms57002/tms57kdec.c
Normal file
@ -0,0 +1,91 @@
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#include "emu.h"
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#include "debugger.h"
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#include "tms57002.h"
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#include "tms57kpr.h"
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#ifdef __GNUC__
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#define noinline __attribute__((noinline))
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#else
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#define noinline /* */
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#endif
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static void tms57002_decode_error(tms57002_t *s, UINT32 opcode)
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{
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char buf[256];
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UINT8 opr[3];
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if(s->unsupported_inst_warning)
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return;
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s->unsupported_inst_warning = 1;
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opr[0] = opcode;
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opr[1] = opcode >> 8;
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opr[2] = opcode >> 16;
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CPU_DISASSEMBLE_NAME(tms57002)(0, buf, s->pc, opr, opr, 0);
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popmessage("tms57002: %s - Contact Mamedev", buf);
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}
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void tms57002_decode_cat1(tms57002_t *s, UINT32 opcode, unsigned short *op, cstate *cs)
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{
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switch(opcode >> 18) {
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case 0x00: // nop
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break;
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#define CDEC1
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#include "cpu/tms57002/tms57002.inc"
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#undef CDEC1
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default:
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tms57002_decode_error(s, opcode);
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break;
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}
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}
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void tms57002_decode_cat2_pre(tms57002_t *s, UINT32 opcode, unsigned short *op, cstate *cs)
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{
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switch((opcode >> 11) & 0x7f) {
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case 0x00: // nop
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break;
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#define CDEC2A
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#include "cpu/tms57002/tms57002.inc"
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#undef CDEC2A
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default:
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tms57002_decode_error(s, opcode);
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break;
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}
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}
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void tms57002_decode_cat2_post(tms57002_t *s, UINT32 opcode, unsigned short *op, cstate *cs)
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{
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switch((opcode >> 11) & 0x7f) {
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case 0x00: // nop
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break;
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#define CDEC2B
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#include "cpu/tms57002/tms57002.inc"
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#undef CDEC2B
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default:
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tms57002_decode_error(s, opcode);
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break;
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}
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}
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void tms57002_decode_cat3(tms57002_t *s, UINT32 opcode, unsigned short *op, cstate *cs)
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{
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switch((opcode >> 11) & 0x7f) {
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case 0x00: // nop
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break;
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#define CDEC3
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#include "cpu/tms57002/tms57002.inc"
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#undef CDEC3
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default:
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tms57002_decode_error(s, opcode);
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break;
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}
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}
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171
src/emu/cpu/tms57002/tms57kpr.h
Normal file
171
src/emu/cpu/tms57002/tms57kpr.h
Normal file
@ -0,0 +1,171 @@
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#ifndef TMS57KPRIVATE_H
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#define TMS57KPRIVATE_H
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CPU_DISASSEMBLE(tms57002);
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#ifdef __GNUC__
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#define noinline __attribute__((noinline))
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#else
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#define noinline /* */
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#endif
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enum {
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IN_PLOAD = 0x00000001,
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IN_CLOAD = 0x00000002,
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SU_CVAL = 0x00000004,
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SU_MASK = 0x00000018, SU_ST0 = 0x00, SU_ST1 = 0x08, SU_PRG = 0x10,
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S_IDLE = 0x00000020,
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S_READ = 0x00000040,
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S_WRITE = 0x00000080,
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S_BRANCH = 0x00000100,
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S_HOST = 0x00000200
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};
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enum {
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ST0_INCS = 0x000001,
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ST0_DIRI = 0x000002,
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ST0_FI = 0x000004,
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ST0_SIM = 0x000008,
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ST0_PLRI = 0x000020,
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ST0_PBCI = 0x000040,
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ST0_DIRO = 0x000080,
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ST0_FO = 0x000100,
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ST0_SOM = 0x000600,
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ST0_PLRO = 0x000800,
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ST0_PBCO = 0x001000,
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ST0_CNS = 0x002000,
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ST0_WORD = 0x004000,
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ST0_SEL = 0x008000,
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ST0_M = 0x030000, ST0_M_64K = 0x000000, ST0_M_256K = 0x010000, ST0_M_1M = 0x020000,
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ST0_SRAM = 0x200000,
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ST1_AOV = 0x000001,
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ST1_SFAI = 0x000002,
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ST1_SFAO = 0x000004,
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ST1_MOVM = 0x000020,
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ST1_MOV = 0x000040,
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ST1_SFMA = 0x000180, ST1_SFMA_SHIFT = 7,
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ST1_SFMO = 0x001800, ST1_SFMO_SHIFT = 11,
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ST1_RND = 0x038000, ST1_RND_SHIFT = 15,
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ST1_CRM = 0x0C0000, ST1_CRM_SHIFT = 18, ST1_CRM_32 = 0x000000, ST1_CRM_16H = 0x040000, ST1_CRM_16L = 0x080000,
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ST1_DBP = 0x100000,
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ST1_CAS = 0x200000,
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ST1_CACHE = ST1_SFAI|ST1_SFAO|ST1_MOVM|ST1_SFMA|ST1_SFMO|ST1_RND|ST1_CRM|ST1_DBP
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};
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enum { BR_UB, BR_CB, BR_IDLE };
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enum { IBS = 8192, HBS = 4096 };
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typedef struct {
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unsigned short op;
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short next;
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unsigned char param;
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} icd;
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||||
|
||||
typedef struct {
|
||||
unsigned int st1;
|
||||
short ipc;
|
||||
short next;
|
||||
} hcd;
|
||||
|
||||
typedef struct {
|
||||
short hashbase[256];
|
||||
hcd hashnode[HBS];
|
||||
icd inst[IBS];
|
||||
int hused, iused;
|
||||
} cd;
|
||||
|
||||
typedef struct {
|
||||
int branch;
|
||||
short hnode;
|
||||
short ipc;
|
||||
} cstate;
|
||||
|
||||
typedef struct {
|
||||
INT64 macc;
|
||||
|
||||
UINT32 cmem[256];
|
||||
UINT32 dmem0[256];
|
||||
UINT32 dmem1[32];
|
||||
|
||||
UINT32 si[4], so[4];
|
||||
|
||||
UINT32 st0, st1, sti;
|
||||
UINT32 aacc, xoa, xba, xwr, xrd, creg;
|
||||
|
||||
UINT8 pc, ca, id, ba0, ba1, rptc, rptc_next, sa;
|
||||
|
||||
UINT32 xm_adr;
|
||||
|
||||
UINT8 host[4], hidx, allow_update;
|
||||
|
||||
cd cache;
|
||||
|
||||
address_space *program, *data;
|
||||
int icount;
|
||||
int unsupported_inst_warning;
|
||||
} tms57002_t;
|
||||
|
||||
void tms57002_decode_cat1(tms57002_t *s, UINT32 opcode, unsigned short *op, cstate *cs);
|
||||
void tms57002_decode_cat2_pre(tms57002_t *s, UINT32 opcode, unsigned short *op, cstate *cs);
|
||||
void tms57002_decode_cat3(tms57002_t *s, UINT32 opcode, unsigned short *op, cstate *cs);
|
||||
void tms57002_decode_cat2_post(tms57002_t *s, UINT32 opcode, unsigned short *op, cstate *cs);
|
||||
|
||||
INLINE int xmode(UINT32 opcode, char type)
|
||||
{
|
||||
if(((opcode & 0x400) && (type == 'c')) || (!(opcode & 0x400) && (type == 'd'))) {
|
||||
if(opcode & 0x100)
|
||||
return 0;
|
||||
else if(opcode & 0x80)
|
||||
return 2;
|
||||
else
|
||||
return 1;
|
||||
} else if(opcode & 0x200)
|
||||
return 2;
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
INLINE int sfao(UINT32 st1)
|
||||
{
|
||||
return st1 & ST1_SFAO ? 1 : 0;
|
||||
}
|
||||
|
||||
INLINE int dbp(UINT32 st1)
|
||||
{
|
||||
return st1 & ST1_DBP ? 1 : 0;
|
||||
}
|
||||
|
||||
INLINE int crm(UINT32 st1)
|
||||
{
|
||||
return (st1 & ST1_CRM) >> ST1_CRM_SHIFT;
|
||||
}
|
||||
|
||||
INLINE int sfai(UINT32 st1)
|
||||
{
|
||||
return st1 & ST1_SFAI ? 1 : 0;
|
||||
}
|
||||
|
||||
INLINE int sfmo(UINT32 st1)
|
||||
{
|
||||
return (st1 & ST1_SFMO) >> ST1_SFMO_SHIFT;
|
||||
}
|
||||
|
||||
INLINE int rnd(UINT32 st1)
|
||||
{
|
||||
return (st1 & ST1_RND) >> ST1_RND_SHIFT;
|
||||
}
|
||||
|
||||
INLINE int movm(UINT32 st1)
|
||||
{
|
||||
return st1 & ST1_MOVM ? 1 : 0;
|
||||
}
|
||||
|
||||
INLINE int sfma(UINT32 st1)
|
||||
{
|
||||
return (st1 & ST1_SFMA) >> ST1_SFMA_SHIFT;
|
||||
}
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user