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(MESS) Reimplemented the NCR5380 SCSI controller using nscsi. [R. Belmont]
This commit is contained in:
R. Belmont
parent
ee72cf5471
commit
bff5a6cfa9
2
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vendored
@ -7319,6 +7319,8 @@ src/mess/machine/nascom1.c svneol=native#text/plain
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src/mess/machine/nc.c svneol=native#text/plain
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src/mess/machine/ncr5380.c svneol=native#text/plain
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src/mess/machine/ncr5380.h svneol=native#text/plain
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src/mess/machine/ncr5380n.c svneol=native#text/plain
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src/mess/machine/ncr5380n.h svneol=native#text/plain
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src/mess/machine/ncr5390.c svneol=native#text/plain
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src/mess/machine/ncr5390.h svneol=native#text/plain
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src/mess/machine/ne1000.c svneol=native#text/plain
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601
src/mess/machine/ncr5380n.c
Normal file
601
src/mess/machine/ncr5380n.c
Normal file
@ -0,0 +1,601 @@
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/*********************************************************************
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ncr5380n.c
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Implementation of the NCR 5380, aka the Zilog Z5380
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TODO:
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- IRQs (Apple doesn't use 'em)
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- Target mode
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*********************************************************************/
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#include "emu.h"
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#include "ncr5380n.h"
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const device_type NCR5380N = &device_creator<ncr5380n_device>;
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DEVICE_ADDRESS_MAP_START(map, 8, ncr5380n_device)
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AM_RANGE(0x0, 0x0) AM_READWRITE(scsidata_r, outdata_w)
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AM_RANGE(0x1, 0x1) AM_READWRITE(icmd_r, icmd_w)
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AM_RANGE(0x2, 0x2) AM_READWRITE(mode_r, mode_w)
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AM_RANGE(0x3, 0x3) AM_READWRITE(command_r, command_w)
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AM_RANGE(0x4, 0x4) AM_READWRITE(status_r, selenable_w)
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AM_RANGE(0x5, 0x5) AM_READWRITE(busandstatus_r, startdmasend_w)
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AM_RANGE(0x6, 0x6) AM_READWRITE(indata_r, startdmatargetrx_w)
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AM_RANGE(0x7, 0x7) AM_READWRITE(resetparityirq_r, startdmainitrx_w)
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ADDRESS_MAP_END
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ncr5380n_device::ncr5380n_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
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: nscsi_device(mconfig, NCR5380N, "5380 SCSI (new)", tag, owner, clock)
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{
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}
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void ncr5380n_device::device_start()
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{
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save_item(NAME(m_tcommand));
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save_item(NAME(m_icommand));
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save_item(NAME(status));
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save_item(NAME(istatus));
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save_item(NAME(m_busstatus));
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save_item(NAME(tcount));
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save_item(NAME(mode));
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save_item(NAME(irq));
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save_item(NAME(drq));
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save_item(NAME(clock_conv));
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save_item(NAME(m_dmalatch));
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m_irq_func.resolve(m_irq_cb, *this);
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m_drq_func.resolve(m_drq_cb, *this);
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tcount = 0;
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status = 0;
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bus_id = 0;
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select_timeout = 0;
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tm = timer_alloc(0);
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}
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void ncr5380n_device::device_reset()
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{
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clock_conv = 2;
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sync_period = 5;
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sync_offset = 0;
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seq = 0;
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status = 0;
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m_tcommand = 0;
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m_icommand = 0;
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istatus = 0;
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m_busstatus = 0;
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irq = false;
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if(!m_irq_func.isnull())
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m_irq_func(irq);
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reset_soft();
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}
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void ncr5380n_device::device_config_complete()
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{
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// inherit a copy of the static data
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const ncr5380n_interface *intf = reinterpret_cast<const ncr5380n_interface *>(static_config());
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if (intf != NULL)
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{
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*static_cast<ncr5380n_interface *>(this) = *intf;
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}
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// or initialize to defaults if none provided
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else
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{
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memset(&m_irq_cb, 0, sizeof(m_irq_cb));
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memset(&m_drq_cb, 0, sizeof(m_drq_cb));
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}
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m_shortname = "ncr5380";
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}
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void ncr5380n_device::reset_soft()
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{
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state = IDLE;
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scsi_bus->ctrl_w(scsi_refid, 0, S_ALL); // clear any signals we're driving
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scsi_bus->ctrl_wait(scsi_refid, S_ALL, S_ALL);
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status = 0;
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drq = false;
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if(!m_drq_func.isnull())
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m_drq_func(drq);
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reset_disconnect();
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}
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void ncr5380n_device::reset_disconnect()
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{
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mode = MODE_D;
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}
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//static int last_phase = -1;
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void ncr5380n_device::scsi_ctrl_changed()
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{
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UINT32 ctrl = scsi_bus->ctrl_r();
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// printf("scsi_ctrl_changed: lines now %x\n", ctrl);
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/* if ((ctrl & (S_PHASE_MASK|S_SEL|S_BSY)) != last_phase)
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{
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printf("phase now %d, SEL %x BSY %x\n", ctrl & S_PHASE_MASK, ctrl & S_SEL, ctrl & S_BSY);
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last_phase = (S_PHASE_MASK|S_SEL|S_BSY);
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}*/
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// recalculate phase match
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m_busstatus &= ~BAS_PHASEMATCH;
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if ((ctrl & S_PHASE_MASK) == (m_tcommand & S_PHASE_MASK))
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{
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m_busstatus |= BAS_PHASEMATCH;
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}
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if (m_mode & MODE_DMA)
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{
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// if BSY drops or the phase goes mismatch, that terminates the DMA
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if ((!(ctrl & S_BSY)) || !(m_busstatus & BAS_PHASEMATCH))
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{
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// printf("BSY dropped or phase mismatch during DMA, ending DMA\n");
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m_mode &= ~MODE_DMA;
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m_busstatus |= BAS_ENDOFDMA;
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drq_clear();
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}
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}
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if(ctrl & S_RST) {
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logerror("%s: scsi bus reset\n", tag());
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return;
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}
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step(false);
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}
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void ncr5380n_device::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr)
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{
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step(true);
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}
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void ncr5380n_device::step(bool timeout)
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{
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UINT32 ctrl = scsi_bus->ctrl_r();
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UINT32 data = scsi_bus->data_r();
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if(0)
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printf("%s: state=%d.%d %s\n",
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tag(), state & STATE_MASK, (state & SUB_MASK) >> SUB_SHIFT,
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timeout ? "timeout" : "change");
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if(mode == MODE_I && !(ctrl & S_BSY)) {
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state = IDLE;
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reset_disconnect();
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check_irq();
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}
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switch(state & SUB_MASK ? state & SUB_MASK : state & STATE_MASK) {
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case IDLE:
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break;
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case ARB_COMPLETE << SUB_SHIFT: {
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if(!timeout)
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break;
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int win;
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for(win=7; win>=0 && !(data & (1<<win)); win--);
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// printf("data %02x win %02x scsi_id %02x\n", data, win, scsi_id);
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if(win != scsi_id) {
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scsi_bus->data_w(scsi_refid, 0);
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scsi_bus->ctrl_w(scsi_refid, 0, S_ALL);
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fatalerror("need to wait for bus free\n");
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break;
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}
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// arbitration no longer in progress
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m_icommand &= ~IC_ARBITRATION;
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state &= STATE_MASK;
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step(true);
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break;
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}
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case SEND_WAIT_SETTLE << SUB_SHIFT:
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if(!timeout)
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break;
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state = (state & STATE_MASK) | (SEND_WAIT_REQ_0 << SUB_SHIFT);
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step(false);
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break;
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case SEND_WAIT_REQ_0 << SUB_SHIFT:
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if(ctrl & S_REQ)
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break;
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state = state & STATE_MASK;
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scsi_bus->data_w(scsi_refid, 0);
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scsi_bus->ctrl_w(scsi_refid, 0, S_ACK);
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step(false);
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// byte's done, ask for another if the target hasn't said otherwise
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if (m_mode & MODE_DMA)
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{
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drq_set();
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}
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break;
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case RECV_WAIT_REQ_1 << SUB_SHIFT:
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if(!(ctrl & S_REQ))
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break;
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state = (state & STATE_MASK) | (RECV_WAIT_SETTLE << SUB_SHIFT);
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delay_cycles(sync_period);
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break;
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case RECV_WAIT_SETTLE << SUB_SHIFT:
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if(!timeout)
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break;
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m_dmalatch = scsi_bus->data_r();
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drq_set();
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scsi_bus->ctrl_w(scsi_refid, S_ACK, S_ACK);
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state = (state & STATE_MASK) | (RECV_WAIT_REQ_0 << SUB_SHIFT);
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step(false);
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break;
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case RECV_WAIT_REQ_0 << SUB_SHIFT:
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if(ctrl & S_REQ)
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break;
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state = state & STATE_MASK;
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step(false);
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break;
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default:
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printf("%s: step() unexpected state %d.%d\n",
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tag(),
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state & STATE_MASK, (state & SUB_MASK) >> SUB_SHIFT);
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exit(0);
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}
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}
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void ncr5380n_device::send_byte()
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{
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state = (state & STATE_MASK) | (SEND_WAIT_SETTLE << SUB_SHIFT);
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scsi_bus->data_w(scsi_refid, m_dmalatch);
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scsi_bus->ctrl_w(scsi_refid, S_ACK, S_ACK);
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scsi_bus->ctrl_wait(scsi_refid, S_REQ, S_REQ);
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delay_cycles(sync_period);
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}
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void ncr5380n_device::recv_byte()
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{
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state = (state & STATE_MASK) | (RECV_WAIT_REQ_1 << SUB_SHIFT);
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step(false);
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}
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void ncr5380n_device::function_bus_complete()
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{
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state = IDLE;
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// istatus |= I_FUNCTION|I_BUS;
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check_irq();
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}
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void ncr5380n_device::function_complete()
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{
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state = IDLE;
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// istatus |= I_FUNCTION;
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check_irq();
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}
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void ncr5380n_device::bus_complete()
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{
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state = IDLE;
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// istatus |= I_BUS;
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check_irq();
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}
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void ncr5380n_device::delay(int cycles)
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{
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if(!clock_conv)
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return;
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cycles *= clock_conv;
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tm->adjust(clocks_to_attotime(cycles));
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}
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void ncr5380n_device::delay_cycles(int cycles)
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{
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tm->adjust(clocks_to_attotime(cycles));
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}
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READ8_MEMBER(ncr5380n_device::scsidata_r)
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{
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return scsi_bus->data_r();
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}
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WRITE8_MEMBER(ncr5380n_device::outdata_w)
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{
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m_outdata = data;
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// are we driving the data bus?
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if (m_icommand & IC_DBUS)
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{
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scsi_bus->data_w(scsi_refid, data);
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}
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}
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READ8_MEMBER(ncr5380n_device::icmd_r)
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{
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return m_icommand;
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}
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WRITE8_MEMBER(ncr5380n_device::icmd_w)
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{
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// asserting to drive the data bus?
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if ((data & IC_DBUS) && !(m_icommand & IC_DBUS))
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{
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// printf("%s: driving data bus with %02x\n", tag(), m_outdata);
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scsi_bus->data_w(scsi_refid, m_outdata);
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delay(2);
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}
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// any control lines changing?
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UINT8 mask = (data & IC_PHASEMASK) ^ (m_icommand & IC_PHASEMASK);
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if (mask)
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{
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// translate data to nscsi
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UINT8 newdata = 0;
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newdata = (data & IC_RST ? S_RST : 0) |
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(data & IC_ACK ? S_ACK : 0) |
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(data & IC_BSY ? S_BSY : 0) |
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(data & IC_SEL ? S_SEL : 0) |
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(data & IC_ATN ? S_ATN : 0);
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// printf("%s: changing control lines %04x\n", tag(), newdata);
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scsi_bus->ctrl_w(scsi_refid, newdata, S_RST|S_ACK|S_BSY|S_SEL|S_ATN);
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}
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m_icommand = (data & IC_WRITEMASK);
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delay(2);
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}
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READ8_MEMBER(ncr5380n_device::mode_r)
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{
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return m_mode;
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}
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WRITE8_MEMBER(ncr5380n_device::mode_w)
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{
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// printf("%s: mode_w %02x (%08x)\n", tag(), data, space.device().safe_pc());
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// arbitration bit being set?
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if ((data & MODE_ARBITRATE) && !(m_mode & MODE_ARBITRATE))
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{
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// if SEL is selected and the assert SEL bit in the initiator
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// command register is clear, fail
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if ((scsi_bus->ctrl_r() & S_SEL) && !(m_icommand & IC_SEL))
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{
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// printf("arbitration lost, ctrl = %x, m_icommand&IC_SEL = %x\n", scsi_bus->ctrl_r(), m_icommand & IC_SEL);
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m_icommand &= ~IC_ARBITRATION;
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m_icommand |= IC_ARBLOST;
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}
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else
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{
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seq = 0;
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// state = DISC_SEL_ARBITRATION;
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arbitrate();
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}
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}
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m_mode = data;
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}
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READ8_MEMBER(ncr5380n_device::command_r)
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{
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// logerror("%s: command_r %02x (%08x)\n", tag(), m_tcommand, space.device().safe_pc());
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return m_tcommand;
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}
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WRITE8_MEMBER(ncr5380n_device::command_w)
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{
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// printf("%s: command_w %02x (%08x)\n", tag(), data, space.device().safe_pc());
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m_tcommand = data;
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// recalculate phase match
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m_busstatus &= ~BAS_PHASEMATCH;
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if ((scsi_bus->ctrl_r() & S_PHASE_MASK) == (m_tcommand & S_PHASE_MASK))
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{
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m_busstatus |= BAS_PHASEMATCH;
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}
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}
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void ncr5380n_device::arbitrate()
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{
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m_icommand &= ~IC_ARBLOST;
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m_icommand |= IC_ARBITRATION;
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state = (state & STATE_MASK) | (ARB_COMPLETE << SUB_SHIFT);
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scsi_bus->data_w(scsi_refid, m_outdata);
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scsi_bus->ctrl_w(scsi_refid, S_BSY, S_BSY);
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delay(11);
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}
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void ncr5380n_device::check_irq()
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{
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#if 0
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bool oldirq = irq;
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irq = istatus != 0;
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if(irq != oldirq && !m_irq_func.isnull())
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m_irq_func(irq);
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#endif
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}
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READ8_MEMBER(ncr5380n_device::status_r)
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{
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UINT32 ctrl = scsi_bus->ctrl_r();
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UINT8 res = status |
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(ctrl & S_RST ? ST_RST : 0) |
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(ctrl & S_BSY ? ST_BSY : 0) |
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(ctrl & S_REQ ? ST_REQ : 0) |
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(ctrl & S_MSG ? ST_MSG : 0) |
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(ctrl & S_CTL ? ST_CD : 0) |
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(ctrl & S_INP ? ST_IO : 0) |
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(ctrl & S_SEL ? ST_SEL : 0);
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// printf("%s: status_r %02x (%08x)\n", tag(), res, space.device().safe_pc());
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return res;
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}
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WRITE8_MEMBER(ncr5380n_device::selenable_w)
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{
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}
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READ8_MEMBER(ncr5380n_device::busandstatus_r)
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{
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UINT32 ctrl = scsi_bus->ctrl_r();
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UINT8 res = m_busstatus |
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(ctrl & S_ATN ? BAS_ATN : 0) |
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(ctrl & S_ACK ? BAS_ACK : 0);
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// printf("%s: busandstatus_r %02x (%08x)\n", tag(), res, space.device().safe_pc());
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return res;
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}
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|
||||
WRITE8_MEMBER(ncr5380n_device::startdmasend_w)
|
||||
{
|
||||
printf("%02x to start dma send\n", data);
|
||||
drq_set();
|
||||
}
|
||||
|
||||
READ8_MEMBER(ncr5380n_device::indata_r)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(ncr5380n_device::startdmatargetrx_w)
|
||||
{
|
||||
printf("%02x to start dma target Rx\n", data);
|
||||
}
|
||||
|
||||
READ8_MEMBER(ncr5380n_device::resetparityirq_r)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(ncr5380n_device::startdmainitrx_w)
|
||||
{
|
||||
// printf("%02x to start dma initiator Rx\n", data);
|
||||
recv_byte();
|
||||
}
|
||||
|
||||
void ncr5380n_device::dma_w(UINT8 val)
|
||||
{
|
||||
// drop DRQ until we're ready for another byte
|
||||
drq_clear();
|
||||
|
||||
if (m_mode & MODE_DMA)
|
||||
{
|
||||
m_dmalatch = val;
|
||||
send_byte();
|
||||
}
|
||||
}
|
||||
|
||||
UINT8 ncr5380n_device::dma_r()
|
||||
{
|
||||
// drop DRQ
|
||||
drq_clear();
|
||||
|
||||
// set up to receive our next byte if still in DMA mode
|
||||
scsi_bus->ctrl_w(scsi_refid, 0, S_ACK);
|
||||
if (m_mode & MODE_DMA)
|
||||
{
|
||||
recv_byte();
|
||||
}
|
||||
return m_dmalatch;
|
||||
}
|
||||
|
||||
void ncr5380n_device::drq_set()
|
||||
{
|
||||
if(!drq)
|
||||
{
|
||||
drq = true;
|
||||
m_busstatus |= BAS_DMAREQUEST;
|
||||
if(!m_drq_func.isnull())
|
||||
m_drq_func(drq);
|
||||
}
|
||||
}
|
||||
|
||||
void ncr5380n_device::drq_clear()
|
||||
{
|
||||
if(drq)
|
||||
{
|
||||
drq = false;
|
||||
m_busstatus &= ~BAS_DMAREQUEST;
|
||||
if(!m_drq_func.isnull())
|
||||
m_drq_func(drq);
|
||||
}
|
||||
}
|
||||
|
||||
READ8_MEMBER(ncr5380n_device::read)
|
||||
{
|
||||
switch (offset & 7)
|
||||
{
|
||||
case 0:
|
||||
return scsidata_r(space, offset);
|
||||
|
||||
case 1:
|
||||
return icmd_r(space, offset);
|
||||
|
||||
case 2:
|
||||
return mode_r(space, offset);
|
||||
|
||||
case 3:
|
||||
return command_r(space, offset);
|
||||
|
||||
case 4:
|
||||
return status_r(space, offset);
|
||||
|
||||
case 5:
|
||||
return busandstatus_r(space, offset);
|
||||
|
||||
case 6:
|
||||
return indata_r(space, offset);
|
||||
|
||||
case 7:
|
||||
return resetparityirq_r(space, offset);
|
||||
}
|
||||
|
||||
return 0xff;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(ncr5380n_device::write)
|
||||
{
|
||||
switch (offset & 7)
|
||||
{
|
||||
case 0:
|
||||
outdata_w(space, offset, data);
|
||||
break;
|
||||
|
||||
case 1:
|
||||
icmd_w(space, offset, data);
|
||||
break;
|
||||
|
||||
case 2:
|
||||
mode_w(space, offset, data);
|
||||
break;
|
||||
|
||||
case 3:
|
||||
command_w(space, offset, data);
|
||||
break;
|
||||
|
||||
case 4:
|
||||
selenable_w(space, offset, data);
|
||||
break;
|
||||
|
||||
case 5:
|
||||
startdmasend_w(space, offset, data);
|
||||
break;
|
||||
|
||||
case 6:
|
||||
startdmatargetrx_w(space, offset, data);
|
||||
break;
|
||||
|
||||
case 7:
|
||||
startdmainitrx_w(space, offset, data);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
223
src/mess/machine/ncr5380n.h
Normal file
223
src/mess/machine/ncr5380n.h
Normal file
@ -0,0 +1,223 @@
|
||||
/*********************************************************************
|
||||
|
||||
ncr5380n.c
|
||||
|
||||
Implementation of the NCR 5380
|
||||
|
||||
*********************************************************************/
|
||||
|
||||
#ifndef NCR5380_H
|
||||
#define NCR5380_H
|
||||
|
||||
#include "machine/nscsi_bus.h"
|
||||
|
||||
struct ncr5380n_interface
|
||||
{
|
||||
devcb_write_line m_irq_cb;
|
||||
devcb_write_line m_drq_cb;
|
||||
};
|
||||
|
||||
class ncr5380n_device : public nscsi_device,
|
||||
public ncr5380n_interface
|
||||
{
|
||||
public:
|
||||
ncr5380n_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
|
||||
|
||||
DECLARE_ADDRESS_MAP(map, 8);
|
||||
|
||||
DECLARE_READ8_MEMBER(scsidata_r);
|
||||
DECLARE_WRITE8_MEMBER(outdata_w);
|
||||
DECLARE_READ8_MEMBER(icmd_r);
|
||||
DECLARE_WRITE8_MEMBER(icmd_w);
|
||||
DECLARE_READ8_MEMBER(mode_r);
|
||||
DECLARE_WRITE8_MEMBER(mode_w);
|
||||
DECLARE_READ8_MEMBER(command_r);
|
||||
DECLARE_WRITE8_MEMBER(command_w);
|
||||
DECLARE_READ8_MEMBER(status_r);
|
||||
DECLARE_WRITE8_MEMBER(selenable_w);
|
||||
DECLARE_READ8_MEMBER(busandstatus_r);
|
||||
DECLARE_WRITE8_MEMBER(startdmasend_w);
|
||||
DECLARE_READ8_MEMBER(indata_r);
|
||||
DECLARE_WRITE8_MEMBER(startdmatargetrx_w);
|
||||
DECLARE_READ8_MEMBER(resetparityirq_r);
|
||||
DECLARE_WRITE8_MEMBER(startdmainitrx_w);
|
||||
|
||||
DECLARE_READ8_MEMBER(read);
|
||||
DECLARE_WRITE8_MEMBER(write);
|
||||
|
||||
virtual void scsi_ctrl_changed();
|
||||
|
||||
UINT8 dma_r();
|
||||
void dma_w(UINT8 val);
|
||||
|
||||
protected:
|
||||
virtual void device_start();
|
||||
virtual void device_reset();
|
||||
virtual void device_config_complete();
|
||||
virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
|
||||
|
||||
private:
|
||||
enum { MODE_D, MODE_T, MODE_I };
|
||||
enum { IDLE };
|
||||
|
||||
enum {
|
||||
// Bus initiated sequences
|
||||
BUSINIT_SETTLE_DELAY = 1,
|
||||
BUSINIT_ASSERT_BUS_SEL,
|
||||
BUSINIT_MSG_OUT,
|
||||
BUSINIT_RECV_BYTE,
|
||||
BUSINIT_ASSERT_BUS_RESEL,
|
||||
BUSINIT_WAIT_REQ,
|
||||
BUSINIT_RECV_BYTE_NACK,
|
||||
|
||||
// Bus SCSI Reset
|
||||
BUSRESET_WAIT_INT,
|
||||
BUSRESET_RESET_BOARD,
|
||||
|
||||
// Disconnected state commands
|
||||
DISC_SEL_ARBITRATION,
|
||||
DISC_SEL_ATN_WAIT_REQ,
|
||||
DISC_SEL_ATN_SEND_BYTE,
|
||||
DISC_SEL_WAIT_REQ,
|
||||
DISC_SEL_SEND_BYTE,
|
||||
DISC_REC_ARBITRATION,
|
||||
DISC_REC_MSG_IN,
|
||||
DISC_REC_SEND_BYTE,
|
||||
DISC_RESET,
|
||||
|
||||
// Command sequence
|
||||
CMDSEQ_CMD_PHASE,
|
||||
CMDSEQ_RECV_BYTE,
|
||||
|
||||
// Target commands
|
||||
TARGET_SEND_BYTE,
|
||||
TARGET_CMD_RECV_BYTE,
|
||||
TARGET_MSG_RECV_BYTE,
|
||||
TARGET_MSG_RECV_PAD,
|
||||
TARGET_DISC_SEND_BYTE,
|
||||
TARGET_DISC_MSG_IN,
|
||||
TARGET_DISC_SEND_BYTE_2,
|
||||
|
||||
// Initiator commands
|
||||
INIT_MSG_WAIT_REQ,
|
||||
INIT_XFR,
|
||||
INIT_XFR_SEND_BYTE,
|
||||
INIT_XFR_SEND_PAD_WAIT_REQ,
|
||||
INIT_XFR_SEND_PAD,
|
||||
INIT_XFR_RECV_PAD_WAIT_REQ,
|
||||
INIT_XFR_RECV_PAD,
|
||||
INIT_XFR_RECV_BYTE_ACK,
|
||||
INIT_XFR_RECV_BYTE_NACK,
|
||||
INIT_XFR_WAIT_REQ,
|
||||
INIT_CPT_RECV_BYTE_ACK,
|
||||
INIT_CPT_RECV_WAIT_REQ,
|
||||
INIT_CPT_RECV_BYTE_NACK,
|
||||
};
|
||||
|
||||
enum {
|
||||
// Arbitration
|
||||
ARB_WAIT_BUS_FREE = 1,
|
||||
ARB_COMPLETE,
|
||||
ARB_ASSERT_SEL,
|
||||
ARB_SET_DEST,
|
||||
ARB_RELEASE_BUSY,
|
||||
ARB_TIMEOUT_BUSY,
|
||||
ARB_TIMEOUT_ABORT,
|
||||
ARB_DESKEW_WAIT,
|
||||
|
||||
// Send/recieve byte
|
||||
SEND_WAIT_SETTLE,
|
||||
SEND_WAIT_REQ_0,
|
||||
RECV_WAIT_REQ_1,
|
||||
RECV_WAIT_SETTLE,
|
||||
RECV_WAIT_REQ_0,
|
||||
};
|
||||
|
||||
enum {
|
||||
STATE_MASK = 0x00ff,
|
||||
SUB_SHIFT = 8,
|
||||
SUB_MASK = 0xff00,
|
||||
};
|
||||
|
||||
enum { BUS_BUSY, BUS_FREE_WAIT, BUS_FREE };
|
||||
|
||||
enum {
|
||||
ST_RST = 0x80,
|
||||
ST_BSY = 0x40,
|
||||
ST_REQ = 0x20,
|
||||
ST_MSG = 0x10,
|
||||
ST_CD = 0x08,
|
||||
ST_IO = 0x04,
|
||||
ST_SEL = 0x02,
|
||||
ST_DBP = 0x01,
|
||||
|
||||
BAS_ENDOFDMA = 0x80,
|
||||
BAS_DMAREQUEST = 0x40,
|
||||
BAS_PARITYERROR = 0x20,
|
||||
BAS_IRQACTIVE = 0x10,
|
||||
BAS_PHASEMATCH = 0x08,
|
||||
BAS_BUSYERROR = 0x04,
|
||||
BAS_ATN = 0x02,
|
||||
BAS_ACK = 0x01,
|
||||
|
||||
IC_RST = 0x80,
|
||||
IC_ARBITRATION = 0x40,
|
||||
IC_ARBLOST = 0x20,
|
||||
IC_ACK = 0x10,
|
||||
IC_BSY = 0x08,
|
||||
IC_SEL = 0x04,
|
||||
IC_ATN = 0x02,
|
||||
IC_DBUS = 0x01,
|
||||
IC_PHASEMASK = 0x9e,
|
||||
IC_WRITEMASK = 0x9f,
|
||||
|
||||
MODE_BLOCKDMA = 0x80,
|
||||
MODE_TARGET = 0x40,
|
||||
MODE_PARITYCHK = 0x20,
|
||||
MODE_PARITYIRQ = 0x10,
|
||||
MODE_EOPIRQ = 0x08,
|
||||
MODE_BSYIRQ = 0x04,
|
||||
MODE_DMA = 0x02,
|
||||
MODE_ARBITRATE = 0x01,
|
||||
};
|
||||
|
||||
enum { DMA_NONE, DMA_IN, DMA_OUT };
|
||||
|
||||
emu_timer *tm;
|
||||
|
||||
UINT8 status, istatus, m_mode, m_outdata, m_busstatus, m_dmalatch;
|
||||
UINT8 m_icommand, m_tcommand;
|
||||
UINT8 clock_conv, sync_offset, sync_period, bus_id, select_timeout, seq;
|
||||
UINT16 tcount;
|
||||
int mode;
|
||||
int state, xfr_phase;
|
||||
|
||||
bool irq, drq;
|
||||
|
||||
devcb_resolved_write_line m_irq_func;
|
||||
devcb_resolved_write_line m_drq_func;
|
||||
|
||||
void drq_set();
|
||||
void drq_clear();
|
||||
|
||||
void step(bool timeout);
|
||||
void function_complete();
|
||||
void function_bus_complete();
|
||||
void bus_complete();
|
||||
|
||||
void arbitrate();
|
||||
void check_irq();
|
||||
|
||||
void reset_soft();
|
||||
void reset_disconnect();
|
||||
|
||||
void send_byte();
|
||||
void recv_byte();
|
||||
|
||||
void delay(int cycles);
|
||||
void delay_cycles(int cycles);
|
||||
};
|
||||
|
||||
extern const device_type NCR5380N;
|
||||
|
||||
#endif
|
||||
@ -529,6 +529,7 @@ $(MESSOBJ)/shared.a: \
|
||||
$(MESS_MACHINE)/msm6222b.o \
|
||||
$(MESS_MACHINE)/serial.o \
|
||||
$(MESS_MACHINE)/ncr5380.o \
|
||||
$(MESS_MACHINE)/ncr5380n.o \
|
||||
$(MESS_MACHINE)/ncr5390.o \
|
||||
$(MESS_MACHINE)/pc_kbdc.o \
|
||||
$(MESS_MACHINE)/pc_lpt.o \
|
||||
|
||||
Loading…
Reference in New Issue
Block a user