mirror of
https://github.com/holub/mame
synced 2025-04-16 05:24:54 +03:00
cpu/dps56156, plygonet.cpp: DSP56156 fixes and plygonet.cpp cleanup: (#9894) [Ryan Holtz]
* cpu/dsp56156: Fixed ANDI, fixed BFCLR errata, fixed DEC24 not affecting flags. * cpu/dsp56156: Added proper devcb_write16 for Port C output. * plygonet.cpp: Fixed banking and tightened up VRAM access. * plygonet.cpp: Account for endianness in tilemap accesses. * plygonet.cpp: Switched to logmacro, merged into one file, and general code cleanup.
This commit is contained in:
MooglyGuy
GitHub
parent
4fdaa5733a
commit
c046ba26c0
@ -2564,8 +2564,6 @@ files {
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MAME_DIR .. "src/mame/video/pingpong.cpp",
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MAME_DIR .. "src/mame/drivers/piratesh.cpp",
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MAME_DIR .. "src/mame/drivers/plygonet.cpp",
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MAME_DIR .. "src/mame/includes/plygonet.h",
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MAME_DIR .. "src/mame/video/plygonet.cpp",
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MAME_DIR .. "src/mame/drivers/pooyan.cpp",
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MAME_DIR .. "src/mame/includes/pooyan.h",
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MAME_DIR .. "src/mame/video/pooyan.cpp",
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@ -127,6 +127,7 @@ dsp56156_device::dsp56156_device(const machine_config &mconfig, const char *tag,
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, m_program_config("program", ENDIANNESS_LITTLE, 16, 16, -1, address_map_constructor(FUNC(dsp56156_device::dsp56156_program_map), this))
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, m_data_config("data", ENDIANNESS_LITTLE, 16, 16, -1, address_map_constructor(FUNC(dsp56156_device::dsp56156_x_data_map), this))
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, m_program_ram(*this, "dsk56156_program_ram")
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, portC_cb(*this)
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{
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}
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@ -268,6 +269,9 @@ void dsp56156_device::device_start()
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m_core.modC_state = false;
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m_core.reset_state = false;
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/* Resolve line callbacks */
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portC_cb.resolve_safe();
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/* save states - dsp56156_core members */
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save_item(NAME(m_core.modA_state));
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save_item(NAME(m_core.modB_state));
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@ -23,9 +23,10 @@
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#define DSP56156_IRQ_MODC 2
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#define DSP56156_IRQ_RESET 3 /* Is this needed? */
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namespace DSP_56156 {
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class dsp56156_device;
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/***************************************************************************
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STRUCTURES & TYPEDEFS
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***************************************************************************/
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@ -182,15 +183,14 @@ struct dsp56156_core
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uint8_t repFlag; // Knowing if we're in a 'repeat' state (dunno how the processor does this)
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uint32_t repAddr; // The address of the instruction to repeat...
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/* MAME internal stuff */
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// MAME internal stuff
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int icount;
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uint32_t ppc;
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uint32_t op;
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int interrupt_cycles;
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void (*output_pins_changed)(uint32_t pins);
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cpu_device *device;
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int interrupt_cycles;
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void (*output_pins_changed)(uint32_t pins);
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dsp56156_device *device;
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memory_access<16, 1, -1, ENDIANNESS_LITTLE>::cache cache;
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memory_access<16, 1, -1, ENDIANNESS_LITTLE>::specific program;
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memory_access<16, 1, -1, ENDIANNESS_LITTLE>::specific data;
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@ -211,10 +211,13 @@ public:
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void host_interface_write(uint8_t offset, uint8_t data);
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uint8_t host_interface_read(uint8_t offset);
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uint16_t get_peripheral_memory(uint16_t addr);
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void dsp56156_program_map(address_map &map);
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void dsp56156_x_data_map(address_map &map);
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auto portc_cb() { return portC_cb.bind(); }
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void output_portc(uint16_t value) { portC_cb(value); }
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protected:
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// device-level overrides
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virtual void device_start() override;
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@ -246,6 +249,8 @@ private:
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dsp56156_core m_core;
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devcb_write16 portC_cb;
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void agu_init();
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void alu_init();
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};
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@ -47,6 +47,7 @@ void mem_reset(dsp56156_core* cpustate)
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/************************************/
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void HCR_set(dsp56156_core* cpustate, uint16_t value)
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{
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cpustate->device->logerror("HCR_set: %02x\n", value);
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HF3_bit_set (cpustate, (value & 0x0010) >> 4);
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HF2_bit_set (cpustate, (value & 0x0008) >> 3);
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HCIE_bit_set(cpustate, (value & 0x0004) >> 2);
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@ -65,6 +66,7 @@ void HF3_bit_set(dsp56156_core* cpustate, uint16_t value)
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HCR &= ~(0x0010);
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HCR |= (value << 4);
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cpustate->device->logerror("HF3_bit_set: %d\n", value);
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HF3_bit_host_set(cpustate, value);
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}
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void HF2_bit_set(dsp56156_core* cpustate, uint16_t value)
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@ -73,6 +75,7 @@ void HF2_bit_set(dsp56156_core* cpustate, uint16_t value)
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HCR &= ~(0x0008);
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HCR |= (value << 3);
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cpustate->device->logerror("HF2_bit_set: %d\n", value);
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HF2_bit_host_set(cpustate, value);
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}
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void HCIE_bit_set(dsp56156_core* cpustate, uint16_t value)
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@ -468,12 +471,11 @@ void PCD_set(dsp56156_core* cpustate, uint16_t value)
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if (value & 0xf000)
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cpustate->device->logerror("Dsp56k : Attempting to set reserved bits in the PCD. Ignoring.\n");
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/* TODO: Temporary */
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cpustate->device->logerror("Dsp56k : Setting general output port C data to 0x%04x\n", value);
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value = value & 0x0fff;
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PCD &= ~(0x0fff);
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PCD |= (value << 0);
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cpustate->device->output_portc(PCD);
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}
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void dsp56156_io_reset(dsp56156_core* cpustate)
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@ -888,18 +890,22 @@ uint8_t dsp56156_device::host_interface_read(uint8_t offset)
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{
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// Interrupt Control Register (ICR)
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case 0x00:
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logerror("DSP: Returning ICR\n");
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return ICR;
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// Command Vector Register (CVR)
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case 0x01:
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logerror("DSP: Returning CVR\n");
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return CVR;
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// Interrupt status register (ISR)
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case 0x02:
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logerror("DSP: Returning ISR\n");
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return ISR;
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// Interrupt vector register (IVR)
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case 0x03:
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logerror("DSP: Returning IVR\n");
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return IVR;
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// Read zeroes
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@ -938,12 +944,5 @@ uint8_t dsp56156_device::host_interface_read(uint8_t offset)
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return 0xff;
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}
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/* MISC*/
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uint16_t dsp56156_device::get_peripheral_memory(uint16_t addr)
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{
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dsp56156_core* cpustate = &m_core;
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return cpustate->peripheral_ram[A2O(addr)];
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}
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} // namespace DSP_56156
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@ -21,7 +21,6 @@
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TODO:
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- 0x01ee: should this move sign extend? otherwise the test-against-minus means nothing.
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- Restore only the proper bits upon loop termination!
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- BFCLR has some errata in the docs that may need to be applied.
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*/
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/************************/
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@ -1818,6 +1817,7 @@ static size_t dsp56156_op_dec24(dsp56156_core* cpustate, const uint16_t op_byte,
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/* TODO: I wonder if workBits24 should be signed? */
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workBits24 = ((*((uint64_t*)D.addr)) & 0x000000ffffff0000U) >> 16;
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workBits24--;
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bool carry(workBits24 & 0x01000000);
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workBits24 &= 0x00ffffff; /* Solves -x issues */
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/* Set the D bits with the dec result */
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@ -1829,9 +1829,10 @@ static size_t dsp56156_op_dec24(dsp56156_core* cpustate, const uint16_t op_byte,
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/* S L E U N Z V C */
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/* * * * * * ? * * */
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/* TODO: S, L, E, U, V, C */
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/* TODO: S, L, E, U, V */
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if ( *((uint64_t*)D.addr) & 0x0000008000000000U) DSP56156_N_SET(); else DSP56156_N_CLEAR();
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if ((*((uint64_t*)D.addr) & 0x000000ffffff0000U) == 0) DSP56156_Z_SET(); else DSP56156_Z_CLEAR();
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if (carry) DSP56156_C_SET(); else DSP56156_C_CLEAR();
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cycles += 2; /* TODO: + mv oscillator clock cycles */
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return 1;
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@ -2185,12 +2186,12 @@ static size_t dsp56156_op_andi(dsp56156_core* cpustate, const uint16_t op, uint8
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SR &= ((immediate << 8) | 0x00ff);
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break;
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case 0x02: /* CCR */
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SR &= (immediate | 0xff00);
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case 0x02: /* OMR */
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OMR &= (uint8_t)(immediate);
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break;
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case 0x03: /* OMR */
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OMR &= (uint8_t)(immediate);
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case 0x03: /* CCR */
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SR &= (immediate | 0xff00);
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break;
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default:
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@ -2342,7 +2343,7 @@ static size_t dsp56156_op_bfop(dsp56156_core* cpustate, const uint16_t op, const
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case 0x12: /* BFCHG */
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if ((iVal & previousValue) == iVal) DSP56156_C_SET(); else DSP56156_C_CLEAR(); break;
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case 0x04: /* BFCLR */
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if ((iVal & previousValue) == iVal) DSP56156_C_SET(); else DSP56156_C_CLEAR(); break;
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if ((iVal & previousValue) == 0x0000) DSP56156_C_SET(); else DSP56156_C_CLEAR(); break;
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case 0x18: /* BFSET */
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if ((iVal & previousValue) == iVal) DSP56156_C_SET(); else DSP56156_C_CLEAR(); break;
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case 0x10: /* BFTSTH */
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@ -2408,7 +2409,7 @@ static size_t dsp56156_op_bfop_1(dsp56156_core* cpustate, const uint16_t op, con
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case 0x12: /* BFCHG */
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if ((iVal & previousValue) == iVal) DSP56156_C_SET(); else DSP56156_C_CLEAR(); break;
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case 0x04: /* BFCLR */
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if ((iVal & previousValue) == iVal) DSP56156_C_SET(); else DSP56156_C_CLEAR(); break;
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if ((iVal & previousValue) == 0x0000) DSP56156_C_SET(); else DSP56156_C_CLEAR(); break;
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case 0x18: /* BFSET */
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if ((iVal & previousValue) == iVal) DSP56156_C_SET(); else DSP56156_C_CLEAR(); break;
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case 0x10: /* BFTSTH */
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@ -2478,7 +2479,7 @@ static size_t dsp56156_op_bfop_2(dsp56156_core* cpustate, const uint16_t op, con
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case 0x12: /* BFCHG */
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if ((iVal & previousValue) == iVal) DSP56156_C_SET(); else DSP56156_C_CLEAR(); break;
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case 0x04: /* BFCLR */
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if ((iVal & previousValue) == iVal) DSP56156_C_SET(); else DSP56156_C_CLEAR(); break;
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if ((iVal & previousValue) == 0x0000) DSP56156_C_SET(); else DSP56156_C_CLEAR(); break;
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case 0x18: /* BFSET */
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if ((iVal & previousValue) == iVal) DSP56156_C_SET(); else DSP56156_C_CLEAR(); break;
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case 0x10: /* BFTSTH */
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@ -2855,7 +2856,8 @@ static size_t dsp56156_op_do_2(dsp56156_core* cpustate, const uint16_t op, const
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/* HACK */
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if (lValue >= 0xfff0)
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{
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cpustate->device->logerror("Dsp56156 : DO_2 operation changed %04x to 0000.\n", lValue);
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cpustate->device->logerror("Dsp56156 : DO_2 operation changed %04x to 0000, pc:%04x ppc:%04x.\n", lValue, cpustate->PCU.pc, cpustate->ppc);
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cpustate->device->machine().debug_break();
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lValue = 0x0000;
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}
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@ -2887,6 +2889,8 @@ static size_t dsp56156_op_do_2(dsp56156_core* cpustate, const uint16_t op, const
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/* Third instruction cycle */
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LF_bit_set(cpustate, 1);
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/* Undocumented, but it must be true to nest Dos in DoForevers */
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FV_bit_set(cpustate, 0);
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/* S L E U N Z V C */
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/* - * - - - - - - */
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File diff suppressed because it is too large
Load Diff
@ -1,124 +0,0 @@
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// license:BSD-3-Clause
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// copyright-holders:R. Belmont, Andrew Gardner
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#ifndef MAME_INCLUDES_PLYGONET_H
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#define MAME_INCLUDES_PLYGONET_H
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#pragma once
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#include "machine/eepromser.h"
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#include "machine/k054321.h"
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#include "video/k053936.h"
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#include "cpu/dsp56156/dsp56156.h"
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#include "emupal.h"
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#include "tilemap.h"
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static const uint16_t dsp56156_bank00_size = 0x1000;
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static const uint16_t dsp56156_bank01_size = 0x1000;
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static const uint16_t dsp56156_bank02_size = 0x4000;
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static const uint16_t dsp56156_shared_ram_16_size = 0x2000;
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static const uint16_t dsp56156_bank04_size = 0x1fc0;
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class polygonet_state : public driver_device
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{
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public:
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polygonet_state(const machine_config &mconfig, device_type type, const char *tag) :
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driver_device(mconfig, type, tag),
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m_maincpu(*this, "maincpu"),
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m_audiocpu(*this, "audiocpu"),
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m_dsp(*this, "dsp"),
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m_eeprom(*this, "eeprom"),
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m_k053936(*this, "k053936"),
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m_gfxdecode(*this, "gfxdecode"),
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m_palette(*this, "palette"),
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m_k054321(*this, "k054321"),
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m_shared_ram(*this, "shared_ram"),
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m_dsp56156_p_mirror(*this, "dsp56156_p_mirror"),
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m_dsp56156_p_8000(*this, "dsp56156_p_8000")
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{ }
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void plygonet(machine_config &config);
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void init_polygonet();
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private:
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required_device<cpu_device> m_maincpu;
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required_device<cpu_device> m_audiocpu;
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required_device<dsp56156_device> m_dsp;
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required_device<eeprom_serial_er5911_device> m_eeprom;
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required_device<k053936_device> m_k053936;
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required_device<gfxdecode_device> m_gfxdecode;
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required_device<palette_device> m_palette;
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required_device<k054321_device> m_k054321;
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/* 68k-side shared ram */
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required_shared_ptr<uint32_t> m_shared_ram;
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required_shared_ptr<uint16_t> m_dsp56156_p_mirror;
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required_shared_ptr<uint16_t> m_dsp56156_p_8000;
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ioport_port *m_inputs[4]{};
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uint8_t m_sys0 = 0;
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uint8_t m_sys1 = 0;
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/* TTL text plane stuff */
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int m_ttl_gfx_index = 0;
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tilemap_t *m_ttl_tilemap = nullptr;
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tilemap_t *m_roz_tilemap = nullptr;
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uint16_t m_ttl_vram[0x800];
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uint16_t m_roz_vram[0x800];
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/* sound */
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uint8_t m_sound_ctrl = 0;
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uint8_t m_sound_intck = 0;
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/* memory buffers */
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uint16_t m_dsp56156_bank00_ram[2 * 8 * dsp56156_bank00_size]; /* 2 bank sets, 8 potential banks each */
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uint16_t m_dsp56156_bank01_ram[2 * 8 * dsp56156_bank01_size];
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uint16_t m_dsp56156_bank02_ram[2 * 8 * dsp56156_bank02_size];
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uint16_t m_dsp56156_shared_ram_16[2 * 8 * dsp56156_shared_ram_16_size];
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uint16_t m_dsp56156_bank04_ram[2 * 8 * dsp56156_bank04_size];
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void polygonet_sys_w(offs_t offset, uint8_t data);
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uint8_t polygonet_inputs_r(offs_t offset);
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void sound_irq_w(uint32_t data);
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uint32_t dsp_host_interface_r(offs_t offset, uint32_t mem_mask = ~0);
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void shared_ram_write(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
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void dsp_w_lines(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
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void dsp_host_interface_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
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uint32_t network_r();
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uint16_t dsp56156_bootload_r();
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uint16_t dsp56156_ram_bank00_read(offs_t offset);
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void dsp56156_ram_bank00_write(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
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uint16_t dsp56156_ram_bank01_read(offs_t offset);
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void dsp56156_ram_bank01_write(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
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uint16_t dsp56156_ram_bank02_read(offs_t offset);
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void dsp56156_ram_bank02_write(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
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uint16_t dsp56156_shared_ram_read(offs_t offset);
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void dsp56156_shared_ram_write(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
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uint16_t dsp56156_ram_bank04_read(offs_t offset);
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void dsp56156_ram_bank04_write(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
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void sound_ctrl_w(uint8_t data);
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uint32_t polygonet_ttl_ram_r(offs_t offset);
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void polygonet_ttl_ram_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
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uint32_t polygonet_roz_ram_r(offs_t offset);
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void polygonet_roz_ram_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
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TILE_GET_INFO_MEMBER(ttl_get_tile_info);
|
||||
TILE_GET_INFO_MEMBER(roz_get_tile_info);
|
||||
TILEMAP_MAPPER_MEMBER(plygonet_scan);
|
||||
TILEMAP_MAPPER_MEMBER(plygonet_scan_cols);
|
||||
virtual void machine_reset() override;
|
||||
virtual void machine_start() override;
|
||||
virtual void video_start() override;
|
||||
uint32_t screen_update_polygonet(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
|
||||
INTERRUPT_GEN_MEMBER(polygonet_interrupt);
|
||||
DECLARE_WRITE_LINE_MEMBER(k054539_nmi_gen);
|
||||
|
||||
void dsp_data_map(address_map &map);
|
||||
void dsp_program_map(address_map &map);
|
||||
void main_map(address_map &map);
|
||||
void sound_map(address_map &map);
|
||||
};
|
||||
|
||||
#endif // MAME_INCLUDES_PLYGONET_H
|
||||
@ -1,131 +0,0 @@
|
||||
// license:BSD-3-Clause
|
||||
// copyright-holders:R. Belmont, Andrew Gardner
|
||||
/*
|
||||
Polygonet Commanders (Konami, 1993)
|
||||
|
||||
Video hardware emulation
|
||||
|
||||
Currently contains: TTL text plane (probably not complete, needs banking? colors?)
|
||||
Needs: PSAC2 roz plane, polygons
|
||||
*/
|
||||
|
||||
#include "emu.h"
|
||||
#include "includes/plygonet.h"
|
||||
#include "screen.h"
|
||||
|
||||
|
||||
/* TTL text plane */
|
||||
|
||||
TILE_GET_INFO_MEMBER(polygonet_state::ttl_get_tile_info)
|
||||
{
|
||||
int attr, code;
|
||||
|
||||
code = m_ttl_vram[tile_index]&0xfff;
|
||||
|
||||
attr = m_ttl_vram[tile_index]>>12; /* palette in all 4 bits? */
|
||||
|
||||
tileinfo.set(m_ttl_gfx_index, code, attr, 0);
|
||||
}
|
||||
|
||||
TILE_GET_INFO_MEMBER(polygonet_state::roz_get_tile_info)
|
||||
{
|
||||
int attr, code;
|
||||
|
||||
attr = (m_roz_vram[tile_index] >> 12) + 16; /* roz base palette is palette 16 */
|
||||
code = m_roz_vram[tile_index] & 0x3ff;
|
||||
|
||||
tileinfo.set(0, code, attr, 0);
|
||||
}
|
||||
|
||||
uint32_t polygonet_state::polygonet_ttl_ram_r(offs_t offset)
|
||||
{
|
||||
uint32_t *vram = (uint32_t *)m_ttl_vram;
|
||||
|
||||
return vram[offset];
|
||||
}
|
||||
|
||||
void polygonet_state::polygonet_ttl_ram_w(offs_t offset, uint32_t data, uint32_t mem_mask)
|
||||
{
|
||||
uint32_t *vram = (uint32_t *)m_ttl_vram;
|
||||
|
||||
COMBINE_DATA(&vram[offset]);
|
||||
|
||||
m_ttl_tilemap->mark_tile_dirty(offset*2);
|
||||
m_ttl_tilemap->mark_tile_dirty(offset*2+1);
|
||||
}
|
||||
|
||||
uint32_t polygonet_state::polygonet_roz_ram_r(offs_t offset)
|
||||
{
|
||||
uint32_t *vram = (uint32_t *)m_roz_vram;
|
||||
|
||||
return vram[offset];
|
||||
}
|
||||
|
||||
void polygonet_state::polygonet_roz_ram_w(offs_t offset, uint32_t data, uint32_t mem_mask)
|
||||
{
|
||||
uint32_t *vram = (uint32_t *)m_roz_vram;
|
||||
|
||||
COMBINE_DATA(&vram[offset]);
|
||||
|
||||
m_roz_tilemap->mark_tile_dirty(offset*2);
|
||||
m_roz_tilemap->mark_tile_dirty(offset*2+1);
|
||||
}
|
||||
|
||||
TILEMAP_MAPPER_MEMBER(polygonet_state::plygonet_scan)
|
||||
{
|
||||
return row * num_cols + (col^1);
|
||||
}
|
||||
|
||||
TILEMAP_MAPPER_MEMBER(polygonet_state::plygonet_scan_cols)
|
||||
{
|
||||
return col * num_rows + (row^1);
|
||||
}
|
||||
|
||||
void polygonet_state::video_start()
|
||||
{
|
||||
static const gfx_layout charlayout =
|
||||
{
|
||||
8, 8, /* 8x8 */
|
||||
4096, /* # of tiles */
|
||||
4, /* 4bpp */
|
||||
{ 0, 1, 2, 3 }, /* plane offsets */
|
||||
{ 0*4, 1*4, 2*4, 3*4, 4*4, 5*4, 6*4, 7*4 }, /* X offsets */
|
||||
{ 0*8*4, 1*8*4, 2*8*4, 3*8*4, 4*8*4, 5*8*4, 6*8*4, 7*8*4 }, /* Y offsets */
|
||||
8*8*4
|
||||
};
|
||||
|
||||
/* find first empty slot to decode gfx */
|
||||
for (m_ttl_gfx_index = 0; m_ttl_gfx_index < MAX_GFX_ELEMENTS; m_ttl_gfx_index++)
|
||||
if (m_gfxdecode->gfx(m_ttl_gfx_index) == nullptr)
|
||||
break;
|
||||
|
||||
assert(m_ttl_gfx_index != MAX_GFX_ELEMENTS);
|
||||
|
||||
/* decode the ttl layer's gfx */
|
||||
m_gfxdecode->set_gfx(m_ttl_gfx_index, std::make_unique<gfx_element>(m_palette, charlayout, memregion("gfx1")->base(), 0, m_palette->entries() / 16, 0));
|
||||
|
||||
/* create the tilemap */
|
||||
m_ttl_tilemap = &machine().tilemap().create(*m_gfxdecode, tilemap_get_info_delegate(*this, FUNC(polygonet_state::ttl_get_tile_info)), tilemap_mapper_delegate(*this, FUNC(polygonet_state::plygonet_scan)), 8, 8, 64, 32);
|
||||
|
||||
m_ttl_tilemap->set_transparent_pen(0);
|
||||
|
||||
/* set up the roz t-map too */
|
||||
m_roz_tilemap = &machine().tilemap().create(*m_gfxdecode, tilemap_get_info_delegate(*this, FUNC(polygonet_state::roz_get_tile_info)), tilemap_mapper_delegate(*this, FUNC(polygonet_state::plygonet_scan_cols)), 16, 16, 32, 64);
|
||||
m_roz_tilemap->set_transparent_pen(0);
|
||||
|
||||
/* save states */
|
||||
save_item(NAME(m_ttl_gfx_index));
|
||||
save_item(NAME(m_ttl_vram));
|
||||
save_item(NAME(m_roz_vram));
|
||||
}
|
||||
|
||||
uint32_t polygonet_state::screen_update_polygonet(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)
|
||||
{
|
||||
screen.priority().fill(0);
|
||||
bitmap.fill(m_palette->black_pen(), cliprect);
|
||||
|
||||
m_k053936->zoom_draw(screen, bitmap, cliprect, m_roz_tilemap, 0, 0, 0);
|
||||
|
||||
m_ttl_tilemap->draw(screen, bitmap, cliprect, 0, 1<<0);
|
||||
return 0;
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user