Sprinter/mame
2
0
Fork 0
mirror of https://github.com/holub/mame synced 2025-04-19 23:12:11 +03:00
Code Issues Actions 6 Packages Projects Releases Wiki Activity

netlist: Device refactoring

Browse Source 
* Move DIPs for 82S16, 82S115, and 2102A devices into nlm_proms
* Moved 7448 DIP to a macro. Replaced 7442 with truthtable and macro.
* Moved 74LS629 DIP into macro.
* Expand truthtable to handle 10 outputs.
This commit is contained in:
Aaron Giles 2020-08-01 18:25:04 +02:00 committed by couriersud
parent bcfc49f5b8
commit c0ecd68341
21 changed files with 275 additions and 476 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
scripts/src/netlist.lua
View File

@ -146,8 +146,6 @@ project "netlist"
MAME_DIR .. "src/lib/netlist/devices/nld_4066.h",
MAME_DIR .. "src/lib/netlist/devices/nld_4316.cpp",
MAME_DIR .. "src/lib/netlist/devices/nld_4316.h",
MAME_DIR .. "src/lib/netlist/devices/nld_7442.cpp",
MAME_DIR .. "src/lib/netlist/devices/nld_7442.h",
MAME_DIR .. "src/lib/netlist/devices/nld_7448.cpp",
MAME_DIR .. "src/lib/netlist/devices/nld_7448.h",
MAME_DIR .. "src/lib/netlist/devices/nld_7450.cpp",

1
src/lib/netlist/build/makefile
View File

@ -158,7 +158,6 @@ NLOBJS := \
$(NLOBJ)/devices/nld_4053.o \
$(NLOBJ)/devices/nld_4066.o \
$(NLOBJ)/devices/nld_4316.o \
$(NLOBJ)/devices/nld_7442.o \
$(NLOBJ)/devices/nld_7448.o \
$(NLOBJ)/devices/nld_7450.o \
$(NLOBJ)/devices/nld_7473.o \

7
src/lib/netlist/devices/net_lib.cpp
View File

@ -69,14 +69,10 @@ namespace devices
LIB_ENTRY(nicRSFF)
LIB_ENTRY(nicDelay)
LIB_ENTRY(2102A)
LIB_ENTRY(2102A_dip)
LIB_ENTRY(2716)
#if !(NL_USE_TRUTHTABLE_7448)
LIB_ENTRY(7448)
LIB_ENTRY(7448_dip)
#endif
LIB_ENTRY(7442)
LIB_ENTRY(7442_dip)
LIB_ENTRY(7450)
LIB_ENTRY(7450_dip)
LIB_ENTRY(7473)
@ -177,8 +173,6 @@ namespace devices
LIB_ENTRY(74193_dip)
LIB_ENTRY(74194_dip)
LIB_ENTRY(74365_dip)
LIB_ENTRY(82S16_dip)
LIB_ENTRY(82S115_dip)
LIB_ENTRY(9602)
LIB_ENTRY(9310_dip)
LIB_ENTRY(9314_dip)
@ -186,7 +180,6 @@ namespace devices
LIB_ENTRY(9322_dip)
LIB_ENTRY(9334_dip)
LIB_ENTRY(AM2847_dip)
LIB_ENTRY(SN74LS629_dip)
LIB_ENTRY(MM5837_dip)
}

33
src/lib/netlist/devices/nld_2102A.cpp
View File

@ -60,7 +60,6 @@ namespace netlist
}
}
friend class NETLIB_NAME(2102A_dip);
private:
object_array_t<logic_input_t, 10> m_A;
logic_input_t m_CEQ;
@ -74,39 +73,7 @@ namespace netlist
nld_power_pins m_power_pins;
};
NETLIB_OBJECT(2102A_dip)
{
NETLIB_CONSTRUCTOR(2102A_dip)
, A(*this, "A")
{
register_subalias("8", A.m_A[0]);
register_subalias("4", A.m_A[1]);
register_subalias("5", A.m_A[2]);
register_subalias("6", A.m_A[3]);
register_subalias("7", A.m_A[4]);
register_subalias("2", A.m_A[5]);
register_subalias("1", A.m_A[6]);
register_subalias("16", A.m_A[7]);
register_subalias("15", A.m_A[8]);
register_subalias("14", A.m_A[9]);
register_subalias("13", A.m_CEQ);
register_subalias("3", A.m_RWQ);
register_subalias("11", A.m_DI);
register_subalias("12", A.m_DO);
register_subalias("10", "A.VCC");
register_subalias("9", "A.GND");
}
//NETLIB_RESETI() {}
private:
NETLIB_SUB(2102A) A;
};
NETLIB_DEVICE_IMPL(2102A, "RAM_2102A", "+CEQ,+A0,+A1,+A2,+A3,+A4,+A5,+A6,+A7,+A8,+A9,+RWQ,+DI,@VCC,@GND")
NETLIB_DEVICE_IMPL(2102A_dip,"RAM_2102A_DIP","")
} //namespace devices
} // namespace netlist

23
src/lib/netlist/devices/nld_2102A.h
View File

@ -26,25 +26,8 @@
#include "netlist/nl_setup.h"
#define RAM_2102A(name, cCEQ, cA0, cA1, cA2, cA3, cA4, cA5, cA6, cA7, cA8, cA9, cRWQ, cDI) \
NET_REGISTER_DEV(RAM_2102A, name) \
NET_CONNECT(name, GND, GND) \
NET_CONNECT(name, VCC, VCC) \
NET_CONNECT(name, CEQ, cCEQ) \
NET_CONNECT(name, A0, cA0) \
NET_CONNECT(name, A1, cA1) \
NET_CONNECT(name, A2, cA2) \
NET_CONNECT(name, A3, cA3) \
NET_CONNECT(name, A4, cA4) \
NET_CONNECT(name, A5, cA5) \
NET_CONNECT(name, A6, cA6) \
NET_CONNECT(name, A7, cA7) \
NET_CONNECT(name, A8, cA8) \
NET_CONNECT(name, A9, cA9) \
NET_CONNECT(name, RWQ, cRWQ) \
NET_CONNECT(name, DI, cDI)
#define RAM_2102A_DIP(name) \
NET_REGISTER_DEV(RAM_2102A_DIP, name)
// expects: RAM_2102A(name, cCEQ, cA0, cA1, cA2, cA3, cA4, cA5, cA6, cA7, cA8, cA9, cRWQ, cDI)
#define RAM_2102A(...) \
NET_REGISTER_DEVEXT(RAM_2102A, __VA_ARGS__)
#endif /* NLD_2102A_H_ */

105
src/lib/netlist/devices/nld_7442.cpp
View File

@ -1,105 +0,0 @@
// license:GPL-2.0+
// copyright-holders:Ryan Holtz
/*
* nld_7442.cpp
*
*/
#include "nld_7442.h"
#include "netlist/nl_base.h"
namespace netlist
{
namespace devices
{
static constexpr const netlist_time delay = NLTIME_FROM_NS(30); // Worst-case through 3 levels of logic
// FIXME: stateless device, convert to TRUTHTABLE
NETLIB_OBJECT(7442)
{
NETLIB_CONSTRUCTOR(7442)
, m_A(*this, "A", NETLIB_DELEGATE(inputs))
, m_B(*this, "B", NETLIB_DELEGATE(inputs))
, m_C(*this, "C", NETLIB_DELEGATE(inputs))
, m_D(*this, "D", NETLIB_DELEGATE(inputs))
, m_val(*this, "m_val", 0)
, m_last_val(*this, "m_last_val", 0)
, m_Q(*this, {"Q0", "Q1", "Q2", "Q3", "Q4", "Q5", "Q6", "Q7", "Q8", "Q9"})
, m_power_pins(*this)
{
}
private:
NETLIB_RESETI()
{
m_val = 0;
m_last_val = 0;
}
NETLIB_HANDLERI(inputs)
{
const netlist_sig_t new_A = m_A();
const netlist_sig_t new_B = m_B();
const netlist_sig_t new_C = m_C();
const netlist_sig_t new_D = m_D();
m_last_val = m_val;
m_val = static_cast<uint8_t>((new_D << 3) | (new_C << 2) | (new_B << 1) | new_A);
if (m_last_val != m_val)
{
update_outputs();
}
}
void update_outputs() noexcept
{
for (std::size_t i=0; i<10; i++)
m_Q[i].push(i == m_val ? 0 : 1, delay);
}
logic_input_t m_A;
logic_input_t m_B;
logic_input_t m_C;
logic_input_t m_D;
state_var_u8 m_val;
state_var_u8 m_last_val;
object_array_t<logic_output_t, 10> m_Q;
nld_power_pins m_power_pins;
};
NETLIB_OBJECT(7442_dip)
{
NETLIB_CONSTRUCTOR(7442_dip)
, A(*this, "A")
{
register_subalias("1", "A.Q0");
register_subalias("2", "A.Q1");
register_subalias("3", "A.Q2");
register_subalias("4", "A.Q3");
register_subalias("5", "A.Q4");
register_subalias("6", "A.Q5");
register_subalias("7", "A.Q6");
register_subalias("8", "A.GND");
register_subalias("9", "A.Q7");
register_subalias("10", "A.Q8");
register_subalias("11", "A.Q9");
register_subalias("12", "A.D");
register_subalias("13", "A.C");
register_subalias("14", "A.B");
register_subalias("15", "A.A");
register_subalias("16", "A.VCC");
}
//NETLIB_RESETI() {}
private:
NETLIB_SUB(7442) A;
};
NETLIB_DEVICE_IMPL(7442, "TTL_7442", "+A,+B,+C,+D,@VCC,@GND")
NETLIB_DEVICE_IMPL(7442_dip, "TTL_7442_DIP", "")
} // namespace devices
} // namespace netlist

63
src/lib/netlist/devices/nld_7442.h
View File

@ -1,63 +0,0 @@
// license:GPL-2.0+
// copyright-holders:Ryan Holtz
/*
* nld_7442.h
*
* SN7442: 4-Line BCD to 10-Line Decimal Decoder
*
* +--------------+
* 0 |1 ++ 16| VCC
* 1 |2 15| A
* 2 |3 14| B
* 3 |4 13| C
* 4 |5 7442 12| D
* 5 |6 11| 9
* 6 |7 10| 8
* GND |8 9| 7
* +--------------+
*
* Truth Table
*
* +------++---+---+---+---++---+---+---+---+---+---+---+---+---+---+
* | Num. || D | C | B | A || 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 |
* +======++===+===+===+===++===+===+===+===+===+===+===+===+===+===+
* | 0 || 0 | 0 | 0 | 0 || 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
* | 1 || 0 | 0 | 0 | 1 || 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
* | 2 || 0 | 0 | 1 | 0 || 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
* | 3 || 0 | 0 | 1 | 1 || 1 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 |
* | 4 || 0 | 1 | 0 | 0 || 1 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 |
* | 5 || 0 | 1 | 0 | 1 || 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 1 |
* | 6 || 0 | 1 | 1 | 0 || 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 1 |
* | 7 || 0 | 1 | 1 | 1 || 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 |
* | 8 || 1 | 0 | 0 | 0 || 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 |
* | 9 || 1 | 0 | 0 | 1 || 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 |
* | - || 1 | 0 | 1 | 0 || 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
* | - || 1 | 0 | 1 | 1 || 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
* | - || 1 | 1 | 0 | 0 || 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
* | - || 1 | 1 | 0 | 1 || 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
* | - || 1 | 1 | 1 | 0 || 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
* | - || 1 | 1 | 1 | 1 || 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
* +------++---+---+---+---++---+---+---+---+---+---+---+---+---+---+
*
* Naming conventions follow Texas Instruments datasheet
*
*/
#ifndef NLD_7442_H_
#define NLD_7442_H_
#include "netlist/nl_setup.h"
#define TTL_7442(name, cA, cB, cC, cD) \
NET_REGISTER_DEV(TTL_7442, name) \
NET_CONNECT(name, GND, GND) \
NET_CONNECT(name, VCC, VCC) \
NET_CONNECT(name, A, cA) \
NET_CONNECT(name, B, cB) \
NET_CONNECT(name, C, cC) \
NET_CONNECT(name, D, cD)
#define TTL_7442_DIP(name) \
NET_REGISTER_DEV(TTL_7442_DIP, name)
#endif /* NLD_7442_H_ */

32
src/lib/netlist/devices/nld_7448.cpp
View File

@ -36,7 +36,6 @@ namespace netlist
m_state = 0;
}
friend class NETLIB_NAME(7448_dip);
private:
void update_outputs(unsigned v) noexcept
{
@ -98,36 +97,6 @@ namespace netlist
static const std::array<uint8_t, 16> tab7448;
};
NETLIB_OBJECT(7448_dip)
{
NETLIB_CONSTRUCTOR(7448_dip)
, A(*this, "A")
{
register_subalias("1", A.m_B);
register_subalias("2", A.m_C);
register_subalias("3", A.m_LTQ);
register_subalias("4", A.m_BIQ);
register_subalias("5", A.m_RBIQ);
register_subalias("6", A.m_D);
register_subalias("7", A.m_A);
register_subalias("8", "A.GND");
register_subalias("9", A.m_Q[4]); // e
register_subalias("10", A.m_Q[3]); // d
register_subalias("11", A.m_Q[2]); // c
register_subalias("12", A.m_Q[1]); // b
register_subalias("13", A.m_Q[0]); // a
register_subalias("14", A.m_Q[6]); // g
register_subalias("15", A.m_Q[5]); // f
register_subalias("16", "A.VCC");
}
private:
NETLIB_SUB(7448) A;
};
#endif
#if !(NL_USE_TRUTHTABLE_7448)
#define BITS7(b6,b5,b4,b3,b2,b1,b0) ((b6)<<6) | ((b5)<<5) | ((b4)<<4) | ((b3)<<3) | ((b2)<<2) | ((b1)<<1) | ((b0)<<0)
const std::array<uint8_t, 16> NETLIB_NAME(7448)::tab7448 =
@ -151,7 +120,6 @@ namespace netlist
};
NETLIB_DEVICE_IMPL(7448, "TTL_7448", "+A,+B,+C,+D,+LTQ,+BIQ,+RBIQ,@VCC,@GND")
NETLIB_DEVICE_IMPL(7448_dip, "TTL_7448_DIP", "")
#endif

16
src/lib/netlist/devices/nld_7448.h
View File

@ -28,20 +28,8 @@
#if !NL_AUTO_DEVICES
#if !(NL_USE_TRUTHTABLE_7448)
#define TTL_7448(name, cA0, cA1, cA2, cA3, cLTQ, cBIQ, cRBIQ) \
NET_REGISTER_DEV(TTL_7448, name) \
NET_CONNECT(name, VCC, VCC) \
NET_CONNECT(name, GND, GND) \
NET_CONNECT(name, A, cA0) \
NET_CONNECT(name, B, cA1) \
NET_CONNECT(name, C, cA2) \
NET_CONNECT(name, D, cA3) \
NET_CONNECT(name, LTQ, cLTQ) \
NET_CONNECT(name, BIQ, cBIQ) \
NET_CONNECT(name, RBIQ, cRBIQ)
#define TTL_7448_DIP(name) \
NET_REGISTER_DEV(TTL_7448_DIP, name)
#define TTL_7448(name) \
NET_REGISTER_DEV(TTL_7448, name) \
#endif
#endif

43
src/lib/netlist/devices/nld_74ls629.cpp
View File

@ -54,6 +54,7 @@ namespace netlist
, m_enableq(*this, "m_enableq", 1)
, m_out(*this, "m_out", 0)
, m_inc(*this, "m_inc", netlist_time::zero())
, m_power_pins(*this)
{
connect(m_FB, m_Y);
}
@ -72,6 +73,8 @@ namespace netlist
state_var<netlist_sig_t> m_enableq;
state_var<netlist_sig_t> m_out;
state_var<netlist_time> m_inc;
nld_power_pins m_power_pins;
private:
NETLIB_HANDLERI(fb)
{
@ -98,8 +101,9 @@ namespace netlist
, m_RNG(*this, "RNG", NETLIB_DELEGATE(inputs))
, m_FC(*this, "FC", NETLIB_DELEGATE(inputs))
, m_CAP(*this, "CAP", nlconst::magic(1e-6))
, m_power_pins(*this)
{
register_subalias("GND", m_R_FC.N());
connect(m_power_pins.GND(), m_R_FC.N());
connect(m_FC, m_R_FC.P());
connect(m_RNG, m_R_RNG.P());
@ -130,6 +134,7 @@ namespace netlist
analog_input_t m_FC;
param_fp_t m_CAP;
nld_power_pins m_power_pins;
private:
NETLIB_HANDLERI(inputs)
@ -194,43 +199,7 @@ namespace netlist
};
NETLIB_OBJECT(SN74LS629_dip)
{
NETLIB_CONSTRUCTOR(SN74LS629_dip)
, m_A(*this, "A")
, m_B(*this, "B")
{
register_subalias("1", m_B.m_FC);
register_subalias("2", m_A.m_FC);
register_subalias("3", m_A.m_RNG);
register_subalias("6", m_A.m_ENQ);
register_subalias("7", m_A.m_clock.m_Y);
register_subalias("8", m_A.m_R_FC.N());
register_subalias("9", m_A.m_R_FC.N());
connect(m_A.m_R_FC.N(), m_B.m_R_FC.N());
register_subalias("10", m_B.m_clock.m_Y);
register_subalias("11", m_B.m_ENQ);
register_subalias("14", m_B.m_RNG);
}
NETLIB_RESETI()
{
m_A.reset();
m_B.reset();
}
private:
NETLIB_SUB(SN74LS629) m_A;
NETLIB_SUB(SN74LS629) m_B;
};
NETLIB_DEVICE_IMPL(SN74LS629, "SN74LS629", "CAP")
NETLIB_DEVICE_IMPL(SN74LS629_dip, "SN74LS629_DIP", "1.CAP1,2.CAP2")
} //namespace devices
} // namespace netlist

3
src/lib/netlist/devices/nld_74ls629.h
View File

@ -33,7 +33,4 @@
#define SN74LS629(name, p_cap) \
NET_REGISTER_DEVEXT(SN74LS629, name, p_cap)
#define SN74LS629_DIP(name, p_cap1, p_cap2) \
NET_REGISTER_DEVEXT(SN74LS629_DIP, name, p_cap1, p_cap2)
#endif /* NLD_74LS629_H_ */

43
src/lib/netlist/devices/nld_82S115.cpp
View File

@ -31,7 +31,6 @@ namespace netlist
m_last_O = 0;
}
friend class NETLIB_NAME(82S115_dip);
private:
// FIXME: timing!
NETLIB_HANDLERI(inputs)
@ -73,49 +72,7 @@ namespace netlist
nld_power_pins m_power_pins;
};
NETLIB_OBJECT(82S115_dip)
{
NETLIB_CONSTRUCTOR(82S115_dip)
, A(*this, "A")
{
register_subalias("21", A.m_A[0]);
register_subalias("22", A.m_A[1]);
register_subalias("23", A.m_A[2]);
register_subalias("1", A.m_A[3]);
register_subalias("2", A.m_A[4]);
register_subalias("3", A.m_A[5]);
register_subalias("4", A.m_A[6]);
register_subalias("5", A.m_A[7]);
register_subalias("6", A.m_A[8]);
register_subalias("20", A.m_CE1Q);
register_subalias("19", A.m_CE2);
// FIXME: implement FE1, FE2
// register_subalias("13", m_FE1);
// register_subalias("11", m_FE2);
register_subalias("18", A.m_STROBE);
register_subalias("7", A.m_O[0]);
register_subalias("8", A.m_O[1]);
register_subalias("9", A.m_O[2]);
register_subalias("10", A.m_O[3]);
register_subalias("14", A.m_O[4]);
register_subalias("15", A.m_O[5]);
register_subalias("16", A.m_O[6]);
register_subalias("17", A.m_O[7]);
register_subalias("12", "A.GND");
register_subalias("24", "A.VCC");
}
//NETLIB_RESETI() {}
private:
NETLIB_SUB(82S115) A;
};
NETLIB_DEVICE_IMPL(82S115, "PROM_82S115", "+CE1Q,+CE2,+A0,+A1,+A2,+A3,+A4,+A5,+A6,+A7,+A8,+STROBE,@VCC,@GND")
NETLIB_DEVICE_IMPL(82S115_dip, "PROM_82S115_DIP", "")
} //namespace devices
} // namespace netlist

22
src/lib/netlist/devices/nld_82S115.h
View File

@ -30,24 +30,8 @@
#include "netlist/nl_setup.h"
#define PROM_82S115(name, cCE1Q, cCE2, cA0, cA1, cA2, cA3, cA4, cA5, cA6, cA7, cA8, cSTROBE) \
NET_REGISTER_DEV(PROM_82S115, name) \
NET_CONNECT(name, GND, GND) \
NET_CONNECT(name, VCC, VCC) \
NET_CONNECT(name, CE1Q, cCE1Q) \
NET_CONNECT(name, CE2, cCE2) \
NET_CONNECT(name, A0, cA0) \
NET_CONNECT(name, A1, cA1) \
NET_CONNECT(name, A2, cA2) \
NET_CONNECT(name, A3, cA3) \
NET_CONNECT(name, A4, cA4) \
NET_CONNECT(name, A5, cA5) \
NET_CONNECT(name, A6, cA6) \
NET_CONNECT(name, A7, cA7) \
NET_CONNECT(name, A8, cA8) \
NET_CONNECT(name, STROBE, cSTROBE)
#define PROM_82S115_DIP(name) \
NET_REGISTER_DEV(PROM_82S115_DIP, name)
// expects: PROM_82S115(name, cCE1Q, cCE2, cA0, cA1, cA2, cA3, cA4, cA5, cA6, cA7, cA8, cSTROBE)
#define PROM_82S115(...) \
NET_REGISTER_DEVEXT(PROM_82S115, __VA_ARGS__)
#endif /* NLD_82S115_H_ */

34
src/lib/netlist/devices/nld_82S16.cpp
View File

@ -38,7 +38,7 @@ namespace netlist
m_addr = 0;
m_enq = 0;
}
friend class NETLIB_NAME(82S16_dip);
private:
// FIXME: timing!
// FIXME: optimize device (separate address decoder!)
@ -105,39 +105,7 @@ namespace netlist
nld_power_pins m_power_pins;
};
NETLIB_OBJECT(82S16_dip)
{
NETLIB_CONSTRUCTOR(82S16_dip)
, A(*this, "A")
{
register_subalias("2", A.m_A[0]);
register_subalias("1", A.m_A[1]);
register_subalias("15", A.m_A[2]);
register_subalias("14", A.m_A[3]);
register_subalias("7", A.m_A[4]);
register_subalias("9", A.m_A[5]);
register_subalias("10", A.m_A[6]);
register_subalias("11", A.m_A[7]);
register_subalias("3", A.m_CE1Q);
register_subalias("4", A.m_CE2Q);
register_subalias("5", A.m_CE3Q);
register_subalias("12", A.m_WEQ);
register_subalias("13", A.m_DIN);
register_subalias("6", A.m_DOUTQ);
register_subalias("8", "A.GND");
register_subalias("16", "A.VCC");
}
//NETLIB_RESETI() {}
private:
NETLIB_SUB(82S16) A;
};
NETLIB_DEVICE_IMPL(82S16, "TTL_82S16", "")
NETLIB_DEVICE_IMPL(82S16_dip, "TTL_82S16_DIP", "")
} //namespace devices
} // namespace netlist

2
src/lib/netlist/devices/nld_82S16.h
View File

@ -28,7 +28,5 @@
#define TTL_82S16(name) \
NET_REGISTER_DEV(TTL_82S16, name)
#define TTL_82S16_DIP(name) \
NET_REGISTER_DEV(TTL_82S16_DIP, name)
#endif /* NLD_82S16_H_ */

70
src/lib/netlist/devices/nld_devinc.h
View File

@ -228,10 +228,6 @@
#define RAM_2102A(...) \
NET_REGISTER_DEVEXT(RAM_2102A, __VA_ARGS__)
// usage : RAM_2102A_DIP(name)
#define RAM_2102A_DIP(...) \
NET_REGISTER_DEVEXT(RAM_2102A_DIP, __VA_ARGS__)
// ---------------------------------------------------------------------
// Source: src/lib/netlist/devices/nld_roms.cpp
// ---------------------------------------------------------------------
@ -248,22 +244,6 @@
#define TTL_7448(...) \
NET_REGISTER_DEVEXT(TTL_7448, __VA_ARGS__)
// usage : TTL_7448_DIP(name)
#define TTL_7448_DIP(...) \
NET_REGISTER_DEVEXT(TTL_7448_DIP, __VA_ARGS__)
// ---------------------------------------------------------------------
// Source: src/lib/netlist/devices/nld_7442.cpp
// ---------------------------------------------------------------------
// usage : TTL_7442(name, pA, pB, pC, pD)
// auto connect: VCC, GND
#define TTL_7442(...) \
NET_REGISTER_DEVEXT(TTL_7442, __VA_ARGS__)
// usage : TTL_7442_DIP(name)
#define TTL_7442_DIP(...) \
NET_REGISTER_DEVEXT(TTL_7442_DIP, __VA_ARGS__)
// ---------------------------------------------------------------------
// Source: src/lib/netlist/devices/nld_7450.cpp
// ---------------------------------------------------------------------
@ -845,20 +825,6 @@
#define TTL_74365_DIP(...) \
NET_REGISTER_DEVEXT(TTL_74365_DIP, __VA_ARGS__)
// ---------------------------------------------------------------------
// Source: src/lib/netlist/devices/nld_82S16.cpp
// ---------------------------------------------------------------------
// usage : TTL_82S16_DIP(name)
#define TTL_82S16_DIP(...) \
NET_REGISTER_DEVEXT(TTL_82S16_DIP, __VA_ARGS__)
// ---------------------------------------------------------------------
// Source: src/lib/netlist/devices/nld_82S115.cpp
// ---------------------------------------------------------------------
// usage : PROM_82S115_DIP(name)
#define PROM_82S115_DIP(...) \
NET_REGISTER_DEVEXT(PROM_82S115_DIP, __VA_ARGS__)
// ---------------------------------------------------------------------
// Source: src/lib/netlist/devices/nld_74123.cpp
// ---------------------------------------------------------------------
@ -908,13 +874,6 @@
#define TTL_AM2847_DIP(...) \
NET_REGISTER_DEVEXT(TTL_AM2847_DIP, __VA_ARGS__)
// ---------------------------------------------------------------------
// Source: src/lib/netlist/devices/nld_74ls629.cpp
// ---------------------------------------------------------------------
// usage : SN74LS629_DIP(name, p1_CAP1, p2_CAP2)
#define SN74LS629_DIP(...) \
NET_REGISTER_DEVEXT(SN74LS629_DIP, __VA_ARGS__)
// ---------------------------------------------------------------------
// Source: src/lib/netlist/devices/nld_mm5837.cpp
// ---------------------------------------------------------------------
@ -1053,6 +1012,10 @@
#define TTL_7437_NAND(...) \
NET_REGISTER_DEVEXT(TTL_7437_NAND, __VA_ARGS__)
// usage : TTL_7448_DIP(name)
#define TTL_7448_DIP(...) \
NET_REGISTER_DEVEXT(TTL_7448_DIP, __VA_ARGS__)
// usage : TTL_7486_GATE(name)
#define TTL_7486_GATE(...) \
NET_REGISTER_DEVEXT(TTL_7486_GATE, __VA_ARGS__)
@ -1187,6 +1150,14 @@
#define TTL_7437_DIP(...) \
NET_REGISTER_DEVEXT(TTL_7437_DIP, __VA_ARGS__)
// usage : TTL_7442(name, cA, cB, cC, cD)
#define TTL_7442(...) \
NET_REGISTER_DEVEXT(TTL_7442, __VA_ARGS__)
// usage : TTL_7442_DIP(name)
#define TTL_7442_DIP(...) \
NET_REGISTER_DEVEXT(TTL_7442_DIP, __VA_ARGS__)
// usage : TTL_7486_DIP(name)
#define TTL_7486_DIP(...) \
NET_REGISTER_DEVEXT(TTL_7486_DIP, __VA_ARGS__)
@ -1243,6 +1214,10 @@
#define TTL_74379_DIP(...) \
NET_REGISTER_DEVEXT(TTL_74379_DIP, __VA_ARGS__)
// usage : SN74LS629_DIP(name, p1_CAP1, p2_CAP2)
#define SN74LS629_DIP(...) \
NET_REGISTER_DEVEXT(SN74LS629_DIP, __VA_ARGS__)
// usage : DM9312_DIP(name)
#define DM9312_DIP(...) \
NET_REGISTER_DEVEXT(DM9312_DIP, __VA_ARGS__)
@ -1429,5 +1404,18 @@
#define EPROM_2716_DIP(...) \
NET_REGISTER_DEVEXT(EPROM_2716_DIP, __VA_ARGS__)
// usage : TTL_82S16_DIP(name)
#define TTL_82S16_DIP(...) \
NET_REGISTER_DEVEXT(TTL_82S16_DIP, __VA_ARGS__)
// usage : PROM_82S115_DIP(name)
#define PROM_82S115_DIP(...) \
NET_REGISTER_DEVEXT(PROM_82S115_DIP, __VA_ARGS__)
// usage : RAM_2102A_DIP(name)
#define RAM_2102A_DIP(...) \
NET_REGISTER_DEVEXT(RAM_2102A_DIP, __VA_ARGS__)
#endif // __PLIB_PREPROCESSOR__
#endif

3
src/lib/netlist/devices/nlid_truthtable.cpp
View File

@ -677,7 +677,8 @@ namespace factory
#define ENTRY(n, s) ENTRYY(n, 1, s); ENTRYY(n, 2, s); ENTRYY(n, 3, s); \
ENTRYY(n, 4, s); ENTRYY(n, 5, s); ENTRYY(n, 6, s); \
ENTRYY(n, 7, s); ENTRYY(n, 8, s)
ENTRYY(n, 7, s); ENTRYY(n, 8, s); ENTRYY(n, 9, s); \
ENTRYY(n, 10, s);
host_arena::unique_ptr<truthtable_base_element_t> truthtable_create(tt_desc &desc, properties &&props)
{

1
src/lib/netlist/examples/sn74ls629_osc.c
View File

@ -25,6 +25,7 @@ NETLIST_START(ls629)
SN74LS629(OSC, 0.022e-6)
NET_C(GND, OSC.GND)
NET_C(V5, OSC.VCC)
NET_C(VR, OSC.RNG)
NET_C(VF, OSC.FC)
NET_C(GND, OSC.ENQ)

125
src/lib/netlist/macro/nlm_roms.cpp
View File

@ -185,6 +185,27 @@ static NETLIST_START(PROM_82S123_DIP)
ALIAS(16, A.VCC)
NETLIST_END()
/*
* nld_82S16.h
*
* DM82S16: 256 Bit bipolar ram
*
* +--------------+
* A1 |1 ++ 16| VCC
* A0 |2 15| A2
* CE1Q |3 14| A3
* CE2Q |4 82S16 13| DIN
* CE3Q |5 12| WEQ
* DOUTQ |6 11| A7
* A4 |7 10| A6
* GND |8 9| A5
* +--------------+
*
*
* Naming conventions follow Signetics datasheet
*/
//- Identifier: EPROM_2716_DIP
//- Title: 2716 16K (2K x 8) UV ERASABLE PROM
//- Description: The Intel®2716 is a 16,384-bit ultraviolet erasable and
@ -263,6 +284,107 @@ static NETLIST_START(EPROM_2716_DIP)
ALIAS(24, A.VCC)
NETLIST_END()
/* DM82S16: 256 Bit bipolar ram
*
* +--------------+
* A1 |1 ++ 16| VCC
* A0 |2 15| A2
* CE1Q |3 14| A3
* CE2Q |4 82S16 13| DIN
* CE3Q |5 12| WEQ
* DOUTQ |6 11| A7
* A4 |7 10| A6
* GND |8 9| A5
* +--------------+
*
* Naming conventions follow Signetics datasheet
*/
static NETLIST_START(TTL_82S16_DIP)
TTL_82S16(A)
DIPPINS( /* +--------------+ */
A.A1, /* A1 |1 ++ 16| VCC */ A.VCC,
A.A0, /* A0 |2 15| A2 */ A.A2,
A.CE1Q, /* CE1Q |3 14| A3 */ A.A3,
A.CE2Q, /* CE2Q |4 82S16 13| DIN */ A.DIN,
A.CE3Q, /* CE3Q |5 12| WEQ */ A.WEQ,
A.DOUTQ, /* DOUTQ |6 11| A7 */ A.A7,
A.A4, /* A4 |7 10| A6 */ A.A6,
A.GND, /* GND |8 9| A5 */ A.A5
/* +--------------+ */
)
NETLIST_END()
/* 82S115: 4K-bit TTL bipolar PROM (512 x 8)
*
* +--------------+
* A3 |1 ++ 24| VCC
* A4 |2 23| A2
* A5 |3 22| A1
* A6 |4 82S115 21| A0
* A7 |5 20| CE1Q
* A8 |6 19| CE2
* O1 |7 18| STROBE
* O2 |8 17| O8
* O3 |9 16| O7
* O4 |10 15| O6
* FE2 |11 14| O5
* GND |12 13| FE1
* +--------------+
*/
static NETLIST_START(PROM_82S115_DIP)
PROM_82S115(A)
NC_PIN(NC)
DIPPINS( /* +--------------+ */
A.A3, /* A3 |1 ++ 24| VCC */ A.VCC,
A.A4, /* A4 |2 23| A2 */ A.A2,
A.A5, /* A5 |3 22| A1 */ A.A1,
A.A6, /* A6 |4 82S115 21| A0 */ A.A0,
A.A7, /* A7 |5 20| CE1Q */ A.CE1Q,
A.A8, /* A8 |6 19| CE2 */ A.CE2,
A.O1, /* O1 |7 18| STROBE */ A.STROBE,
A.O2, /* O2 |8 17| O8 */ A.O8,
A.O3, /* O3 |9 16| O7 */ A.O7,
A.O4, /* O4 |10 15| O6 */ A.O6,
NC.I, /* FE2 |11 14| O5 */ A.O5,
A.GND, /* GND |12 13| FE1 */ NC.I
/* +--------------+ */
)
NETLIST_END()
/* 2102: 1024 x 1-bit Static RAM
*
* +--------------+
* A6 |1 ++ 16| A7
* A5 |2 15| A8
* RWQ |3 14| A9
* A1 |4 82S16 13| CEQ
* A2 |5 12| DO
* A3 |6 11| DI
* A4 |7 10| VCC
* A0 |8 9| GND
* +--------------+
*/
static NETLIST_START(RAM_2102A_DIP)
RAM_2102A(A)
DIPPINS( /* +--------------+ */
A.A6, /* A6 |1 ++ 16| A7 */ A.A7,
A.A5, /* A5 |2 15| A8 */ A.A8,
A.RWQ, /* RWQ |3 14| A9 */ A.A9,
A.A1, /* A1 |4 82S16 13| CEQ */ A.CEQ,
A.A2, /* A2 |5 12| DO */ A.DO,
A.A3, /* A3 |6 11| DI */ A.DI,
A.A4, /* A4 |7 10| VCC */ A.VCC,
A.A0, /* A0 |8 9| GND */ A.GND
/* +--------------+ */
)
NETLIST_END()
NETLIST_START(ROMS_lib)
@ -270,6 +392,9 @@ NETLIST_START(ROMS_lib)
LOCAL_LIB_ENTRY(PROM_82S126_DIP)
LOCAL_LIB_ENTRY(PROM_74S287_DIP)
LOCAL_LIB_ENTRY(EPROM_2716_DIP)
LOCAL_LIB_ENTRY(TTL_82S16_DIP)
LOCAL_LIB_ENTRY(PROM_82S115_DIP)
LOCAL_LIB_ENTRY(RAM_2102A_DIP)
NETLIST_END()

116
src/lib/netlist/macro/nlm_ttl74xx.cpp
View File

@ -1311,6 +1311,42 @@ static NETLIST_START(TTL_74379_DIP)
)
NETLIST_END()
/*
* SN74LS629: VOLTAGE-CONTROLLED OSCILLATORS
*
* +--------------+
* 2FC |1 ++ 16| VCC
* 1FC |2 15| QSC VCC
* 1RNG |3 14| 2RNG
* 1CX1 |4 74LS629 13| 2CX1
* 1CX2 |5 12| 2CX2
* 1ENQ |6 11| 2ENQ
* 1Y |7 10| 2Y
* OSC GND |8 9| GND
* +--------------+
*/
static NETLIST_START(SN74LS629_DIP)
SN74LS629(A, CAP_U(1))
SN74LS629(B, CAP_U(1))
NET_C(A.GND, B.GND)
NET_C(A.VCC, B.VCC)
NC_PIN(NC)
DIPPINS( /* +--------------+ */
B.FC, /* 2FC |1 ++ 16| VCC */ NC.I,
A.FC, /* 1FC |2 15| OSC VCC */ A.VCC,
A.RNG, /* 1RNG |3 14| 2RNG */ B.RNG,
NC.I, /* 1CX1 |4 74LS629 13| 2CX1 */ NC.I,
NC.I, /* 1CX2 |5 12| 2CX2 */ NC.I,
A.ENQ, /* 1ENQ |6 11| 2ENQ */ B.ENQ,
B.Y, /* 1Y |7 10| 2Y */ B.Y,
A.GND, /* OSC GND |8 9| GND */ NC.I
/* +--------------+ */
)
NETLIST_END()
/*
* DM9312: One of Eight Line Data Selectors/Multiplexers
*
@ -1359,7 +1395,36 @@ static NETLIST_START(DM9312_DIP)
)
NETLIST_END()
#if (NL_USE_TRUTHTABLE_7448)
/* SN7442: 4-Line BCD to 10-Line Decimal Decoder
*
* +--------------+
* 0 |1 ++ 16| VCC
* 1 |2 15| A
* 2 |3 14| B
* 3 |4 13| C
* 4 |5 7442 12| D
* 5 |6 11| 9
* 6 |7 10| 8
* GND |8 9| 7
* +--------------+
*/
static NETLIST_START(TTL_7442_DIP)
NET_REGISTER_DEV(TTL_7442, A)
DIPPINS( /* +--------------+ */
A.Q0, /* 0 |1 ++ 16| VCC */ A.VCC,
A.Q1, /* 1 |2 15| A */ A.A,
A.Q2, /* 2 |3 14| B */ A.B,
A.Q3, /* 3 |4 13| C */ A.C,
A.Q4, /* 4 |5 7442 12| D */ A.D,
A.Q5, /* 5 |6 11| 9 */ A.Q9,
A.Q6, /* 6 |7 10| 8 */ A.Q8,
A.GND, /* GND |8 9| 7 */ A.Q7
/* +--------------+ */
)
NETLIST_END()
/*
* DM7448: BCD to 7-Segment decoders/drivers
@ -1375,31 +1440,30 @@ NETLIST_END()
* GND |8 9| e
* +--------------+
*
*
* Naming conventions follow National Semiconductor datasheet
*
*/
#ifndef __PLIB_PREPROCESSOR__
#define TTL_7448_TT(name) \
NET_REGISTER_DEV(TTL_7448_TT, name)
#endif
static NETLIST_START(TTL_7448_DIP)
TTL_7448_TT(s)
#if (NL_USE_TRUTHTABLE_7448)
NET_REGISTER_DEV(TTL_7448_TT, A)
#else
NET_REGISTER_DEV(TTL_7448, A)
#endif
DIPPINS( /* +--------------+ */
s.B, /* B |1 ++ 16| VCC */ s.VCC,
s.C, /* C |2 15| f */ s.f,
s.LTQ, /* LTQ |3 14| g */ s.g,
s.BIQ, /* BIQ |4 7448 13| a */ s.a,
s.RBIQ, /* RBIQ |5 12| b */ s.b,
s.D, /* D |6 11| c */ s.c,
s.A, /* A |7 10| d */ s.d,
s.GND, /* GND |8 9| e */ s.e
A.B, /* B |1 ++ 16| VCC */ A.VCC,
A.C, /* C |2 15| f */ A.f,
A.LTQ, /* LTQ |3 14| g */ A.g,
A.BIQ, /* BIQ |4 7448 13| a */ A.a,
A.RBIQ, /* RBIQ |5 12| b */ A.b,
A.D, /* D |6 11| c */ A.c,
A.A, /* A |7 10| d */ A.d,
A.GND, /* GND |8 9| e */ A.e
/* +--------------+ */
)
NETLIST_END()
#endif
NETLIST_START(TTL74XX_lib)
NET_MODEL("DM7414 SCHMITT_TRIGGER(VTP=1.7 VTM=0.9 VI=4.35 RI=6.15k VOH=3.5 ROH=120 VOL=0.1 ROL=37.5 TPLH=15 TPHL=15)")
@ -1664,6 +1728,22 @@ NETLIST_START(TTL74XX_lib)
TT_FAMILY("74XX")
TRUTHTABLE_END()
TRUTHTABLE_START(TTL_7442, 4, 10, "")
TT_HEAD("D,C,B,A|0,1,2,3,4,5,6,7,8,9")
TT_LINE("0,0,0,0|0,1,1,1,1,1,1,1,1,1|30,30,30,30,30,30,30,30,30,30")
TT_LINE("0,0,0,1|1,0,1,1,1,1,1,1,1,1|30,30,30,30,30,30,30,30,30,30")
TT_LINE("0,0,1,0|1,1,0,1,1,1,1,1,1,1|30,30,30,30,30,30,30,30,30,30")
TT_LINE("0,0,1,1|1,1,1,0,1,1,1,1,1,1|30,30,30,30,30,30,30,30,30,30")
TT_LINE("0,1,0,0|1,1,1,1,0,1,1,1,1,1|30,30,30,30,30,30,30,30,30,30")
TT_LINE("0,1,0,1|1,1,1,1,1,0,1,1,1,1|30,30,30,30,30,30,30,30,30,30")
TT_LINE("0,1,1,0|1,1,1,1,1,1,0,1,1,1|30,30,30,30,30,30,30,30,30,30")
TT_LINE("0,1,1,1|1,1,1,1,1,1,1,0,1,1|30,30,30,30,30,30,30,30,30,30")
TT_LINE("1,0,0,0|1,1,1,1,1,1,1,1,0,1|30,30,30,30,30,30,30,30,30,30")
TT_LINE("1,0,0,1|1,1,1,1,1,1,1,1,1,0|30,30,30,30,30,30,30,30,30,30")
TT_LINE("1,0,1,X|1,1,1,1,1,1,1,1,1,1|30,30,30,30,30,30,30,30,30,30")
TT_LINE("1,1,X,X|1,1,1,1,1,1,1,1,1,1|30,30,30,30,30,30,30,30,30,30")
TRUTHTABLE_END()
#if (NL_USE_TRUTHTABLE_7448)
TRUTHTABLE_START(TTL_7448, 7, 7, "+A,+B,+C,+D,+LTQ,+BIQ,+RBIQ,@VCC,@GND")
TT_HEAD(" LTQ,BIQ,RBIQ, A , B , C , D | a, b, c, d, e, f, g")
@ -1941,9 +2021,8 @@ NETLIST_START(TTL74XX_lib)
LOCAL_LIB_ENTRY(TTL_7430_DIP)
LOCAL_LIB_ENTRY(TTL_7432_DIP)
LOCAL_LIB_ENTRY(TTL_7437_DIP)
#if (NL_USE_TRUTHTABLE_7448)
LOCAL_LIB_ENTRY(TTL_7442_DIP)
LOCAL_LIB_ENTRY(TTL_7448_DIP)
#endif
LOCAL_LIB_ENTRY(TTL_7486_DIP)
LOCAL_LIB_ENTRY(TTL_74121_DIP)
LOCAL_LIB_ENTRY(TTL_74123_DIP)
@ -1961,5 +2040,6 @@ NETLIST_START(TTL74XX_lib)
LOCAL_LIB_ENTRY(TTL_74377_DIP)
LOCAL_LIB_ENTRY(TTL_74378_DIP)
LOCAL_LIB_ENTRY(TTL_74379_DIP)
LOCAL_LIB_ENTRY(SN74LS629_DIP)
LOCAL_LIB_ENTRY(DM9312_DIP)
NETLIST_END()

7
src/lib/netlist/macro/nlm_ttl74xx.h
View File

@ -245,6 +245,10 @@
NET_REGISTER_DEV(TTL_7437_DIP, name)
#define TTL_7442_DIP(name) \
NET_REGISTER_DEV(TTL_7442_DIP, name)
#if (NL_USE_TRUTHTABLE_7448)
#define TTL_7448(name, cA0, cA1, cA2, cA3, cLTQ, cBIQ, cRBIQ) \
NET_REGISTER_DEV(TTL_7448, name) \
@ -257,12 +261,11 @@
NET_CONNECT(name, LTQ, cLTQ) \
NET_CONNECT(name, BIQ, cBIQ) \
NET_CONNECT(name, RBIQ, cRBIQ)
#endif
#define TTL_7448_DIP(name) \
NET_REGISTER_DEV(TTL_7448_DIP, name)
#endif
#define TTL_7486_GATE(name) \
NET_REGISTER_DEV(TTL_7486_GATE, name)