diff --git a/src/devices/machine/68340sim.cpp b/src/devices/machine/68340sim.cpp index 701369269f8..ddc7516b237 100644 --- a/src/devices/machine/68340sim.cpp +++ b/src/devices/machine/68340sim.cpp @@ -18,8 +18,9 @@ #define LOG_DATA (1U << 6) #define LOG_INT (1U << 7) #define LOG_PIT (1U << 8) +#define LOG_CS (1U << 9) -//#define VERBOSE (LOG_SETUP) +//#define VERBOSE (LOG_CS) #define LOG_OUTPUT_FUNC printf // Needs always to be enabled as the default value 'logerror' is not available here #include "logmacro.h" @@ -33,6 +34,7 @@ #define LOGDATA(...) LOGMASKED(LOG_DATA, __VA_ARGS__) #define LOGINT(...) LOGMASKED(LOG_INT, __VA_ARGS__) #define LOGPIT(...) LOGMASKED(LOG_PIT, __VA_ARGS__) +#define LOGCS(...) LOGMASKED(LOG_CS, __VA_ARGS__) #ifdef _MSC_VER #define FUNCNAME __func__ @@ -45,7 +47,7 @@ READ16_MEMBER( m68340_cpu_device::m68340_internal_sim_r ) LOGR("%s\n", FUNCNAME); assert(m68340SIM); m68340_sim &sim = *m68340SIM; - int val = space.machine().rand(); + int val = 0; int pc = space.device().safe_pc(); switch (offset * 2) @@ -86,14 +88,15 @@ READ16_MEMBER( m68340_cpu_device::m68340_internal_sim_r ) break; default: - LOGSIM("- %08x %s %04x, (%04x)\n", pc, FUNCNAME, offset * 2, mem_mask); + logerror("- %08x %s %04x, (%04x) (unsupported register)\n", pc, FUNCNAME, offset * 2, mem_mask); + LOGSIM("- %08x %s %04x, (%04x) (unsupported register)\n", pc, FUNCNAME, offset * 2, mem_mask); } LOGR(" * Reg %02x -> %02x - %s\n", offset * 2, val, ((offset * 2) >= 0x10 && (offset * 2) < 0x20) || (offset * 2) >= 0x60 ? "Error - should not happen" : std::array {{"MCR", "reserved", "SYNCR", "AVR/RSR", "SWIV/SYPCR", "PICR", "PITR", "SWSR"}}[(offset * 2) <= m68340_sim::REG_AVR_RSR ? offset : offset - 0x10 + 0x04]); - return 0x0000; + return val; } WRITE16_MEMBER( m68340_cpu_device::m68340_internal_sim_w ) @@ -376,14 +379,24 @@ WRITE32_MEMBER( m68340_cpu_device::m68340_internal_sim_cs_w ) { LOG("%s\n", FUNCNAME); offset += m68340_sim::REG_AM_CS0>>2; - LOGSETUP("- %08x %s %08x, %08x (%08x) - not implemented\n", pc, FUNCNAME, offset*4,data,mem_mask); + + if (offset & 1) + { + LOGCS("%08x Base address CS%d %08x, %08x (%08x) ", pc, (offset - 0x10) / 2, offset * 4, data, mem_mask); + LOGCS("- Base: %08x BFC:%02x WP:%d FTE:%d NCS:%d Valid: %s\n", data & 0xffffff00, (data & 0xf0) >> 4, data & 0x08 ? 1 : 0, data & 0x04 ? 1 : 0, data & 0x02 ? 1 : 0, data & 0x01 ? "Yes" : "No"); + } + else + { + LOGCS("%08x Address mask CS%d %08x, %08x (%08x) ", pc, (offset - 0x10) / 2, offset * 4, data, mem_mask); + LOGCS("- Mask: %08x FCM:%02x DD:%d PS: %s\n", data & 0xffffff00, (data & 0xf0) >> 4, (data >> 2) & 0x03, std::array{{"Reserved", "16-Bit", "8-bit", "External DSACK response"}}[data & 0x03]); + } assert(m68340SIM); m68340_sim &sim = *m68340SIM; int pc = space.device().safe_pc(); - switch (offset<<2) + switch (offset << 2) { case m68340_sim::REG_AM_CS0: COMBINE_DATA(&sim.m_am[0]);