mirror of
https://github.com/holub/mame
synced 2025-04-21 07:52:35 +03:00
hd6301x, hd6301y & derivatives: Updates to internal peripheral emulation
- Add Timer 2 and its associated interrupt and allow it to clock the serial port - Change divider for external serial clock to 16 - Remove timer hack in supremo
This commit is contained in:
AJR
parent
9e0e9fb978
commit
c137f89f86
@ -118,7 +118,7 @@ void epson_pf10_device::device_start()
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void epson_pf10_device::device_reset()
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{
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m_timer->adjust(attotime::zero, 0, attotime::from_hz(38400 * 8));
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m_timer->adjust(attotime::zero, 0, attotime::from_hz(38400 * 16));
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}
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//-------------------------------------------------
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@ -82,6 +82,7 @@ enum
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#define TAKE_OCI enter_interrupt("take OCI\n",0xfff4)
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#define TAKE_TOI enter_interrupt("take TOI\n",0xfff2)
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#define TAKE_SCI enter_interrupt("take SCI\n",0xfff0)
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#define TAKE_CMI enter_interrupt("take CMI\n",0xffec)
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/* mnemonics for the Timer Control and Status Register bits */
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#define TCSR_OLVL 0x01
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@ -276,9 +277,9 @@ void hd6301x_cpu_device::hd6301x_io(address_map &map)
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map(0x0018, 0x0018).rw(FUNC(hd6301x_cpu_device::p7_data_r), FUNC(hd6301x_cpu_device::p7_data_w)); // TODO: external except in single-chip mode
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map(0x0019, 0x0019).rw(FUNC(hd6301x_cpu_device::ocr2h_r), FUNC(hd6301x_cpu_device::ocr2h_w));
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map(0x001a, 0x001a).rw(FUNC(hd6301x_cpu_device::ocr2l_r), FUNC(hd6301x_cpu_device::ocr2l_w));
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//map(0x001b, 0x001b).rw(FUNC(hd6301x_cpu_device::tcsr3_r), FUNC(hd6301x_cpu_device::tcsr3_w));
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//map(0x001c, 0x001c).rw(FUNC(hd6301x_cpu_device::ff_r), FUNC(hd6301x_cpu_device::tconr_w));
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//map(0x001d, 0x001d).rw(FUNC(hd6301x_cpu_device::t2cnt_r), FUNC(hd6301x_cpu_device::t2cnt_w));
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map(0x001b, 0x001b).rw(FUNC(hd6301x_cpu_device::tcsr3_r), FUNC(hd6301x_cpu_device::tcsr3_w));
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map(0x001c, 0x001c).rw(FUNC(hd6301x_cpu_device::ff_r), FUNC(hd6301x_cpu_device::tconr_w));
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map(0x001d, 0x001d).rw(FUNC(hd6301x_cpu_device::t2cnt_r), FUNC(hd6301x_cpu_device::t2cnt_w));
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//map(0x001f, 0x001f).rw(FUNC(hd6301x_cpu_device::tstreg_r), FUNC(hd6301x_cpu_device::tstreg_w));
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}
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@ -318,6 +319,7 @@ m6801_cpu_device::m6801_cpu_device(const machine_config &mconfig, device_type ty
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, m_out_port_func(*this)
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, m_out_sc2_func(*this)
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, m_out_sertx_func(*this)
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, m_sclk_divider(8)
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{
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}
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@ -356,6 +358,7 @@ hd6301x_cpu_device::hd6301x_cpu_device(const machine_config &mconfig, device_typ
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, m_in_portx_func(*this)
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, m_out_portx_func(*this)
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{
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m_sclk_divider = 16;
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}
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hd6301x0_cpu_device::hd6301x0_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
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@ -433,6 +436,10 @@ void hd6301x_cpu_device::m6800_check_irq2()
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{
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TAKE_TOI;
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}
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else if ((m_tcsr3 & 0xc0) == 0xc0)
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{
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TAKE_CMI;
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}
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else if (((m_trcsr & (M6801_TRCSR_RIE|M6801_TRCSR_RDRF)) == (M6801_TRCSR_RIE|M6801_TRCSR_RDRF)) ||
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((m_trcsr & (M6801_TRCSR_RIE|M6801_TRCSR_ORFE)) == (M6801_TRCSR_RIE|M6801_TRCSR_ORFE)) ||
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((m_trcsr & (M6801_TRCSR_TIE|M6801_TRCSR_TDRE)) == (M6801_TRCSR_TIE|M6801_TRCSR_TDRE)))
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@ -572,7 +579,7 @@ void hd6301x_cpu_device::check_timer_event()
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modified_tcsr();
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}
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if (m_irq2 & (TCSR_OCF | TCSR_TOF))
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if ((m_irq2 & (TCSR_OCF | TCSR_TOF)) || (m_tcsr3 & 0xc0) == 0xc0)
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{
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if (m_wai_state & M6800_SLP)
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m_wai_state &= ~M6800_SLP;
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@ -591,6 +598,40 @@ void m6801_cpu_device::increment_counter(int amount)
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check_timer_event();
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}
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void hd6301x_cpu_device::increment_counter(int amount)
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{
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m6800_cpu_device::increment_counter(amount);
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if (m_t2cnt_written)
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m_t2cnt_written = false;
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else if (BIT(m_tcsr3, 4))
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{
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switch (m_tcsr3 & 0x03)
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{
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case 0x00:
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// Timer 2 input = E clock
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increment_t2cnt(amount);
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break;
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case 0x01:
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// Timer 2 input = E clock/8
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increment_t2cnt((amount + (CTD & 0x0007)) >> 3);
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break;
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case 0x02:
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// Timer 2 input = E clock/128
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increment_t2cnt((amount + (CTD & 0x007f)) >> 7);
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break;
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case 0x03:
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// Timer 2 input = external Tclk
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break;
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}
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}
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CTD += amount;
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if (CTD >= m_timer_next || (m_tcsr3 & 0xc0) == 0xc0)
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check_timer_event();
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}
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void m6801_cpu_device::EAT_CYCLES()
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{
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int cycles_to_eat = std::min(int(m_timer_next - CTD), m_icount);
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@ -648,6 +689,44 @@ void m6801_cpu_device::set_rmcr(uint8_t data)
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}
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}
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void hd6301x_cpu_device::set_rmcr(uint8_t data)
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{
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if (m_rmcr == data) return;
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m_rmcr = data;
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switch ((m_rmcr & 0x1c) >> 2)
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{
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case 0: // TODO: clock sync
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case 3:
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case 7: // external clock
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LOGSER("SCI: Using external serial clock: true\n");
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m_use_ext_serclock = true;
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m_sci_timer->enable(false);
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break;
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case 1:
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case 2:
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case 4: // TODO: clock sync
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case 5:
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case 6:
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if (BIT(m_rmcr, 5))
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{
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LOGSER("SCI: Using Timer 2 clock\n");
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m_sci_timer->enable(false);
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}
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else
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{
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int divisor = M6801_RMCR_SS[m_rmcr & M6801_RMCR_SS_MASK];
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attotime period = cycles_to_attotime(divisor);
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LOGSER("SCI: Setting serial rate, Divisor: %d Hz: %d\n", divisor, period.as_hz());
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m_sci_timer->adjust(period, 0, period);
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}
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m_use_ext_serclock = false;
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break;
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}
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}
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int m6801_cpu_device::m6800_rx()
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{
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return (m_in_port_func[1]() & M6801_PORT2_IO3) >> 3;
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@ -991,6 +1070,12 @@ void hd6301x_cpu_device::device_start()
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save_item(NAME(m_tcsr2));
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save_item(NAME(m_pending_tcsr2));
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save_item(NAME(m_output_compare2.d));
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save_item(NAME(m_t2cnt));
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save_item(NAME(m_tconr));
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save_item(NAME(m_tcsr3));
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save_item(NAME(m_tout3));
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save_item(NAME(m_t2cnt_written));
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}
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void m6801_cpu_device::device_reset()
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@ -1043,6 +1128,12 @@ void hd6301x_cpu_device::device_reset()
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m_tcsr2 = 0x00;
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m_pending_tcsr2 = 0x00;
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OC2D = 0xffff;
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m_t2cnt = 0x00;
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m_tconr = 0xff;
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m_tcsr3 = 0x00;
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m_tout3 = false;
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m_t2cnt_written = false;
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}
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@ -1086,6 +1177,11 @@ void hd6301x_cpu_device::write_port2()
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data = (data & 0xef) | (m_tx << 4);
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ddr |= 0x10;
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}
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if ((m_tcsr3 & 0x0c) != 0)
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{
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data = (data & 0xbf) | (m_tout3 << 6);
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ddr |= 0x40;
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}
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m_out_port_func[1](0, data, ddr);
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}
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@ -1540,6 +1636,93 @@ void hd6301x_cpu_device::ocr2l_w(uint8_t data)
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}
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void hd6301x_cpu_device::increment_t2cnt(int amount)
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{
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if (amount > uint8_t(m_tconr - m_t2cnt))
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{
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if (m_t2cnt > m_tconr)
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{
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amount -= 256 - m_t2cnt;
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m_t2cnt = 0;
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}
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m_t2cnt = (m_t2cnt + amount) % (m_tconr + 1);
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if (BIT(m_tcsr3, 3))
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{
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if (m_tout3 != BIT(m_tcsr3, 2))
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{
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m_tout3 = BIT(m_tcsr3, 2);
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m_port2_written = true;
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write_port2();
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}
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}
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else if (BIT(m_tcsr3, 2))
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{
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m_tout3 = !m_tout3;
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m_port2_written = true;
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write_port2();
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}
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if (BIT(m_rmcr, 5) && !m_use_ext_serclock)
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{
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if (m_ext_serclock + amount >= 32)
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{
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m_ext_serclock = (m_ext_serclock + amount) % 32;
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serial_transmit();
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serial_receive();
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}
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else
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m_ext_serclock += amount;
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}
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m_tcsr3 |= 0x80;
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m_timer_next = 0; // HACK
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}
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else
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m_t2cnt += amount;
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}
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uint8_t hd6301x_cpu_device::t2cnt_r()
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{
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return m_t2cnt;
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}
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void hd6301x_cpu_device::t2cnt_w(uint8_t data)
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{
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m_t2cnt = data;
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m_t2cnt_written = true;
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}
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void hd6301x_cpu_device::tconr_w(uint8_t data)
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{
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m_tconr = data;
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}
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uint8_t hd6301x_cpu_device::tcsr3_r()
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{
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return m_tcsr3;
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}
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void hd6301x_cpu_device::tcsr3_w(uint8_t data)
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{
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uint8_t tout3_last_enable = (m_tcsr3 & 0x0c) != 0;
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// Bit 5 does not exist and Bit 7 can only be written with 0
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m_tcsr3 = data & (0x5f | (m_tcsr3 & 0x80));
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if (m_tout3 && !BIT(data, 4))
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{
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m_tout3 = false;
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write_port2();
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}
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else if (tout3_last_enable ? (data & 0x0c) == 0 : (data & 0x0c) != 0)
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{
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m_port2_written = true;
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write_port2();
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}
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}
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uint8_t m6801_cpu_device::sci_rmcr_r()
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{
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return m_rmcr;
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@ -1655,7 +1838,7 @@ void m6801_cpu_device::m6801_clock_serial()
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{
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m_ext_serclock++;
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if (m_ext_serclock >= 8)
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if (m_ext_serclock >= m_sclk_divider)
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{
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m_ext_serclock = 0;
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serial_transmit();
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@ -124,6 +124,8 @@ protected:
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devcb_write_line m_out_sc2_func;
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devcb_write_line m_out_sertx_func;
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int m_sclk_divider;
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/* internal registers */
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uint8_t m_port_ddr[4];
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uint8_t m_port_data[4];
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@ -167,7 +169,7 @@ protected:
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virtual void set_timer_event();
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virtual void modified_counters();
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virtual void check_timer_event();
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void set_rmcr(uint8_t data);
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virtual void set_rmcr(uint8_t data);
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virtual void write_port2();
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int m6800_rx();
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void serial_transmit();
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@ -281,12 +283,21 @@ protected:
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uint8_t ocr2l_r();
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void ocr2l_w(uint8_t data);
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void increment_t2cnt(int amount);
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uint8_t t2cnt_r();
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void t2cnt_w(uint8_t data);
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void tconr_w(uint8_t data);
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uint8_t tcsr3_r();
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void tcsr3_w(uint8_t data);
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virtual void m6800_check_irq2() override;
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virtual void modified_tcsr() override;
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virtual void set_timer_event() override;
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virtual void modified_counters() override;
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virtual void increment_counter(int amount) override;
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virtual void check_timer_event() override;
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virtual void CLEANUP_COUNTERS() override;
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virtual void set_rmcr(uint8_t data) override;
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devcb_read8::array<2> m_in_portx_func;
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devcb_write8::array<3> m_out_portx_func;
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@ -297,6 +308,12 @@ protected:
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uint8_t m_tcsr2;
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uint8_t m_pending_tcsr2;
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PAIR m_output_compare2;
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uint8_t m_t2cnt;
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uint8_t m_tconr;
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uint8_t m_tcsr3;
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bool m_tout3;
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bool m_t2cnt_written;
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};
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@ -7,7 +7,6 @@ Novag Super Nova & related chess computers. I believe the series started with
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Primo. The chess engine is by David Kittinger.
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TODO:
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- remove timer hack for supremo (missing extra timer emulation in MCU core)
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- NMI on power-off switch, it sets 0x14 bit 7 for standby power (see below)
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- add nvram, MCU is missing standby power emulation
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- beeps are glitchy, as if interrupted for too long
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@ -324,10 +323,6 @@ void snova_state::supremo(machine_config &config)
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m_maincpu->set_clock(8_MHz_XTAL);
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m_maincpu->set_addrmap(AS_PROGRAM, &snova_state::supremo_map);
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// THIS IS A HACK, vector @ 0xffec, use ROM_COPY
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const attotime irq_period = attotime::from_ticks(4 * 128 * 11, 8_MHz_XTAL);
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m_maincpu->set_periodic_int(FUNC(snova_state::irq0_line_hold), irq_period);
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config.set_default_layout(layout_novag_supremo);
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config.device_remove("rs232");
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@ -351,8 +346,6 @@ ROM_START( supremo )
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ROM_REGION( 0x10000, "maincpu", 0 )
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ROM_LOAD("sp_a10.u5", 0x8000, 0x8000, CRC(1db63786) SHA1(4f24452ed8955b31ba88f68cc95c357660930aa4) )
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ROM_COPY("maincpu", 0xffec, 0xfff8, 2) // HACK
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ROM_REGION( 50926, "screen", 0 )
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ROM_LOAD("nsnova.svg", 0, 50926, CRC(5ffa1b53) SHA1(8b1f862bfdf0be837a4e8dc94fea592d6ffff629) )
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ROM_END
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@ -41,7 +41,7 @@ private:
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u8 p2_r();
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WRITE_LINE_MEMBER(midi_rx_r) { m_rx_data = state; }
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WRITE_LINE_MEMBER(midiclock_w) { if (state == ASSERT_LINE) m_maincpu->m6801_clock_serial();}
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WRITE_LINE_MEMBER(midiclock_w) { if (state) m_maincpu->m6801_clock_serial(); }
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required_device<hd6303x_cpu_device> m_maincpu;
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required_ioport m_port2;
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@ -130,7 +130,7 @@ void ymtx81z_state::tx81z(machine_config &config)
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NVRAM(config, "nvram", nvram_device::DEFAULT_ALL_0); // TC5564PL-15/-20 + CR2032 battery
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auto &midiclock(CLOCK(config, "midiclock", 500_kHz_XTAL / 2)); // divider not verified
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auto &midiclock(CLOCK(config, "midiclock", 500_kHz_XTAL));
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midiclock.signal_handler().set(FUNC(ymtx81z_state::midiclock_w));
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MIDI_PORT(config, "mdin", midiin_slot, "midiin").rxd_handler().set(FUNC(ymtx81z_state::midi_rx_r));
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