Sprinter/mame
2
0
Fork 0
mirror of https://github.com/holub/mame synced 2025-04-21 16:01:56 +03:00
Code Issues Actions 1 Packages Projects Releases Wiki Activity

m6809/konami: don't use m_opcode as a temp variable

Browse Source
This commit is contained in:
hap 2022-12-15 13:16:05 +01:00
parent f898e47c03
commit c23cebc36c
5 changed files with 47 additions and 38 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
src/devices/cpu/m6809/konami.cpp
View File

@ -7,6 +7,12 @@
Based on M6809 cpu core copyright John Butler
TODO:
- verify cycle timing
- verify status flag handling
- what happens with block/shift opcodes when count is 0? maybe a full loop?
parodius does an indexed LSRD and checks for A==0 to jump over the opcode
References:
6809 Simulator V09, By L.C. Benschop, Eindhoven The Netherlands.
@ -98,6 +104,9 @@ void konami_cpu_device::device_start()
{
super::device_start();
m_bcount = 0;
save_item(NAME(m_bcount));
// resolve callbacks
m_set_lines.resolve();
}

2
src/devices/cpu/m6809/konami.h
View File

@ -69,6 +69,8 @@ private:
template<class T> T safe_shift_left(T value, uint32_t shift);
void set_lines(uint8_t data);
void execute_one();
uint8_t m_bcount;
};
#define KONAMI_IRQ_LINE M6809_IRQ_LINE /* 0 - IRQ line number */

57
src/devices/cpu/m6809/konami.ops
View File

@ -467,8 +467,7 @@ MOVE:
return;
BMOVE:
// BMOVE does not appear to be interruptable, at least judging from the
// old implementation
// BMOVE does not appear to be interruptable, at least judging from the old implementation
while(m_u.w != 0)
{
@m_temp.b.l = read_memory(m_y.w++);
@ -478,8 +477,7 @@ BMOVE:
return;
BSET:
// BSET does not appear to be interruptable, at least judging from the
// old implementation
// BSET does not appear to be interruptable, at least judging from the old implementation
while(m_u.w != 0)
{
@eat(1);
@ -489,8 +487,7 @@ BSET:
return;
BSET2:
// BSET2 does not appear to be interruptable, at least judging from the
// old implementation
// BSET2 does not appear to be interruptable, at least judging from the old implementation
while(m_u.w != 0)
{
@eat(1);
@ -517,90 +514,90 @@ DECBJNZ:
LSRD:
// register addr.mode takes shift count from opcode operand, indexed addr.mode takes it from A
if (is_register_addressing_mode())
m_opcode = read_opcode_arg();
m_bcount = read_opcode_arg();
else
m_opcode = m_q.r.a;
m_bcount = m_q.r.a;
@m_temp.b.h = read_operand(0);
@m_temp.b.l = read_operand(1);
if (m_opcode != 0x00)
if (m_bcount != 0x00)
{
// set C condition code
if (m_temp.w & safe_shift_left(1, m_opcode - 1))
if (m_temp.w & safe_shift_left(1, m_bcount - 1))
m_cc |= CC_C;
else
m_cc &= ~CC_C;
m_temp.w = set_flags<uint16_t>(CC_NZ, safe_shift_right_unsigned<uint16_t>(m_temp.w, m_opcode));
m_temp.w = set_flags<uint16_t>(CC_NZ, safe_shift_right_unsigned<uint16_t>(m_temp.w, m_bcount));
@write_operand(0, m_temp.b.h);
write_operand(1, m_temp.b.l);
}
eat(m_opcode);
eat(m_bcount);
return;
ASLD:
// register addr.mode takes shift count from opcode operand, indexed addr.mode takes it from A
if (is_register_addressing_mode())
m_opcode = read_opcode_arg();
m_bcount = read_opcode_arg();
else
m_opcode = m_q.r.a;
m_bcount = m_q.r.a;
@m_temp.b.h = read_operand(0);
@m_temp.b.l = read_operand(1);
if (m_opcode != 0x00)
if (m_bcount != 0x00)
{
// set C condition code
if (m_temp.w & safe_shift_right(0x10000, m_opcode))
if (m_temp.w & safe_shift_right(0x10000, m_bcount))
m_cc |= CC_C;
else
m_cc &= ~CC_C;
m_temp.w = set_flags<uint16_t>(CC_NZV, safe_shift_left<int16_t>(m_temp.w, m_opcode));
m_temp.w = set_flags<uint16_t>(CC_NZV, safe_shift_left<int16_t>(m_temp.w, m_bcount));
@write_operand(0, m_temp.b.h);
write_operand(1, m_temp.b.l);
}
eat(m_opcode);
eat(m_bcount);
return;
ASRD:
// register addr.mode takes shift count from opcode operand, indexed addr.mode takes it from A
if (is_register_addressing_mode())
m_opcode = read_opcode_arg();
m_bcount = read_opcode_arg();
else
m_opcode = m_q.r.a;
m_bcount = m_q.r.a;
@m_temp.b.h = read_operand(0);
@m_temp.b.l = read_operand(1);
if (m_opcode != 0x00)
if (m_bcount != 0x00)
{
// set C condition code
if (m_temp.w & safe_shift_left(1, m_opcode - 1))
if (m_temp.w & safe_shift_left(1, m_bcount - 1))
m_cc |= CC_C;
else
m_cc &= ~CC_C;
m_temp.w = set_flags<uint16_t>(CC_NZ, safe_shift_right<int16_t>(m_temp.w, m_opcode));
m_temp.w = set_flags<uint16_t>(CC_NZ, safe_shift_right<int16_t>(m_temp.w, m_bcount));
@write_operand(0, m_temp.b.h);
write_operand(1, m_temp.b.l);
}
eat(m_opcode);
eat(m_bcount);
return;
ROLD:
// register addr.mode takes shift count from opcode operand, indexed addr.mode takes it from A
if (is_register_addressing_mode())
m_opcode = read_opcode_arg();
m_bcount = read_opcode_arg();
else
m_opcode = m_q.r.a;
m_bcount = m_q.r.a;
@m_temp.b.h = read_operand(0);
@m_temp.b.l = read_operand(1);
// doing this as a loop is lame
while(m_opcode--)
while(m_bcount--)
{
@eat(1);
m_temp.w = set_flags<uint16_t>(CC_NZ, rotate_left(m_temp.w));
@ -612,15 +609,15 @@ ROLD:
RORD:
// register addr.mode takes shift count from opcode operand, indexed addr.mode takes it from A
if (is_register_addressing_mode())
m_opcode = read_opcode_arg();
m_bcount = read_opcode_arg();
else
m_opcode = m_q.r.a;
m_bcount = m_q.r.a;
@m_temp.b.h = read_operand(0);
@m_temp.b.l = read_operand(1);
// doing this as a loop is lame
while(m_opcode--)
while(m_bcount--)
{
@eat(1);
m_temp.w = set_flags<uint16_t>(CC_NZ, rotate_right(m_temp.w));

1
src/mame/handheld/hh_tms1k.cpp
View File

@ -110,6 +110,7 @@ on Joerg Woerner's datamath.org: http://www.datamath.org/IC_List.htm
@MP1296 TMS1100 1982, Entex Black Knight Pinball (6081)
@MP1311 TMS1100 1981, Bandai TC7: Air Traffic Control
@MP1312 TMS1100 1981, Gakken FX-Micom R-165/Radio Shack Science Fair Microcomputer Trainer
*MP1343 TMS1100 1989, Micronta Vox Clock 3
*MP1359 TMS1100? 1985, Capsela CRC2000
@MP1525 TMS1170 1980, Coleco Head to Head: Electronic Baseball
@MP1604 TMS1370 1982, Gakken Invader 2000/Tandy Cosmic Fire Away 3000

16
src/mame/tecmo/tehkanwc.cpp
View File

@ -142,8 +142,8 @@ private:
required_ioport_array<2> m_track_p2;
output_finder<2> m_digits;
int m_track0[2]{};
int m_track1[2]{};
int m_track_p1_reset[2]{};
int m_track_p2_reset[2]{};
int m_msm_data_offs = 0;
int m_toggle = 0;
uint8_t m_scroll_x[2]{};
@ -190,8 +190,8 @@ private:
void tehkanwc_state::machine_start()
{
// register for savestates
save_item(NAME(m_track0));
save_item(NAME(m_track1));
save_item(NAME(m_track_p1_reset));
save_item(NAME(m_track_p2_reset));
save_item(NAME(m_msm_data_offs));
save_item(NAME(m_toggle));
save_item(NAME(m_scroll_x));
@ -219,24 +219,24 @@ void tehkanwc_state::sound_command_w(uint8_t data)
uint8_t tehkanwc_state::track_0_r(offs_t offset)
{
return m_track_p1[offset]->read() - m_track0[offset];
return m_track_p1[offset]->read() - m_track_p1_reset[offset];
}
uint8_t tehkanwc_state::track_1_r(offs_t offset)
{
return m_track_p2[offset]->read() - m_track1[offset];
return m_track_p2[offset]->read() - m_track_p2_reset[offset];
}
void tehkanwc_state::track_0_reset_w(offs_t offset, uint8_t data)
{
// reset the trackball counters
m_track0[offset] = m_track_p1[offset]->read() + data;
m_track_p1_reset[offset] = m_track_p1[offset]->read() + data;
}
void tehkanwc_state::track_1_reset_w(offs_t offset, uint8_t data)
{
// reset the trackball counters
m_track1[offset] = m_track_p2[offset]->read() + data;
m_track_p2_reset[offset] = m_track_p2[offset]->read() + data;
}