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https://github.com/holub/mame
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@ -50,6 +50,10 @@ offs_t m58846_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *o
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void m58846_device::device_start()
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{
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melps4_cpu_device::device_start();
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// set fixed state
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m_bm_page = 2;
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m_int_page = 1;
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}
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@ -4,7 +4,8 @@
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Mitsubishi MELPS 4 MCU family cores
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Known types and their features: (* means not emulated yet)
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Known types and their features:
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(* means not emulated yet)
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*M58840: 42-pin DIL, 2Kx9 ROM, 128x4 RAM, A/D converter
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*M58841: almost same as M58840
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@ -16,10 +17,12 @@
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*M58847: 40-pin DIL, 2Kx9 ROM, 128x4 RAM, extra I/O ports(not same as M58846)
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MELPS 41/42 subfamily:
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*M58494: 72-pin QFP CMOS, 4Kx10 ROM, 32x4 internal + 4Kx4 external RAM, 2 timers
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*M58496: 72-pin QFP CMOS, 2Kx10 ROM, 128x4 internal + 256x4 external RAM, 1 timer, low-power
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*M58497: almost same as M58496
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References:
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- 1982 Mitsubishi LSI Data Book
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@ -31,15 +34,35 @@
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#include "melps4op.inc"
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// disasm
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void melps4_cpu_device::state_string_export(const device_state_entry &entry, std::string &str)
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{
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switch (entry.index())
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{
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// obviously not from a single flags register, letters are made up
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case STATE_GENFLAGS:
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strprintf(str, "%c%c%c%c",
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m_intp ? 'P':'p',
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m_inte ? 'I':'i',
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m_cps ? 'D':'d',
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m_cy ? 'C':'c'
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);
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break;
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default: break;
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}
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}
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//-------------------------------------------------
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// device_start - device-specific startup
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//-------------------------------------------------
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enum
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{
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MELPS4_PC=1, MELPS4_A, MELPS4_B,
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MELPS4_Y, MELPS4_X, MELPS4_Z, MELPS4_CY, MELPS4_CPS,
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MELPS4_E
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MELPS4_PC=1, MELPS4_A, MELPS4_B, MELPS4_E,
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MELPS4_Y, MELPS4_X, MELPS4_Z,
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MELPS4_H, MELPS4_L, MELPS4_C, MELPS4_V, MELPS4_W
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};
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void melps4_cpu_device::device_start()
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@ -48,52 +71,76 @@ void melps4_cpu_device::device_start()
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m_data = &space(AS_DATA);
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m_prgmask = (1 << m_prgwidth) - 1;
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m_datamask = (1 << m_datawidth) - 1;
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// zerofill
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m_pc = 0;
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m_prev_pc = 0;
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memset(m_stack, 0, sizeof(m_stack));
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m_op = 0;
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m_prev_op = 0;
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m_cps = 0;
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m_skip = false;
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m_inte = 0;
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m_intp = 1;
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m_a = 0;
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m_b = 0;
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m_e = 0;
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m_y = m_y2 = 0;
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m_x = m_x2 = 0;
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m_z = m_z2 = 0;
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m_cy = m_cy2 = 0;
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m_e = 0;
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m_h = 0;
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m_l = 0;
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m_c = 7;
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m_v = 0;
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m_w = 0;
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// register for savestates
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save_item(NAME(m_pc));
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save_item(NAME(m_prev_pc));
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save_item(NAME(m_stack));
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save_item(NAME(m_op));
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save_item(NAME(m_prev_op));
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save_item(NAME(m_cps));
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save_item(NAME(m_skip));
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save_item(NAME(m_inte));
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save_item(NAME(m_intp));
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save_item(NAME(m_a));
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save_item(NAME(m_b));
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save_item(NAME(m_e));
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save_item(NAME(m_y)); save_item(NAME(m_y2));
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save_item(NAME(m_x)); save_item(NAME(m_x2));
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save_item(NAME(m_z)); save_item(NAME(m_z2));
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save_item(NAME(m_cy)); save_item(NAME(m_cy2));
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save_item(NAME(m_e));
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save_item(NAME(m_h));
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save_item(NAME(m_l));
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save_item(NAME(m_c));
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save_item(NAME(m_v));
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save_item(NAME(m_w));
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// register state for debugger
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state_add(STATE_GENPC, "curpc", m_pc).formatstr("%04X").noshow();
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state_add(STATE_GENFLAGS, "GENFLAGS", m_cy).formatstr("%1s").noshow();
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state_add(STATE_GENFLAGS, "GENFLAGS", m_cy).formatstr("%4s").noshow();
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state_add(MELPS4_PC, "PC", m_pc).formatstr("%04X");
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state_add(MELPS4_A, "A", m_a).formatstr("%2d");
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state_add(MELPS4_B, "B", m_b).formatstr("%2d");
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state_add(MELPS4_CPS, "CPS", m_cps).formatstr("%1d");
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state_add(MELPS4_Y, "Y", m_y).formatstr("%2d");
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state_add(MELPS4_A, "A", m_a).formatstr("%2d"); // show in decimal
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state_add(MELPS4_B, "B", m_b).formatstr("%2d"); // "
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state_add(MELPS4_E, "E", m_e).formatstr("%02X");
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state_add(MELPS4_Y, "Y", m_y).formatstr("%1X");
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state_add(MELPS4_X, "X", m_x).formatstr("%1d");
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state_add(MELPS4_Z, "Z", m_z).formatstr("%1d");
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state_add(MELPS4_CY, "CY", m_cy).formatstr("%1d");
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state_add(MELPS4_E, "E", m_e).formatstr("%02X");
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state_add(MELPS4_H, "H", m_h).formatstr("%1X");
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state_add(MELPS4_L, "L", m_l).formatstr("%1X");
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state_add(MELPS4_C, "C", m_c).formatstr("%1X");
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state_add(MELPS4_V, "V", m_v).formatstr("%1X");
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state_add(MELPS4_W, "W", m_w).formatstr("%1X");
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m_icountptr = &m_icount;
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}
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@ -106,6 +153,14 @@ void melps4_cpu_device::device_start()
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void melps4_cpu_device::device_reset()
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{
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m_op = m_prev_op = 0;
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m_pc = m_prev_pc = 0;
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m_inte = 0;
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m_intp = 1;
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op_lcps(); // CPS=0
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m_v = 0;
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m_w = 0;
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}
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@ -129,6 +184,10 @@ void melps4_cpu_device::execute_run()
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{
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while (m_icount > 0)
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{
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// remember previous state
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m_prev_op = m_op;
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m_prev_pc = m_pc;
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// fetch next opcode
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debugger_instruction_hook(this, m_pc);
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m_icount--;
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@ -22,6 +22,10 @@ public:
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, m_data_config("data", ENDIANNESS_LITTLE, 8, datawidth, 0, data)
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, m_prgwidth(prgwidth)
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, m_datawidth(datawidth)
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, m_stack_levels(3)
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, m_bm_page(14)
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, m_int_page(12)
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, m_xami_mask(0)
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{ }
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protected:
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@ -44,35 +48,52 @@ protected:
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// device_disasm_interface overrides
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virtual UINT32 disasm_min_opcode_bytes() const { return 2; }
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virtual UINT32 disasm_max_opcode_bytes() const { return 2; }
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virtual void state_string_export(const device_state_entry &entry, std::string &str);
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address_space_config m_program_config;
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address_space_config m_data_config;
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address_space *m_program;
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address_space *m_data;
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int m_prgwidth;
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int m_datawidth;
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int m_prgmask;
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int m_datamask;
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int m_icount;
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// fixed settings or mask options
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int m_prgwidth; // number of bits and bitmask for ROM/RAM size
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int m_datawidth; // "
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int m_prgmask; // "
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int m_datamask; // "
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UINT8 m_stack_levels; // 3 levels on MELPS 4, 12 levels on MELPS 41/42
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UINT8 m_bm_page; // short BM default page: 14 on '40 to '44, 2 on '45,'46, 0 on '47
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UINT8 m_int_page; // interrupt routine page: 12 on '40 to '44, 1 on '45,'46, 2 on '47
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UINT8 m_xami_mask; // mask option for XAMI opcode on '40,'41,'45 (0 for others)
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// internal state, misc regs
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UINT16 m_pc; // program counter (11 or 10-bit)
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UINT16 m_prev_pc;
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UINT16 m_stack[3]; // callstack, 3 levels
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UINT16 m_stack[12]; // callstack
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UINT16 m_op;
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UINT16 m_prev_op;
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UINT8 m_cps; // DP,CY or DP',CY' selected
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bool m_skip; // skip next opcode
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UINT8 m_inte; // interrupt enable flag
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UINT8 m_intp; // external interrupt polarity ('40 to '44)
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// registers (unless specified, each is 4-bit)
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// work registers (unless specified, each is 4-bit)
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UINT8 m_a; // accumulator
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UINT8 m_b; // generic
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UINT8 m_e; // 8-bit register, hold data for S output
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UINT8 m_y, m_y2; // RAM index Y, Y' (Z.XX.YYYY is DP aka Data Pointer)
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UINT8 m_x, m_x2; // RAM index X, X', 2-bit
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UINT8 m_z, m_z2; // RAM index Z, Z', 1-bit, optional
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UINT8 m_cy, m_cy2; // carry flag(s)
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UINT8 m_e; // 8-bit register, hold data for S output
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UINT8 m_h; // A/D converter H or generic
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UINT8 m_l; // A/D converter L or generic
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UINT8 m_c; // A/D converter counter
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UINT8 m_v; // timer control V
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UINT8 m_w; // timer control W
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// misc internal helpers
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UINT8 ram_r();
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@ -82,10 +82,11 @@ void melps4_cpu_device::op_tax()
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void melps4_cpu_device::op_lxy()
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{
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// LXY x,y: load immediate into X,Y, skip any next LXY
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m_x = m_op >> 4 & 3;
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m_y = m_op & 0xf;
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op_illegal();
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if ((m_op & ~0x3f) != (m_prev_op & ~0x3f))
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{
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m_x = m_op >> 4 & 3;
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m_y = m_op & 0xf;
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}
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}
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void melps4_cpu_device::op_lz()
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@ -170,9 +171,8 @@ void melps4_cpu_device::op_xami()
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{
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// XAMI j: XAM J, INY, skip next on Y=mask(default 0)
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op_xam();
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op_dey();
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op_illegal();
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op_iny();
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m_skip = (m_y == m_xami_mask);
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}
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@ -181,9 +181,8 @@ void melps4_cpu_device::op_xami()
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void melps4_cpu_device::op_la()
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{
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// LA n: load immediate into A, skip any next LA
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m_a = m_op & 0xf;
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op_illegal();
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if ((m_op & ~0xf) != (m_prev_op & ~0xf))
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m_a = m_op & 0xf;
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}
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void melps4_cpu_device::op_am()
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@ -259,7 +258,7 @@ void melps4_cpu_device::op_rb()
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void melps4_cpu_device::op_szb()
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{
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// SZB j: skip next if RAM bit is reset
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// SZB j: skip next if RAM bit is 0
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UINT8 mask = 1 << (m_op & 3);
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m_skip = !(ram_r() & mask);
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}
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@ -285,55 +284,68 @@ void melps4_cpu_device::op_sey()
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void melps4_cpu_device::op_tla()
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{
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// TLA: transfer A to L
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op_illegal();
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m_l = m_a;
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}
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void melps4_cpu_device::op_tha()
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{
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// THA: transfer A to H
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op_illegal();
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m_h = m_a;
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}
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void melps4_cpu_device::op_taj()
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{
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// TAJ: transfer J to A
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// TAJ: transfer J(hi/lo) to A designated by Y
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op_illegal();
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}
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void melps4_cpu_device::op_xal()
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{
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// XAL: exchange A with L
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op_illegal();
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UINT8 a = m_a;
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m_a = m_l;
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m_l = a;
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}
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void melps4_cpu_device::op_xah()
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{
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// XAH: exchange A with H
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op_illegal();
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UINT8 a = m_a;
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m_a = m_h;
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m_h = a;
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}
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void melps4_cpu_device::op_lc7()
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{
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// LC7: load 7 into C
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op_illegal();
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m_c = 7;
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}
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void melps4_cpu_device::op_dec()
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{
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// DEC: decrement C, skip next on overflow
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op_illegal();
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m_c = (m_c - 1) & 7;
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m_skip = (m_c == 7);
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}
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void melps4_cpu_device::op_shl()
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{
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// SHL: set bit in L or H designated by C
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op_illegal();
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UINT8 mask = 1 << (m_c & 3);
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if (m_c & 4)
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m_h |= mask;
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else
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m_l |= mask;
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}
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void melps4_cpu_device::op_rhl()
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{
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// RHL: reset bit in L or H designated by C
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op_illegal();
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UINT8 mask = 1 << (m_c & 3);
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if (m_c & 4)
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m_h &= ~mask;
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else
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m_l &= ~mask;
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}
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void melps4_cpu_device::op_cpa()
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@ -356,7 +368,7 @@ void melps4_cpu_device::op_cpae()
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void melps4_cpu_device::op_szj()
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{
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// SZJ: ..
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// SZJ: skip next if J bit designated by Y is 0
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op_illegal();
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}
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@ -462,7 +474,8 @@ void melps4_cpu_device::op_rt()
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void melps4_cpu_device::op_rts()
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{
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// RTS: RT, skip next
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op_illegal();
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op_rt();
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m_skip = true;
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}
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void melps4_cpu_device::op_rti()
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@ -576,25 +589,25 @@ void melps4_cpu_device::op_su()
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void melps4_cpu_device::op_ei()
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{
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// EI: enable interrupt flag
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op_illegal();
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m_inte = 1;
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}
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void melps4_cpu_device::op_di()
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{
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// DI: disable interrupt flag
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op_illegal();
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m_inte = 0;
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}
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void melps4_cpu_device::op_inth()
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{
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// INTH: set interrupt polarity high
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op_illegal();
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// INTH: set external interrupt polarity high (rising edge)
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m_intp = 1;
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}
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void melps4_cpu_device::op_intl()
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{
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// INTL: set interrupt polarity low
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op_illegal();
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// INTL: set external interrupt polarity low (falling edge)
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m_intp = 0;
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}
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