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ampex210p: Add XTAL values, video RAM, etc. (nw)

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This commit is contained in:
AJR 2018-09-17 04:06:17 -04:00
parent 383eb1b7aa
commit c33edfd060
2 changed files with 23 additions and 6 deletions
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2
src/emu/xtal.cpp
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@ -235,6 +235,7 @@ const double XTAL::known_xtals[] = {
18'869'600, /* 18.8696_MHz_XTAL Memorex 2178 */
19'339'600, /* 19.3396_MHz_XTAL TeleVideo TVI-955 80-column display clock */
19'600'000, /* 19.6_MHz_XTAL Universal Mr. Do - Model 8021 PCB */
19'602'000, /* 19.602_MHz_XTAL Ampex 210+ 80-column display clock */
19'660'800, /* 19.6608_MHz_XTAL Euro League (bootleg), labeled as "UKI 19.6608 20PF" */
19'661'400, /* 19.6614_MHz_XTAL Wyse WY-30 */
19'923'000, /* 19.923_MHz_XTAL Cinematronics vectors */
@ -304,6 +305,7 @@ const double XTAL::known_xtals[] = {
31'684'000, /* 31.684_MHz_XTAL TeleVideo TVI-955 132-column display clock */
31'948'800, /* 31.9488_MHz_XTAL NEC PC-88xx, PC-98xx */
32'000'000, /* 32_MHz_XTAL - */
32'147'000, /* 32.147_MHz_XTAL Ampex 210+ 132-column display clock */
32'220'000, /* 32.22_MHz_XTAL Typically used on 90's Data East PCBs (close to 9x NTSC subcarrier which is 32.215905Mhz */
32'317'400, /* 32.3174_MHz_XTAL DEC VT330, VT340 */
32'530'400, /* 32.5304_MHz_XTAL Seta 2 */

27
src/mame/drivers/ampex210.cpp
View File

@ -9,6 +9,7 @@
#include "emu.h"
#include "cpu/z80/z80.h"
#include "machine/mos6551.h"
#include "machine/nvram.h"
#include "video/scn2674.h"
#include "screen.h"
@ -29,6 +30,8 @@ private:
void mem_map(address_map &map);
void io_map(address_map &map);
void vram_map(address_map &map);
required_device<cpu_device> m_maincpu;
required_region_ptr<u8> m_chargen;
};
@ -41,7 +44,7 @@ SCN2672_DRAW_CHARACTER_MEMBER(ampex210_state::draw_character)
void ampex210_state::mem_map(address_map &map)
{
map(0x0000, 0x7fff).rom().region("maincpu", 0);
map(0x8000, 0x87ff).ram();
map(0x8000, 0x87ff).ram().share("nvram");
map(0x8800, 0x9fff).ram();
}
@ -51,6 +54,14 @@ void ampex210_state::io_map(address_map &map)
map(0x00, 0x07).rw("pvtc", FUNC(scn2672_device::read), FUNC(scn2672_device::write));
map(0x44, 0x47).rw("acia", FUNC(mos6551_device::read), FUNC(mos6551_device::write));
map(0x80, 0x80).nopw();
map(0xc0, 0xc0).w("pvtc", FUNC(scn2672_device::buffer_w));
map(0xc1, 0xc1).r("pvtc", FUNC(scn2672_device::buffer_r));
map(0xc7, 0xc7).nopw();
}
void ampex210_state::vram_map(address_map &map)
{
map(0x0000, 0x1fff).ram(); // MB8464A-10L (second half unused?)
}
@ -60,21 +71,25 @@ INPUT_PORTS_END
void ampex210_state::ampex210p(machine_config &config)
{
Z80(config, m_maincpu, 4'000'000);
Z80(config, m_maincpu, 3.6864_MHz_XTAL); // Z80ACPU; clock uncertain
m_maincpu->set_addrmap(AS_PROGRAM, &ampex210_state::mem_map);
m_maincpu->set_addrmap(AS_IO, &ampex210_state::io_map);
mos6551_device &acia(MOS6551(config, "acia", 1'843'200));
NVRAM(config, "nvram", nvram_device::DEFAULT_ALL_0); // UM6116-2
mos6551_device &acia(MOS6551(config, "acia", 3.6864_MHz_XTAL / 2)); // AMI S6551AP
acia.irq_handler().set_inputline("maincpu", INPUT_LINE_IRQ0);
scn2672_device &pvtc(SCN2672(config, "pvtc", 2'178'000));
scn2672_device &pvtc(SCN2672(config, "pvtc", 19.602_MHz_XTAL / 9)); // MC2672B4P
pvtc.intr_callback().set_inputline("maincpu", INPUT_LINE_NMI);
pvtc.set_character_width(10);
pvtc.set_character_width(9);
pvtc.set_display_callback(FUNC(ampex210_state::draw_character));
pvtc.set_addrmap(0, &ampex210_state::vram_map);
pvtc.set_screen("screen");
screen_device &screen(SCREEN(config, "screen", SCREEN_TYPE_RASTER));
screen.set_raw(21'780'000, 1000, 0, 800, 363, 0, 300); // clock guessed
screen.set_raw(19.602_MHz_XTAL, 900, 0, 720, 363, 0, 300);
//screen.set_raw(32.147_MHz_XTAL, 1476, 0, 1188, 363, 0, 300);
screen.set_screen_update("pvtc", FUNC(scn2672_device::screen_update));
}