mirror of
https://github.com/holub/mame
synced 2025-06-22 20:38:50 +03:00
not really making much sense yet..
This commit is contained in:
davidhay
parent
6d87810b1f
commit
c39f1606da
@ -91,8 +91,8 @@ extern READ16_HANDLER( denjinmk_cop_mcu_r );
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extern WRITE16_HANDLER( denjinmk_cop_mcu_w );
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extern READ16_HANDLER( sdgndmrb_cop_mcu_r );
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extern WRITE16_HANDLER( sdgndmrb_cop_mcu_w );
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extern READ16_HANDLER( copdx_0_r );
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extern WRITE16_HANDLER( copdx_0_w );
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extern READ16_HANDLER( cupsoc_cop_mcu_r );
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extern WRITE16_HANDLER( cupsoc_cop_mcu_w );
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extern READ16_HANDLER( copdxbl_0_r );
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extern WRITE16_HANDLER( copdxbl_0_w );
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@ -210,7 +210,7 @@ ADDRESS_MAP_END
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static ADDRESS_MAP_START( cupsoc_mem, ADDRESS_SPACE_PROGRAM, 16 )
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AM_RANGE(0x000000, 0x0fffff) AM_ROM
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//AM_RANGE(0x100000, 0x1003ff) AM_RAM
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AM_RANGE(0x100000, 0x1007ff) AM_RAM AM_READWRITE(copdx_0_r,copdx_0_w) AM_BASE(&cop_mcu_ram)
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AM_RANGE(0x100000, 0x1007ff) AM_RAM AM_READWRITE(cupsoc_cop_mcu_r,cupsoc_cop_mcu_w) AM_BASE(&cop_mcu_ram)
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AM_RANGE(0x100800, 0x100fff) AM_RAM AM_READWRITE(SMH_RAM,legionna_background_w) AM_BASE(&legionna_back_data)
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AM_RANGE(0x101000, 0x1017ff) AM_RAM AM_WRITE(legionna_foreground_w) AM_BASE(&legionna_fore_data)
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AM_RANGE(0x101800, 0x101fff) AM_RAM AM_WRITE(legionna_midground_w) AM_BASE(&legionna_mid_data)
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@ -60,9 +60,11 @@ static UINT16 cop_438;
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static UINT16 cop_43a;
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static UINT16 cop_43c;
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static UINT16 cop_clearfill_address;
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static UINT16 cop_clearfill_length;
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static UINT16 cop_clearfill_value;
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static UINT16 cop_clearfill_address[0x200];
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static UINT16 cop_clearfill_length[0x200];
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static UINT16 cop_clearfill_value[0x200];
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static UINT16 cop_clearfill_lasttrigger = 0;
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static UINT16 copd2_offs = 0;
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@ -994,7 +996,7 @@ READ16_HANDLER( heatbrl_mcu_r )
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{
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default:
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{
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logerror("%06x: COPX unhandled read returning %04x from offset %04x\n", activecpu_get_pc(), retvalue, offset*2);
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printf("%06x: COPX unhandled read returning %04x from offset %04x\n", activecpu_get_pc(), retvalue, offset*2);
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return retvalue;
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}
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@ -1014,8 +1016,8 @@ READ16_HANDLER( heatbrl_mcu_r )
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case (0x59a/2): { return ((prot_bcd[2] & 0xffff0000) >> 16) + 0x3030; }
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case (0x59c/2): { return 0x3030; }
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//case (0x5b0/2): return (cop_mcu_ram[offset]); /* bit 15 is branched on a few times in the $1938 area */
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case (0x5b4/2): return (0); /* read at $1932 and stored in ram before +0x5b0 bit 15 tested */
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case (0x5b0/2): return (0xffff); /* bit 15 is branched on a few times in the $1938 area */
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case (0x5b4/2): return (0xffff); /* read at $1932 and stored in ram before +0x5b0 bit 15 tested */
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/*********************************************************************
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700-7ff - Non-protection reads
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@ -1069,22 +1071,56 @@ WRITE16_HANDLER( heatbrl_mcu_w )
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/* Layer Clearing */
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case (0x478/2): /* clear address */
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{
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cop_clearfill_address = data; // << 6 to get actual address
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printf("%06x: COPX set layer clear address to %04x (actual %08x)\n", activecpu_get_pc(), data, cop_clearfill_address<<6);
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cop_clearfill_address[cop_clearfill_lasttrigger] = data; // << 6 to get actual address
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printf("%06x: COPX set layer clear address to %04x (actual %08x)\n", activecpu_get_pc(), data, data<<6);
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break;
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}
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case (0x47a/2): /* clear length */
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{
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cop_clearfill_length = data;
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printf("%06x: COPX set layer clear length to %04x (actual %08x)\n", activecpu_get_pc(), data, cop_clearfill_length<<5);
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cop_clearfill_length[cop_clearfill_lasttrigger] = data;
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printf("%06x: COPX set layer clear length to %04x (actual %08x)\n", activecpu_get_pc(), data, data<<5);
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/* do the fill */
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break;
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}
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case (0x47c/2): /* clear value? */
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{
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cop_clearfill_value[cop_clearfill_lasttrigger] = data;
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printf("%06x: COPX set layer clear value to %04x (actual %08x)\n", activecpu_get_pc(), data, data<<6);
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break;
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}
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/* unknown, related to clears? / DMA? */
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case (0x47e/2):
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{
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cop_clearfill_lasttrigger = data;
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printf("%06x: COPX set layer clear trigger? to %04x\n", activecpu_get_pc(), data);
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if (data>=0x1ff)
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{
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printf("invalid!, >0x1ff\n");
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cop_clearfill_lasttrigger = 0;
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}
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break;
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}
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/* hmm, this would be strange the 6xx range should be video regs?? */
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case (0x6fc/2):
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{
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printf("%06x: COPX execute current layer clear??? %04x\n", activecpu_get_pc(), data);
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// I think the value it writes here must match the other value for anything to happen.. maybe */
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//if (data!=cop_clearfill_value[cop_clearfill_lasttrigger]) break;
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if ((cop_clearfill_lasttrigger==0x14) || (cop_clearfill_lasttrigger==0x15)) return;
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/* do the fill */
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if (cop_clearfill_value[cop_clearfill_lasttrigger]==0x0000)
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{
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UINT32 length, address;
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int i;
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address = cop_clearfill_address << 6;
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length = (cop_clearfill_length+1) << 5;
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address = cop_clearfill_address[cop_clearfill_lasttrigger] << 6;
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length = (cop_clearfill_length[cop_clearfill_lasttrigger]+1) << 5;
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for (i=address;i<address+length;i+=2)
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{
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@ -1094,16 +1130,6 @@ WRITE16_HANDLER( heatbrl_mcu_w )
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break;
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}
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case (0x47c/2): /* clear value? */
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{
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cop_clearfill_value = data;
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printf("%06x: COPX set layer clear value to %04x (actual %08x)\n", activecpu_get_pc(), data, cop_clearfill_value<<5);
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break;
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}
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/* unknown, related to clears? / DMA? */
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//case (0x47e/2): { break; }
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/* Registers */
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case (0x4c0/2): { prot_data[0] = cop_mcu_ram[offset]; ram_addr[0] = (prot_data[0]&0xffff)|((prot_data[1]&0xffff)<<16); break; }
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@ -1202,6 +1228,7 @@ READ16_HANDLER( sdgndmrb_cop_mcu_r )
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case (0x59c/2): { return 0x3030; }
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case (0x5b0/2):
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return 2;
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/*check if the DMA has been finished*/
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if(dma_status == 1)
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{
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@ -1257,40 +1284,72 @@ WRITE16_HANDLER( sdgndmrb_cop_mcu_w )
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case (0x43a/2): {cop_43a = data; break; }
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case (0x43c/2): {cop_43c = data; break; }
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case (0x478/2):
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/* Odd, this is a video register */
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case (0x470/2): { heatbrl_setgfxbank( cop_mcu_ram[offset] ); break; }
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/* Layer Clearing */
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case (0x478/2): /* clear address */
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{
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static UINT16 i;
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/*
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AM_RANGE(0x100800, 0x100fff) AM_WRITE(legionna_background_w) AM_BASE(&legionna_back_data)
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AM_RANGE(0x101000, 0x1017ff) AM_WRITE(legionna_foreground_w) AM_BASE(&legionna_fore_data)
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AM_RANGE(0x101800, 0x101fff) AM_WRITE(legionna_midground_w) AM_BASE(&legionna_mid_data)
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AM_RANGE(0x102000, 0x102fff) AM_WRITE(legionna_text_w) AM_BASE(&legionna_textram)
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*/
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switch(cop_mcu_ram[offset])
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cop_clearfill_address[cop_clearfill_lasttrigger] = data; // << 6 to get actual address
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printf("%06x: COPX set layer clear address to %04x (actual %08x)\n", activecpu_get_pc(), data, data<<6);
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break;
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}
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case (0x47a/2): /* clear length */
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{
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cop_clearfill_length[cop_clearfill_lasttrigger] = data;
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printf("%06x: COPX set layer clear length to %04x (actual %08x)\n", activecpu_get_pc(), data, data<<5);
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break;
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}
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case (0x47c/2): /* clear value? */
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{
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cop_clearfill_value[cop_clearfill_lasttrigger] = data;
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printf("%06x: COPX set layer clear value to %04x (actual %08x)\n", activecpu_get_pc(), data, data<<6);
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break;
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}
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/* unknown, related to clears? / DMA? */
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case (0x47e/2):
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{
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cop_clearfill_lasttrigger = data;
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printf("%06x: COPX set layer clear trigger? to %04x\n", activecpu_get_pc(), data);
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if (data>=0x1ff)
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{
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/*txt layer clearance*/
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case 0x4080:
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for(i=0;i<0x1000;i+=2)
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program_write_word(i+0x102000,0x0000);
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break;
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case 0x4100: break;
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case 0x41c0: break;
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//default: popmessage("%04x",cop_mcu_ram[offset]);
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printf("invalid!, >0x1ff\n");
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cop_clearfill_lasttrigger = 0;
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}
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break;
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}
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/* hmm, this would be strange the 6xx range should be video regs?? */
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case (0x6fc/2):
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{
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printf("%06x: COPX execute current layer clear??? %04x\n", activecpu_get_pc(), data);
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// I think the value it writes here must match the other value for anything to happen.. maybe */
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//if (data!=cop_clearfill_value[cop_clearfill_lasttrigger]) break;
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if ((cop_clearfill_lasttrigger==0x14) || (cop_clearfill_lasttrigger==0x15)) return;
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/* do the fill */
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if (cop_clearfill_value[cop_clearfill_lasttrigger]==0x0000)
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{
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UINT32 length, address;
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int i;
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address = cop_clearfill_address[cop_clearfill_lasttrigger] << 6;
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length = (cop_clearfill_length[cop_clearfill_lasttrigger]+1) << 5;
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for (i=address;i<address+length;i+=2)
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{
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program_write_word(i, 0x0000);
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}
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}
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break;
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}
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/*sprite ram clear(Guess)*/
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case (0x47e/2):
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{
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static UINT16 i;
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if(cop_mcu_ram[0x47e/2] == 0x118)
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{
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for(i=0;i<0x800;i+=2)
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program_write_word((0x107000 | i),0x0000);
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}
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break;
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}
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/* MCU registers */
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case (0x4c0/2): { prot_data[0] = cop_mcu_ram[offset]; ram_addr[0] = (prot_data[0]&0xffff)|((prot_data[1]&0xffff)<<16); break; }
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@ -1441,7 +1500,7 @@ WRITE16_HANDLER( sdgndmrb_cop_mcu_w )
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/* Seems a mirror for the choices in the test menu... */
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case (0x67c/2): break;
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case (0x680/2): break;
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case (0x6fc/2): break;
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//case (0x6fc/2): break;
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case (0x700/2): { seibu_main_word_w(machine,0,cop_mcu_ram[offset],0xff00); break; }
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case (0x704/2): { seibu_main_word_w(machine,1,cop_mcu_ram[offset],0xff00); break; }
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@ -1514,8 +1573,67 @@ WRITE16_HANDLER( denjinmk_cop_mcu_w )
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case (0x43c/2): {cop_43c = data; break; }
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/* again, strange, this is a video register */
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case (0x470/2): { denjinmk_setgfxbank( cop_mcu_ram[offset] ); break; }
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/* Layer Clearing */
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case (0x478/2): /* clear address */
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{
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cop_clearfill_address[cop_clearfill_lasttrigger] = data; // << 6 to get actual address
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printf("%06x: COPX set layer clear address to %04x (actual %08x)\n", activecpu_get_pc(), data, data<<6);
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break;
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}
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case (0x47a/2): /* clear length */
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{
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cop_clearfill_length[cop_clearfill_lasttrigger] = data;
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printf("%06x: COPX set layer clear length to %04x (actual %08x)\n", activecpu_get_pc(), data, data<<5);
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break;
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}
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case (0x47c/2): /* clear value? */
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{
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cop_clearfill_value[cop_clearfill_lasttrigger] = data;
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printf("%06x: COPX set layer clear value to %04x (actual %08x)\n", activecpu_get_pc(), data, data<<6);
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break;
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}
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/* unknown, related to clears? / DMA? */
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case (0x47e/2):
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{
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cop_clearfill_lasttrigger = data;
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printf("%06x: COPX set layer clear trigger? to %04x\n", activecpu_get_pc(), data);
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if (data>=0x1ff)
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{
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printf("invalid!, >0x1ff\n");
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cop_clearfill_lasttrigger = 0;
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}
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break;
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}
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/* hmm, this would be strange the 6xx range should be video regs?? */
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case (0x6fc/2):
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{
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printf("%06x: COPX execute current layer clear??? %04x\n", activecpu_get_pc(), data);
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// I think the value it writes here must match the other value for anything to happen.. maybe */
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if (data!=cop_clearfill_value[cop_clearfill_lasttrigger]) break;
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/* do the fill */
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if (cop_clearfill_value[cop_clearfill_lasttrigger]==0x0000)
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{
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UINT32 length, address;
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int i;
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address = cop_clearfill_address[cop_clearfill_lasttrigger] << 6;
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length = (cop_clearfill_length[cop_clearfill_lasttrigger]+1) << 5;
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for (i=address;i<address+length;i+=2)
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{
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program_write_word(i, 0x0000);
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}
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}
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break;
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}
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case (0x620/2): { legionna_scrollram16[0] = cop_mcu_ram[offset]; break; }
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case (0x622/2): { legionna_scrollram16[1] = cop_mcu_ram[offset]; break; }
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@ -1591,6 +1709,7 @@ WRITE16_HANDLER( godzilla_cop_mcu_w )
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case (0x43a/2): {cop_43a = data; break; }
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case (0x43c/2): {cop_43c = data; break; }
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/* Layer Clear */
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case (0x478/2):
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{
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@ -1614,6 +1733,8 @@ WRITE16_HANDLER( godzilla_cop_mcu_w )
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break;
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}
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case (0x620/2): { legionna_scrollram16[0] = cop_mcu_ram[offset]; break; }
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case (0x622/2): { legionna_scrollram16[1] = cop_mcu_ram[offset]; break; }
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case (0x624/2): { legionna_scrollram16[2] = cop_mcu_ram[offset]; break; }
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@ -1636,7 +1757,7 @@ WRITE16_HANDLER( godzilla_cop_mcu_w )
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*******************************************************************************************/
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READ16_HANDLER( copdx_0_r )
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READ16_HANDLER( cupsoc_cop_mcu_r )
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{
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UINT16 retvalue = cop_mcu_ram[offset];
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@ -1740,7 +1861,7 @@ static void cop_reg_w(UINT16 data,UINT8 offset,UINT8 mask)
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//popmessage("%08x",cop_reg[offset]);
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}
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WRITE16_HANDLER( copdx_0_w )
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WRITE16_HANDLER( cupsoc_cop_mcu_w )
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{
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COMBINE_DATA(&cop_mcu_ram[offset]);
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@ -1783,17 +1904,72 @@ WRITE16_HANDLER( copdx_0_w )
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break;
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/*layer clearance,but the bootleg doesn't send values,so this function is an
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original left-over.*/
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case (0x478/2):
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/* Odd, this is a video register */
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case (0x470/2): { heatbrl_setgfxbank( cop_mcu_ram[offset] ); break; }
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/* Layer Clearing */
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case (0x478/2): /* clear address */
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{
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/*
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AM_RANGE(0x100800, 0x100fff) AM_READWRITE(SMH_RAM,legionna_background_w) AM_BASE(&legionna_back_data)
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AM_RANGE(0x101000, 0x1017ff) AM_READWRITE(SMH_RAM,legionna_foreground_w) AM_BASE(&legionna_fore_data)
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AM_RANGE(0x101800, 0x101fff) AM_READWRITE(SMH_RAM,legionna_midground_w) AM_BASE(&legionna_mid_data)
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AM_RANGE(0x102000, 0x102fff) AM_READWRITE(SMH_RAM,legionna_text_w) AM_BASE(&legionna_textram)
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*/
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cop_clearfill_address[cop_clearfill_lasttrigger] = data; // << 6 to get actual address
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printf("%06x: COPX set layer clear address to %04x (actual %08x)\n", activecpu_get_pc(), data, data<<6);
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break;
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}
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case (0x47a/2): /* clear length */
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{
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cop_clearfill_length[cop_clearfill_lasttrigger] = data;
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printf("%06x: COPX set layer clear length to %04x (actual %08x)\n", activecpu_get_pc(), data, data<<5);
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break;
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}
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|
||||
case (0x47c/2): /* clear value? */
|
||||
{
|
||||
cop_clearfill_value[cop_clearfill_lasttrigger] = data;
|
||||
printf("%06x: COPX set layer clear value to %04x (actual %08x)\n", activecpu_get_pc(), data, data<<6);
|
||||
break;
|
||||
}
|
||||
|
||||
/* unknown, related to clears? / DMA? */
|
||||
case (0x47e/2):
|
||||
{
|
||||
cop_clearfill_lasttrigger = data;
|
||||
printf("%06x: COPX set layer clear trigger? to %04x\n", activecpu_get_pc(), data);
|
||||
if (data>=0x1ff)
|
||||
{
|
||||
printf("invalid!, >0x1ff\n");
|
||||
cop_clearfill_lasttrigger = 0;
|
||||
}
|
||||
|
||||
break;
|
||||
}
|
||||
|
||||
/* hmm, this would be strange the 6xx range should be video regs?? */
|
||||
case (0x6fc/2):
|
||||
{
|
||||
printf("%06x: COPX execute current layer clear??? %04x\n", activecpu_get_pc(), data);
|
||||
|
||||
// I think the value it writes here must match the other value for anything to happen.. maybe */
|
||||
//if (data!=cop_clearfill_value[cop_clearfill_lasttrigger]) break;
|
||||
if ((cop_clearfill_lasttrigger==0x14) || (cop_clearfill_lasttrigger==0x15)) return;
|
||||
|
||||
/* do the fill */
|
||||
if (cop_clearfill_value[cop_clearfill_lasttrigger]==0x0000)
|
||||
{
|
||||
UINT32 length, address;
|
||||
int i;
|
||||
address = cop_clearfill_address[cop_clearfill_lasttrigger] << 6;
|
||||
length = (cop_clearfill_length[cop_clearfill_lasttrigger]+1) << 5;
|
||||
|
||||
for (i=address;i<address+length;i+=2)
|
||||
{
|
||||
program_write_word(i, 0x0000);
|
||||
}
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
|
||||
/* Trigger Macro Command */
|
||||
case (0x500/2):
|
||||
{
|
||||
|
||||
Loading…
Reference in New Issue
Block a user