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https://github.com/holub/mame
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z80ne: merge driver into a single file
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hap
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@ -1,252 +0,0 @@
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// license:BSD-3-Clause
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// copyright-holders:Roberto Lavarone
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/*****************************************************************************
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*
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* includes/z80ne.h
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*
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* Nuova Elettronica Z80NE
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*
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* http://www.z80ne.com/
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*
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****************************************************************************/
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#ifndef MAME_INCLUDES_Z80NE_H
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#define MAME_INCLUDES_Z80NE_H
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#pragma once
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#include "imagedev/cassette.h"
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#include "imagedev/floppy.h"
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#include "machine/ay31015.h"
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#include "machine/clock.h"
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#include "machine/kr2376.h"
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#include "machine/ram.h"
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#include "machine/wd_fdc.h"
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#include "video/mc6847.h"
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/***************************************************************************
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CONSTANTS
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***************************************************************************/
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#define Z80NE_CPU_SPEED_HZ 1920000 /* 1.92 MHz */
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#define LX383_KEYS 16
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#define LX383_DOWNSAMPLING 16
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#define LX385_TAPE_SAMPLE_FREQ 38400
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/* wave duration threshold */
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enum z80netape_speed
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{
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TAPE_300BPS = 300, /* 300 bps */
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TAPE_600BPS = 600, /* 600 bps */
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TAPE_1200BPS = 1200 /* 1200 bps */
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};
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struct z80ne_cass_data_t {
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struct {
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int length = 0; /* time cassette level is at input.level */
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int level = 0; /* cassette level */
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int bit = 0; /* bit being read */
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} input;
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struct {
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int length = 0; /* time cassette level is at output.level */
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int level = 0; /* cassette level */
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int bit = 0; /* bit to output */
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} output;
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z80netape_speed speed; /* 300 - 600 - 1200 */
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int wave_filter = 0;
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int wave_length = 0;
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int wave_short = 0;
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int wave_long = 0;
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};
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class z80ne_state : public driver_device
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{
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public:
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z80ne_state(const machine_config &mconfig, device_type type, const char *tag)
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: driver_device(mconfig, type, tag),
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m_uart(*this, "uart"),
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m_uart_clock(*this, "uart_clock"),
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m_maincpu(*this, "maincpu"),
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m_cassette1(*this, "cassette"),
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m_cassette2(*this, "cassette2"),
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m_ram(*this, RAM_TAG),
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m_bank1(*this, "bank1"),
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m_bank2(*this, "bank2"),
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m_bank3(*this, "bank3"),
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m_bank4(*this, "bank4"),
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m_io_row0(*this, "ROW0"),
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m_io_row1(*this, "ROW1"),
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m_io_ctrl(*this, "CTRL"),
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m_io_rst(*this, "RST"),
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m_io_lx_385(*this, "LX.385"),
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m_lx383_digits(*this, "digit%u", 0U)
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, m_rom(*this, "maincpu")
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, m_mram(*this, "mainram")
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{ }
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void z80ne(machine_config &config);
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void init_z80ne();
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DECLARE_INPUT_CHANGED_MEMBER(z80ne_reset);
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protected:
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virtual void machine_start() override;
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virtual void machine_reset() override;
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void base_reset();
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void save_state_vars();
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static void floppy_formats(format_registration &fr);
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uint8_t m_lx383_scan_counter = 0;
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uint8_t m_lx383_key[LX383_KEYS]{};
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int m_lx383_downsampler = 0;
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uint8_t m_lx385_ctrl = 0;
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emu_timer *m_cassette_timer = nullptr;
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emu_timer *m_kbd_timer = nullptr;
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z80ne_cass_data_t m_cass_data;
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uint8_t lx383_r();
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void lx383_w(offs_t offset, uint8_t data);
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uint8_t lx385_ctrl_r();
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void lx385_ctrl_w(uint8_t data);
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DECLARE_WRITE_LINE_MEMBER(lx385_uart_tx_clock_w);
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TIMER_CALLBACK_MEMBER(cassette_tc);
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TIMER_CALLBACK_MEMBER(kbd_scan);
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TIMER_CALLBACK_MEMBER(pulse_nmi);
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memory_passthrough_handler m_rom_shadow_tap;
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required_device<ay31015_device> m_uart;
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required_device<clock_device> m_uart_clock;
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required_device<cpu_device> m_maincpu;
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required_device<cassette_image_device> m_cassette1;
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required_device<cassette_image_device> m_cassette2;
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optional_device<ram_device> m_ram;
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optional_memory_bank m_bank1;
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optional_memory_bank m_bank2;
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optional_memory_bank m_bank3;
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optional_memory_bank m_bank4;
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required_ioport m_io_row0;
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required_ioport m_io_row1;
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required_ioport m_io_ctrl;
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required_ioport m_io_rst;
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required_ioport m_io_lx_385;
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output_finder<8> m_lx383_digits;
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required_region_ptr<u8> m_rom;
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optional_shared_ptr<u8> m_mram;
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emu_timer *m_timer_nmi = nullptr;
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cassette_image_device *cassette_device_image();
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private:
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void mem_map(address_map &map);
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void io_map(address_map &map);
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};
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class z80net_state : public z80ne_state
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{
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public:
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z80net_state(const machine_config &mconfig, device_type type, const char *tag)
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: z80ne_state(mconfig, type, tag),
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m_videoram(*this, "videoram"),
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m_vdg(*this, "mc6847"),
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m_lx387_kr2376(*this, "lx387_kr2376"),
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m_io_lx387_brk(*this, "LX387_BRK"),
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m_io_modifiers(*this, "MODIFIERS")
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{
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}
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void lx387(machine_config &config);
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void z80net(machine_config &config);
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DECLARE_INPUT_CHANGED_MEMBER(z80net_nmi);
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protected:
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virtual void machine_reset() override;
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DECLARE_READ_LINE_MEMBER(lx387_shift_r);
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DECLARE_READ_LINE_MEMBER(lx387_control_r);
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uint8_t lx387_data_r();
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uint8_t lx388_mc6847_videoram_r(offs_t offset);
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uint8_t lx388_read_field_sync();
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required_shared_ptr<uint8_t> m_videoram;
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required_device<mc6847_base_device> m_vdg;
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required_device<kr2376_device> m_lx387_kr2376;
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required_ioport m_io_lx387_brk;
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required_ioport m_io_modifiers;
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void reset_lx387();
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void io_map(address_map &map);
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private:
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void mem_map(address_map &map);
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};
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class z80netb_state : public z80net_state
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{
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public:
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z80netb_state(const machine_config &mconfig, device_type type, const char *tag)
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: z80net_state(mconfig, type, tag)
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{
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}
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void z80netb(machine_config &config);
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protected:
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virtual void machine_reset() override;
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private:
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void mem_map(address_map &map);
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};
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class z80netf_state : public z80netb_state
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{
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public:
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z80netf_state(const machine_config &mconfig, device_type type, const char *tag)
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: z80netb_state(mconfig, type, tag),
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m_io_config(*this, "CONFIG"),
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m_floppy(*this, "wd1771:%u", 0U),
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m_wd1771(*this, "wd1771"),
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m_drv_led(*this, "drv%u", 0U)
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{
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}
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void z80netf(machine_config &config);
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private:
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virtual void machine_start() override;
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virtual void machine_reset() override;
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virtual void driver_start() override;
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struct wd17xx_state_t
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{
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int drq = 0;
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int intrq = 0;
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uint8_t drive = 0; /* current drive */
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uint8_t head = 0; /* current head */
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};
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void mem_map(address_map &map);
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void io_map(address_map &map);
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void lx390_motor_w(uint8_t data);
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uint8_t lx390_fdc_r(offs_t offset);
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void lx390_fdc_w(offs_t offset, uint8_t data);
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void reset_lx390_banking();
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required_ioport m_io_config;
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required_device_array<floppy_connector, 4> m_floppy;
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required_device<fd1771_device> m_wd1771;
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wd17xx_state_t m_wd17xx_state;
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output_finder<2> m_drv_led;
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};
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#endif // MAME_INCLUDES_Z80NE_H
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@ -1,694 +0,0 @@
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// license:BSD-3-Clause
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// copyright-holders:Roberto Lavarone
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/***********************************************************************
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machine/z80ne.c
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Functions to emulate general aspects of the machine (RAM, ROM,
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interrupts, I/O ports)
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***********************************************************************/
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/* Core includes */
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#include "emu.h"
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#include "z80ne.h"
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//#define VERBOSE 1
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#include "logmacro.h"
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/* timer to read cassette waveforms */
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cassette_image_device* z80ne_state::cassette_device_image()
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{
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if (m_lx385_ctrl & 0x08)
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return m_cassette2;
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else
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return m_cassette1;
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}
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TIMER_CALLBACK_MEMBER(z80ne_state::cassette_tc)
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{
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uint8_t cass_ws = 0;
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m_cass_data.input.length++;
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cass_ws = ((cassette_device_image())->input() > +0.02) ? 1 : 0;
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if ((cass_ws ^ m_cass_data.input.level) & cass_ws)
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{
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m_cass_data.input.level = cass_ws;
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m_cass_data.input.bit = ((m_cass_data.input.length < m_cass_data.wave_filter) || (m_cass_data.input.length > 0x20)) ? 1 : 0;
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m_cass_data.input.length = 0;
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m_uart->write_si(m_cass_data.input.bit);
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}
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m_cass_data.input.level = cass_ws;
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/* saving a tape - convert the serial stream from the uart */
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m_cass_data.output.length--;
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if (!(m_cass_data.output.length))
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{
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if (m_cass_data.output.level)
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m_cass_data.output.level = 0;
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else
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{
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m_cass_data.output.level=1;
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cass_ws = m_uart->so_r();
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m_cass_data.wave_length = cass_ws ? m_cass_data.wave_short : m_cass_data.wave_long;
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}
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cassette_device_image()->output(m_cass_data.output.level ? -1.0 : +1.0);
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m_cass_data.output.length = m_cass_data.wave_length;
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}
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}
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void z80ne_state::save_state_vars()
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{
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save_item(NAME(m_lx383_scan_counter));
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save_item(NAME(m_lx383_key));
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save_item(NAME(m_lx383_downsampler));
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save_item(NAME(m_lx385_ctrl));
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}
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void z80ne_state::init_z80ne()
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{
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save_state_vars();
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}
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void z80netf_state::driver_start()
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{
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save_state_vars();
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/* first two entries point to rom on reset */
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u8 *r = m_ram->pointer();
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m_bank1->configure_entry(0, r); /* RAM at 0x0000-0x03FF */
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m_bank1->configure_entries(1, 3, m_rom+0x4400, 0x0400); /* ep390, ep1390, ep2390 at 0x0000-0x03FF */
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m_bank1->configure_entry(4, m_rom+0x4000); /* ep382 at 0x0000-0x03FF */
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m_bank1->configure_entry(5, m_rom); /* ep548 at 0x0000-0x03FF */
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m_bank2->configure_entry(0, r+0x0400); /* RAM at 0x0400 */
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m_bank2->configure_entry(1, m_rom+0x0400); /* ep548 at 0x0400-0x3FFF */
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m_bank3->configure_entry(0, r+0x4000); /* RAM at 0x8000 */
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m_bank3->configure_entry(1, m_rom+0x4000); /* ep382 at 0x8000 */
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m_bank4->configure_entry(0, r+0x5000); /* RAM at 0xF000 */
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m_bank4->configure_entries(1, 3, m_rom+0x4400, 0x0400); /* ep390, ep1390, ep2390 at 0xF000 */
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}
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TIMER_CALLBACK_MEMBER(z80ne_state::kbd_scan)
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{
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/*
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* NE555 is connected to a 74LS93 binary counter
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* 74LS93 output:
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* QA-QC: column index for LEDs and keyboard
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* QD: keyboard row select
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*
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* Port F0 input bit assignment:
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* 0 QA bits 0..3 of row counter
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* 1 QB
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* 2 QC
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* 3 QD
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* 4 Control button pressed, active high
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* 5 Always low
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* 6 Always low
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* 7 Selected button pressed, active low
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*
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*
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*/
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uint16_t key_bits;
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uint8_t ctrl; //, rst;
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uint8_t i;
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/* 4-bit counter */
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--m_lx383_scan_counter;
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m_lx383_scan_counter &= 0x0f;
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if ( --m_lx383_downsampler == 0 )
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{
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m_lx383_downsampler = LX383_DOWNSAMPLING;
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key_bits = (m_io_row1->read() << 8) | m_io_row0->read();
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// rst = m_io_rst->read();
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ctrl = m_io_ctrl->read();
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for ( i = 0; i<LX383_KEYS; i++)
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{
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m_lx383_key[i] = ( i | (key_bits & 0x01 ? 0x80 : 0x00) | ~ctrl);
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key_bits >>= 1;
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}
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}
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}
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TIMER_CALLBACK_MEMBER(z80ne_state::pulse_nmi)
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{
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m_maincpu->pulse_input_line(INPUT_LINE_NMI, attotime::zero);
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}
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void z80net_state::reset_lx387()
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{
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m_lx387_kr2376->set_input_pin( kr2376_device::KR2376_DSII, 0);
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m_lx387_kr2376->set_input_pin( kr2376_device::KR2376_PII, 0);
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}
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void z80netf_state::reset_lx390_banking()
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{
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switch (m_io_config->read() & 0x07)
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{
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case 0x01: /* EP382 Hex Monitor */
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if (VERBOSE)
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logerror("reset_lx390_banking: banking ep382\n");
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m_bank1->set_entry(4); /* ep382 at 0x0000 for 3 cycles, then RAM */
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m_bank2->set_entry(0); /* RAM at 0x0400 */
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m_bank3->set_entry(1); /* ep382 at 0x8000 */
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m_bank4->set_entry(0); /* RAM at 0xF000 */
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break;
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case 0x02: /* EP548 16k BASIC */
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if (VERBOSE)
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logerror("reset_lx390_banking: banking ep548\n");
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m_bank1->set_entry(5); /* ep548 at 0x0000-0x03FF */
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m_bank2->set_entry(1); /* ep548 at 0x0400-0x3FFF */
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m_bank3->set_entry(0); /* RAM at 0x8000 */
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m_bank4->set_entry(0); /* RAM at 0xF000 */
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break;
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case 0x03: /* EP390 Boot Loader for 5.5k floppy BASIC */
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if (VERBOSE)
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logerror("reset_lx390_banking: banking ep390\n");
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m_bank1->set_entry(1); /* ep390 at 0x0000-0 x03FF for 3 cycles, then RAM */
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m_bank2->set_entry(0); /* RAM at 0x0400-0x3FFF */
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m_bank3->set_entry(0); /* RAM at 0x8000 */
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m_bank4->set_entry(1); /* ep390 at 0xF000 */
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break;
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case 0x04: /* EP1390 Boot Loader for NE DOS 1.0/1.5 */
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if (VERBOSE)
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logerror("reset_lx390_banking: banking ep1390\n");
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m_bank1->set_entry(2); /* ep1390 at 0x0000-0x03FF for 3 cycles, then RAM */
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m_bank2->set_entry(0); /* RAM at 0x0400-0x3FFF */
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m_bank3->set_entry(0); /* RAM at 0x8000 */
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m_bank4->set_entry(2); /* ep1390 at 0xF000 */
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break;
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case 0x05: /* EP2390 Boot Loader for NE DOS G.1 */
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if (VERBOSE)
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logerror("reset_lx390_banking: banking ep2390\n");
|
||||
m_bank1->set_entry(3); /* ep2390 at 0x0000-0x03FF for 3 cycles, then RAM */
|
||||
m_bank2->set_entry(0); /* RAM at 0x0400-0x3FFF */
|
||||
m_bank3->set_entry(0); /* RAM at 0x8000 */
|
||||
m_bank4->set_entry(3); /* ep2390 at 0xF000 */
|
||||
break;
|
||||
}
|
||||
|
||||
/* TODO: in real hardware the ENH bus line is pulled down
|
||||
* until a I/O read is performed on a address with A0 address bit low and A1 or A2 address bit high
|
||||
*/
|
||||
}
|
||||
|
||||
void z80ne_state::base_reset()
|
||||
{
|
||||
for (int i = 0; i < LX383_KEYS; i++)
|
||||
m_lx383_key[i] = 0xf0 | i;
|
||||
m_lx383_scan_counter = 0x0f;
|
||||
m_lx383_downsampler = LX383_DOWNSAMPLING;
|
||||
|
||||
/* Initialize cassette interface */
|
||||
switch(m_io_lx_385->read() & 0x07)
|
||||
{
|
||||
case 0x01:
|
||||
m_cass_data.speed = TAPE_300BPS;
|
||||
m_cass_data.wave_filter = LX385_TAPE_SAMPLE_FREQ / 1600;
|
||||
m_cass_data.wave_short = LX385_TAPE_SAMPLE_FREQ / (2400 * 2);
|
||||
m_cass_data.wave_long = LX385_TAPE_SAMPLE_FREQ / (1200 * 2);
|
||||
break;
|
||||
case 0x02:
|
||||
m_cass_data.speed = TAPE_600BPS;
|
||||
m_cass_data.wave_filter = LX385_TAPE_SAMPLE_FREQ / 3200;
|
||||
m_cass_data.wave_short = LX385_TAPE_SAMPLE_FREQ / (4800 * 2);
|
||||
m_cass_data.wave_long = LX385_TAPE_SAMPLE_FREQ / (2400 * 2);
|
||||
break;
|
||||
case 0x04:
|
||||
m_cass_data.speed = TAPE_1200BPS;
|
||||
m_cass_data.wave_filter = LX385_TAPE_SAMPLE_FREQ / 6400;
|
||||
m_cass_data.wave_short = LX385_TAPE_SAMPLE_FREQ / (9600 * 2);
|
||||
m_cass_data.wave_long = LX385_TAPE_SAMPLE_FREQ / (4800 * 2);
|
||||
}
|
||||
m_cass_data.wave_length = m_cass_data.wave_short;
|
||||
m_cass_data.output.length = m_cass_data.wave_length;
|
||||
m_cass_data.output.level = 1;
|
||||
m_cass_data.input.length = 0;
|
||||
m_cass_data.input.bit = 1;
|
||||
|
||||
m_uart->write_cs(0);
|
||||
m_uart->write_nb1(1);
|
||||
m_uart->write_nb2(1);
|
||||
m_uart->write_tsb(1);
|
||||
m_uart->write_eps(1);
|
||||
m_uart->write_np(m_io_lx_385->read() & 0x80 ? 1 : 0);
|
||||
m_uart->write_cs(1);
|
||||
m_uart_clock->set_unscaled_clock(m_cass_data.speed * 16);
|
||||
|
||||
lx385_ctrl_w(0);
|
||||
}
|
||||
|
||||
void z80ne_state::machine_reset()
|
||||
{
|
||||
base_reset();
|
||||
|
||||
address_space &program = m_maincpu->space(AS_PROGRAM);
|
||||
program.install_rom(0x0000, 0x03ff, m_rom); // do it here for F3
|
||||
m_rom_shadow_tap.remove();
|
||||
m_rom_shadow_tap = program.install_read_tap(
|
||||
0x8000, 0x83ff,
|
||||
"rom_shadow_r",
|
||||
[this] (offs_t offset, u8 &data, u8 mem_mask)
|
||||
{
|
||||
if (!machine().side_effects_disabled())
|
||||
{
|
||||
// delete this tap
|
||||
m_rom_shadow_tap.remove();
|
||||
|
||||
// reinstall RAM over the ROM shadow
|
||||
m_maincpu->space(AS_PROGRAM).install_ram(0x0000, 0x03ff, m_mram);
|
||||
}
|
||||
},
|
||||
&m_rom_shadow_tap);
|
||||
}
|
||||
|
||||
void z80net_state::machine_reset()
|
||||
{
|
||||
reset_lx387();
|
||||
z80ne_state::machine_reset();
|
||||
}
|
||||
|
||||
void z80netb_state::machine_reset()
|
||||
{
|
||||
base_reset();
|
||||
reset_lx387();
|
||||
}
|
||||
|
||||
void z80netf_state::machine_reset()
|
||||
{
|
||||
reset_lx390_banking();
|
||||
base_reset();
|
||||
reset_lx387();
|
||||
|
||||
// basic roms are exempt from memory tap
|
||||
if ((m_io_config->read() & 0x07) != 2)
|
||||
{
|
||||
address_space &program = m_maincpu->space(AS_PROGRAM);
|
||||
m_rom_shadow_tap.remove();
|
||||
m_rom_shadow_tap = program.install_read_tap(
|
||||
0x8000, 0xf3ff,
|
||||
"rom_shadow_r",
|
||||
[this] (offs_t offset, u8 &data, u8 mem_mask)
|
||||
{
|
||||
if (!machine().side_effects_disabled())
|
||||
{
|
||||
// delete this tap
|
||||
m_rom_shadow_tap.remove();
|
||||
|
||||
// reinstall RAM over the ROM shadow
|
||||
m_bank1->set_entry(0);
|
||||
}
|
||||
},
|
||||
&m_rom_shadow_tap);
|
||||
}
|
||||
}
|
||||
|
||||
INPUT_CHANGED_MEMBER(z80ne_state::z80ne_reset)
|
||||
{
|
||||
uint8_t rst = m_io_rst->read();
|
||||
|
||||
if ( ! BIT(rst, 0))
|
||||
machine().schedule_soft_reset();
|
||||
}
|
||||
|
||||
INPUT_CHANGED_MEMBER(z80net_state::z80net_nmi)
|
||||
{
|
||||
uint8_t nmi = m_io_lx387_brk->read();
|
||||
|
||||
if ( ! BIT(nmi, 0))
|
||||
m_maincpu->pulse_input_line(INPUT_LINE_NMI, attotime::zero);
|
||||
}
|
||||
|
||||
void z80ne_state::machine_start()
|
||||
{
|
||||
m_timer_nmi = timer_alloc(FUNC(z80ne_state::pulse_nmi), this);
|
||||
|
||||
m_lx383_digits.resolve();
|
||||
|
||||
m_lx385_ctrl = 0x1f;
|
||||
m_cassette_timer = timer_alloc(FUNC(z80ne_state::cassette_tc), this);
|
||||
m_kbd_timer = timer_alloc(FUNC(z80ne_state::kbd_scan), this);
|
||||
m_kbd_timer->adjust(attotime::from_hz(1000), 0, attotime::from_hz(1000));
|
||||
}
|
||||
|
||||
void z80netf_state::machine_start()
|
||||
{
|
||||
z80ne_state::machine_start();
|
||||
m_drv_led.resolve();
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
Drivers
|
||||
******************************************************************************/
|
||||
|
||||
/* LX.383 - LX.384 HEX keyboard and display */
|
||||
uint8_t z80ne_state::lx383_r()
|
||||
{
|
||||
/*
|
||||
* Keyboard scanning
|
||||
*
|
||||
* IC14 NE555 astable oscillator
|
||||
* IC13 74LS93 binary counter
|
||||
* IC5 74LS240 tri-state buffer
|
||||
*
|
||||
* l'oscillatore NE555 alimenta il clock del contatore 74LS93
|
||||
* D0 - Q(A) --\
|
||||
* D1 - Q(B) |-- column
|
||||
* D2 - Q(C) --/
|
||||
* D3 - Q(D) row
|
||||
* D4 - CTRL
|
||||
* D5 - 0
|
||||
* D6 - 0
|
||||
* D7 - ~KEY Pressed
|
||||
*/
|
||||
return m_lx383_key[m_lx383_scan_counter];
|
||||
}
|
||||
|
||||
void z80ne_state::lx383_w(offs_t offset, uint8_t data)
|
||||
{
|
||||
/*
|
||||
* First 8 locations (F0-F7) are mapped to a dual-port 8-byte RAM
|
||||
* The 1KHz NE-555 astable oscillator circuit drive
|
||||
* a 4-bit 74LS93 binary counter.
|
||||
* The 3 least significant bits of the counter are connected
|
||||
* both to the read address of the dual-port ram and to
|
||||
* a 74LS156 3 to 8 binary decoder driving the cathode
|
||||
* of 8 7-segments LEDS.
|
||||
* The data output of the dual-port ram drive the anodes
|
||||
* of the LEDS through 74LS07 buffers.
|
||||
* LED segments - dual-port RAM bit:
|
||||
* A 0x01
|
||||
* B 0x02
|
||||
* C 0x04
|
||||
* D 0x08
|
||||
* E 0x10
|
||||
* F 0x20
|
||||
* G 0x40
|
||||
* P 0x80 (represented by DP in original schematics)
|
||||
*
|
||||
* A write in the range F0-FF starts a 74LS90 counter
|
||||
* that trigger the NMI line of the CPU after 2 instruction
|
||||
* fetch cycles for single step execution.
|
||||
*/
|
||||
|
||||
if ( offset < 8 )
|
||||
m_lx383_digits[offset] = data ^ 0xff;
|
||||
else
|
||||
{
|
||||
// after writing to port 0xF8 and the first ~M1 cycles strike a NMI for single step execution
|
||||
m_timer_nmi->adjust(m_maincpu->cycles_to_attotime(1));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/* LX.385 Cassette tape interface */
|
||||
/*
|
||||
* NE555 is connected to a 74LS93 binary counter
|
||||
* 74LS93 output:
|
||||
* QA-QC: column index for LEDs and keyboard
|
||||
* QD: keyboard row select
|
||||
*
|
||||
* Port EE: UART Data Read/Write
|
||||
* Port EF: Status/Control
|
||||
* read, UART status bits read
|
||||
* 0 OR Overrun
|
||||
* 1 FE Framing Error
|
||||
* 2 PE Parity Error
|
||||
* 3 TBMT Transmitter Buffer Empty
|
||||
* 4 DAV Data Available
|
||||
* 5 EOC End Of Character
|
||||
* 6 1
|
||||
* 7 1
|
||||
* write, UART control bits / Tape Unit select / Modulation control
|
||||
* 0 bit1=0, bit0=0 UART Reset pulse
|
||||
* 1 bit1=0, bit0=1 UART RDAV (Reset Data Available) pulse
|
||||
* 2 Tape modulation enable
|
||||
* 3 *TAPEA Enable (active low) (at reset: low)
|
||||
* 4 *TAPEB Enable (active low) (at reset: low)
|
||||
* Cassette is connected to the uart data input and output via the cassette
|
||||
* interface hardware.
|
||||
*
|
||||
* The cassette interface hardware converts square-wave pulses into bits which the uart receives.
|
||||
*
|
||||
* 1. the cassette format: "frequency shift" is converted
|
||||
into the uart data format "non-return to zero"
|
||||
|
||||
2. on cassette a 1 data bit is stored as 8 2400 Hz pulses
|
||||
and a 0 data bit as 4 1200 Hz pulses
|
||||
- At 1200 baud, a logic 1 is 1 cycle of 1200 Hz and a logic 0 is 1/2 cycle of 600 Hz.
|
||||
- At 300 baud, a logic 1 is 8 cycles of 2400 Hz and a logic 0 is 4 cycles of 1200 Hz.
|
||||
|
||||
Attenuation is applied to the signal and the square wave edges are rounded.
|
||||
|
||||
A manchester encoder is used. A flip-flop synchronises input
|
||||
data on the positive-edge of the clock pulse.
|
||||
|
||||
The UART is a RCA CDP1854 CMOS device with pin 2 jumpered to GND to select the
|
||||
AY-3-1015 compatibility mode. The jumper at P4 can be switched to place 12 V on
|
||||
pin 2 for an old PMOS UART.
|
||||
*
|
||||
*/
|
||||
uint8_t z80ne_state::lx385_ctrl_r()
|
||||
{
|
||||
/* set unused bits high */
|
||||
uint8_t data = 0xc0;
|
||||
|
||||
m_uart->write_swe(0);
|
||||
data |= (m_uart->or_r( ) ? 0x01 : 0);
|
||||
data |= (m_uart->fe_r( ) ? 0x02 : 0);
|
||||
data |= (m_uart->pe_r( ) ? 0x04 : 0);
|
||||
data |= (m_uart->tbmt_r() ? 0x08 : 0);
|
||||
data |= (m_uart->dav_r( ) ? 0x10 : 0);
|
||||
data |= (m_uart->eoc_r( ) ? 0x20 : 0);
|
||||
m_uart->write_swe(1);
|
||||
|
||||
return data;
|
||||
}
|
||||
|
||||
#define LX385_CASSETTE_MOTOR_MASK ((1<<3)|(1<<4))
|
||||
|
||||
void z80ne_state::lx385_ctrl_w(uint8_t data)
|
||||
{
|
||||
/* Translate data to control signals
|
||||
* 0 bit1=0, bit0=0 UART Reset pulse
|
||||
* 1 bit1=0, bit0=1 UART RDAV (Reset Data Available) pulse
|
||||
* 2 UART Tx Clock Enable (active high)
|
||||
* 3 *TAPEA Enable (active low) (at reset: low)
|
||||
* 4 *TAPEB Enable (active low) (at reset: low)
|
||||
*/
|
||||
uint8_t uart_reset, uart_rdav;
|
||||
uint8_t motor_a, motor_b;
|
||||
uint8_t changed_bits = (m_lx385_ctrl ^ data) & 0x1C;
|
||||
m_lx385_ctrl = data;
|
||||
|
||||
uart_reset = ((data & 0x03) == 0x00);
|
||||
uart_rdav = ((data & 0x03) == 0x01);
|
||||
motor_a = ((data & 0x08) == 0x00);
|
||||
motor_b = ((data & 0x10) == 0x00);
|
||||
|
||||
/* UART Reset and RDAV */
|
||||
if (uart_reset)
|
||||
{
|
||||
m_uart->write_xr(1);
|
||||
m_uart->write_xr(0);
|
||||
}
|
||||
|
||||
if (uart_rdav)
|
||||
{
|
||||
m_uart->write_rdav(1);
|
||||
m_uart->write_rdav(0);
|
||||
}
|
||||
|
||||
if (!changed_bits) return;
|
||||
|
||||
/* motors */
|
||||
if(changed_bits & 0x18)
|
||||
{
|
||||
m_cassette1->change_state(
|
||||
(motor_a) ? CASSETTE_MOTOR_ENABLED : CASSETTE_MOTOR_DISABLED,CASSETTE_MASK_MOTOR);
|
||||
|
||||
m_cassette2->change_state(
|
||||
(motor_b) ? CASSETTE_MOTOR_ENABLED : CASSETTE_MOTOR_DISABLED,CASSETTE_MASK_MOTOR);
|
||||
|
||||
if (motor_a || motor_b)
|
||||
m_cassette_timer->adjust(attotime::zero, 0, attotime::from_hz(LX385_TAPE_SAMPLE_FREQ));
|
||||
else
|
||||
m_cassette_timer->adjust(attotime::zero);
|
||||
}
|
||||
}
|
||||
|
||||
WRITE_LINE_MEMBER(z80ne_state::lx385_uart_tx_clock_w)
|
||||
{
|
||||
if (BIT(m_lx385_ctrl, 2))
|
||||
m_uart->write_tcp(state);
|
||||
}
|
||||
|
||||
READ_LINE_MEMBER(z80net_state::lx387_shift_r)
|
||||
{
|
||||
return BIT(m_io_modifiers->read(), 0) || BIT(m_io_modifiers->read(), 2);
|
||||
}
|
||||
|
||||
READ_LINE_MEMBER(z80net_state::lx387_control_r)
|
||||
{
|
||||
return BIT(m_io_modifiers->read(), 1);
|
||||
}
|
||||
|
||||
uint8_t z80net_state::lx388_mc6847_videoram_r(offs_t offset)
|
||||
{
|
||||
if (offset == ~0) return 0xff;
|
||||
|
||||
int d6 = BIT(m_videoram[offset], 6);
|
||||
int d7 = BIT(m_videoram[offset], 7);
|
||||
|
||||
m_vdg->inv_w(d6 && d7);
|
||||
m_vdg->as_w(!d6 && d7);
|
||||
m_vdg->intext_w(!d6 && d7);
|
||||
|
||||
return m_videoram[offset];
|
||||
}
|
||||
|
||||
uint8_t z80net_state::lx387_data_r()
|
||||
{
|
||||
uint8_t data = m_lx387_kr2376->data_r() & 0x7f;
|
||||
data |= m_lx387_kr2376->get_output_pin(kr2376_device::KR2376_SO) << 7;
|
||||
return data;
|
||||
}
|
||||
|
||||
uint8_t z80net_state::lx388_read_field_sync()
|
||||
{
|
||||
return m_vdg->fs_r() << 7;
|
||||
}
|
||||
|
||||
/*
|
||||
* DRQ INTRQ IC9B.10 IC8B.*Q
|
||||
* 0 0 1 0
|
||||
* 0 1 0 x
|
||||
* 1 0 0 x
|
||||
* 1 1 0 x
|
||||
*
|
||||
*/
|
||||
|
||||
void z80netf_state::lx390_motor_w(uint8_t data)
|
||||
{
|
||||
/* Selection of drive and parameters
|
||||
A write also causes the selected drive motor to turn on for about 3 seconds.
|
||||
When the motor turns off, the drive is deselected.
|
||||
d7 Unused (trs80: 1=MFM, 0=FM)
|
||||
d6 (trs80: 1=Wait)
|
||||
d5 0=Side 0, 1=Side 1 (trs80: 1=Write Precompensation enabled)
|
||||
d4 Unused (trs80: 0=Side 0, 1=Side 1)
|
||||
d3 1=select drive 3
|
||||
d2 1=select drive 2
|
||||
d1 1=select drive 1
|
||||
d0 1=select drive 0 */
|
||||
|
||||
floppy_image_device *floppy = nullptr;
|
||||
|
||||
for (u8 f = 0; f < 4; f++)
|
||||
if (BIT(data, f))
|
||||
floppy = m_floppy[f]->get_device();
|
||||
|
||||
m_wd1771->set_floppy(floppy);
|
||||
|
||||
if (floppy)
|
||||
{
|
||||
floppy->ss_w(BIT(data, 5));
|
||||
floppy->mon_w(0);
|
||||
}
|
||||
|
||||
m_wd17xx_state.head = (data & 32) ? 1 : 0;
|
||||
m_wd17xx_state.drive = data & 0x0F;
|
||||
|
||||
/* no drive selected, turn off all leds */
|
||||
if (!m_wd17xx_state.drive)
|
||||
{
|
||||
m_drv_led[0] = 0;
|
||||
m_drv_led[1] = 0;
|
||||
}
|
||||
}
|
||||
|
||||
uint8_t z80netf_state::lx390_fdc_r(offs_t offset)
|
||||
{
|
||||
uint8_t d;
|
||||
|
||||
switch(offset)
|
||||
{
|
||||
case 0:
|
||||
d = m_wd1771->status_r() ^ 0xff;
|
||||
LOG("lx390_fdc_r, WD17xx status: %02x\n", d);
|
||||
break;
|
||||
case 1:
|
||||
d = m_wd1771->track_r() ^ 0xff;
|
||||
LOG("lx390_fdc_r, WD17xx track: %02x\n", d);
|
||||
break;
|
||||
case 2:
|
||||
d = m_wd1771->sector_r() ^ 0xff;
|
||||
LOG("lx390_fdc_r, WD17xx sector: %02x\n", d);
|
||||
break;
|
||||
case 3:
|
||||
d = m_wd1771->data_r() ^ 0xff;
|
||||
LOG("lx390_fdc_r, WD17xx data3: %02x\n", d);
|
||||
break;
|
||||
case 6:
|
||||
d = 0xff;
|
||||
m_bank1->set_entry(0);
|
||||
break;
|
||||
case 7:
|
||||
d = m_wd1771->data_r() ^ 0xff;
|
||||
LOG("lx390_fdc_r, WD17xx data7, force: %02x\n", d);
|
||||
break;
|
||||
default:
|
||||
d = 0x00;
|
||||
}
|
||||
return d;
|
||||
}
|
||||
|
||||
void z80netf_state::lx390_fdc_w(offs_t offset, uint8_t data)
|
||||
{
|
||||
uint8_t d = data;
|
||||
switch(offset)
|
||||
{
|
||||
case 0:
|
||||
LOG("lx390_fdc_w, WD17xx command: %02x\n", d);
|
||||
m_wd1771->cmd_w(d ^ 0xff);
|
||||
if (m_wd17xx_state.drive & 1)
|
||||
m_drv_led[0] = 2;
|
||||
else if (m_wd17xx_state.drive & 2)
|
||||
m_drv_led[1] = 2;
|
||||
break;
|
||||
case 1:
|
||||
LOG("lx390_fdc_w, WD17xx track: %02x\n", d);
|
||||
m_wd1771->track_w(d ^ 0xff);
|
||||
break;
|
||||
case 2:
|
||||
LOG("lx390_fdc_w, WD17xx sector: %02x\n", d);
|
||||
m_wd1771->sector_w(d ^ 0xff);
|
||||
break;
|
||||
case 3:
|
||||
m_wd1771->data_w(d ^ 0xff);
|
||||
LOG("lx390_fdc_w, WD17xx data3: %02x\n", d);
|
||||
break;
|
||||
case 6:
|
||||
LOG("lx390_fdc_w, motor_w: %02x\n", d);
|
||||
lx390_motor_w(d);
|
||||
break;
|
||||
case 7:
|
||||
LOG("lx390_fdc_w, WD17xx data7, force: %02x\n", d);
|
||||
m_wd1771->data_w(d ^ 0xff);
|
||||
break;
|
||||
}
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user