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https://github.com/holub/mame
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arm7: Flesh out ARM946ES, add movable DTCM and ITCM support. [R. Belmont]
This commit is contained in:
arbee
parent
86366508b4
commit
c4b79a2a08
@ -149,12 +149,23 @@ arm920t_cpu_device::arm920t_cpu_device(const machine_config &mconfig, const char
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arm946es_cpu_device::arm946es_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
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: arm9_cpu_device(mconfig, ARM946ES, tag, owner, clock, 5, ARCHFLAG_T | ARCHFLAG_E, ENDIANNESS_LITTLE)
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: arm9_cpu_device(mconfig, ARM946ES, tag, owner, clock, 5, ARCHFLAG_T | ARCHFLAG_E, ENDIANNESS_LITTLE),
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cp15_control(0x78)
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{
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m_copro_id = ARM9_COPRO_ID_MFR_ARM
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| ARM9_COPRO_ID_ARCH_V5TE
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| ARM9_COPRO_ID_PART_ARM946
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| ARM9_COPRO_ID_STEP_ARM946_A0;
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memset(ITCM, 0, 0x8000);
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memset(DTCM, 0, 0x4000);
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cp15_itcm_base = 0xffffffff;
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cp15_itcm_size = 0;
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cp15_itcm_end = 0;
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cp15_dtcm_base = 0xffffffff;
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cp15_dtcm_size = 0;
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cp15_dtcm_end = 0;
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}
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pxa255_cpu_device::pxa255_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
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@ -1231,6 +1242,291 @@ WRITE32_MEMBER( arm7_cpu_device::arm7_rt_w_callback )
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}
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}
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READ32_MEMBER( arm946es_cpu_device::arm7_rt_r_callback )
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{
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uint32_t opcode = offset;
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uint8_t cReg = ( opcode & INSN_COPRO_CREG ) >> INSN_COPRO_CREG_SHIFT;
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uint8_t op2 = ( opcode & INSN_COPRO_OP2 ) >> INSN_COPRO_OP2_SHIFT;
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uint8_t op3 = opcode & INSN_COPRO_OP3;
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uint8_t cpnum = (opcode & INSN_COPRO_CPNUM) >> INSN_COPRO_CPNUM_SHIFT;
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uint32_t data = 0;
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//printf("arm7946: read cpnum %d cReg %d op2 %d op3 %d (%x)\n", cpnum, cReg, op2, op3, opcode);
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if (cpnum == 15)
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{
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switch( cReg )
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{
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case 0:
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switch (op2)
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{
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case 0: // chip ID
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data = 0x41059461;
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break;
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case 1: // cache ID
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data = 0x0f0d2112;
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break;
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case 2: // TCM size
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data = (6 << 6) || (5 << 18);
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break;
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}
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break;
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case 1:
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return cp15_control;
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break;
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case 9:
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if (op3 == 1)
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{
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if (op2 == 0)
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{
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return cp15_dtcm_reg;
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}
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else
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{
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return cp15_itcm_reg;
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}
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}
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break;
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}
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}
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return data;
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}
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WRITE32_MEMBER( arm946es_cpu_device::arm7_rt_w_callback )
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{
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uint32_t opcode = offset;
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uint8_t cReg = ( opcode & INSN_COPRO_CREG ) >> INSN_COPRO_CREG_SHIFT;
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uint8_t op2 = ( opcode & INSN_COPRO_OP2 ) >> INSN_COPRO_OP2_SHIFT;
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uint8_t op3 = opcode & INSN_COPRO_OP3;
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uint8_t cpnum = (opcode & INSN_COPRO_CPNUM) >> INSN_COPRO_CPNUM_SHIFT;
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// printf("arm7946: copro %d write %x to cReg %d op2 %d op3 %d (mask %08x)\n", cpnum, data, cReg, op2, op3, mem_mask);
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if (cpnum == 15)
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{
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switch (cReg)
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{
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case 1: // control
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cp15_control = data;
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RefreshDTCM();
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RefreshITCM();
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break;
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case 2: // Protection Unit cacheability bits
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break;
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case 3: // write bufferability bits for PU
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break;
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case 5: // protection unit region controls
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break;
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case 6: // protection unit region controls 2
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break;
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case 7: // cache commands
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break;
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case 9: // cache lockdown & TCM controls
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if (op3 == 1)
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{
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if (op2 == 0)
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{
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cp15_dtcm_reg = data;
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RefreshDTCM();
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}
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else if (op2 == 1)
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{
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cp15_itcm_reg = data;
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RefreshITCM();
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}
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}
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break;
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}
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}
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}
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void arm946es_cpu_device::RefreshDTCM()
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{
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if (cp15_control & (1<<16))
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{
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cp15_dtcm_base = (cp15_dtcm_reg & ~0xfff);
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cp15_dtcm_size = 512 << ((cp15_dtcm_reg & 0x3f) >> 1);
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cp15_dtcm_end = cp15_dtcm_base + cp15_dtcm_size;
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//printf("DTCM enabled: base %08x size %x\n", cp15_dtcm_base, cp15_dtcm_size);
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}
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else
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{
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cp15_dtcm_base = 0xffffffff;
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cp15_dtcm_size = cp15_dtcm_end = 0;
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}
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}
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void arm946es_cpu_device::RefreshITCM()
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{
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if (cp15_control & (1<<18))
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{
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cp15_itcm_base = 0; //(cp15_itcm_reg & ~0xfff);
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cp15_itcm_size = 512 << ((cp15_itcm_reg & 0x3f) >> 1);
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cp15_itcm_end = cp15_itcm_base + cp15_itcm_size;
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//printf("ITCM enabled: base %08x size %x\n", cp15_dtcm_base, cp15_dtcm_size);
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}
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else
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{
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cp15_itcm_base = 0xffffffff;
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cp15_itcm_size = cp15_itcm_end = 0;
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}
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}
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void arm946es_cpu_device::arm7_cpu_write32(uint32_t addr, uint32_t data)
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{
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addr &= ~3;
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if ((addr >= cp15_itcm_base) && (addr <= cp15_itcm_end))
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{
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uint32_t *wp = (uint32_t *)&ITCM[addr&0x7fff];
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*wp = data;
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return;
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}
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else if ((addr >= cp15_dtcm_base) && (addr <= cp15_dtcm_end))
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{
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uint32_t *wp = (uint32_t *)&DTCM[addr&0x3fff];
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*wp = data;
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return;
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}
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m_program->write_dword(addr, data);
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}
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void arm946es_cpu_device::arm7_cpu_write16(uint32_t addr, uint16_t data)
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{
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addr &= ~1;
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if ((addr >= cp15_itcm_base) && (addr <= cp15_itcm_end))
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{
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uint16_t *wp = (uint16_t *)&ITCM[addr&0x7fff];
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*wp = data;
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return;
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}
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else if ((addr >= cp15_dtcm_base) && (addr <= cp15_dtcm_end))
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{
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uint16_t *wp = (uint16_t *)&DTCM[addr&0x3fff];
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*wp = data;
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return;
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}
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m_program->write_word(addr, data);
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}
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void arm946es_cpu_device::arm7_cpu_write8(uint32_t addr, uint8_t data)
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{
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if ((addr >= cp15_itcm_base) && (addr <= cp15_itcm_end))
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{
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ITCM[addr&0x7fff] = data;
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return;
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}
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else if ((addr >= cp15_dtcm_base) && (addr <= cp15_dtcm_end))
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{
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DTCM[addr&0x3fff] = data;
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return;
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}
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m_program->write_byte(addr, data);
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}
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uint32_t arm946es_cpu_device::arm7_cpu_read32(uint32_t addr)
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{
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uint32_t result;
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if ((addr >= cp15_itcm_base) && (addr <= cp15_itcm_end))
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{
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if (addr & 3)
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{
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uint32_t *wp = (uint32_t *)&ITCM[(addr & ~3)&0x7fff];
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result = *wp;
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result = (result >> (8 * (addr & 3))) | (result << (32 - (8 * (addr & 3))));
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}
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else
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{
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uint32_t *wp = (uint32_t *)&ITCM[addr&0x7fff];
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result = *wp;
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}
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}
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else if ((addr >= cp15_dtcm_base) && (addr <= cp15_dtcm_end))
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{
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if (addr & 3)
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{
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uint32_t *wp = (uint32_t *)&DTCM[(addr & ~3)&0x3fff];
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result = *wp;
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result = (result >> (8 * (addr & 3))) | (result << (32 - (8 * (addr & 3))));
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}
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else
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{
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uint32_t *wp = (uint32_t *)&DTCM[addr&0x3fff];
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result = *wp;
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}
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}
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else
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{
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if (addr & 3)
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{
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result = m_program->read_dword(addr & ~3);
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result = (result >> (8 * (addr & 3))) | (result << (32 - (8 * (addr & 3))));
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}
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else
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{
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result = m_program->read_dword(addr);
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}
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}
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return result;
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}
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uint16_t arm946es_cpu_device::arm7_cpu_read16(uint32_t addr)
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{
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uint16_t result;
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if ((addr >= cp15_itcm_base) && (addr <= cp15_itcm_end))
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{
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uint16_t *wp = (uint16_t *)&ITCM[(addr & ~1)&0x7fff];
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result = *wp;
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}
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else if ((addr >= cp15_dtcm_base) && (addr <= cp15_dtcm_end))
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{
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uint16_t *wp = (uint16_t *)&DTCM[(addr & ~1)&0x3fff];
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result = *wp;
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}
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else
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{
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result = m_program->read_word(addr & ~1);
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}
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if (addr & 1)
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{
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result = ((result >> 8) & 0xff) | ((result & 0xff) << 8);
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}
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return result;
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}
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uint8_t arm946es_cpu_device::arm7_cpu_read8(uint32_t addr)
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{
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if ((addr >= cp15_itcm_base) && (addr <= cp15_itcm_end))
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{
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return ITCM[addr & 0x7fff];
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}
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else if ((addr >= cp15_dtcm_base) && (addr <= cp15_dtcm_end))
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{
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return DTCM[addr & 0x3fff];
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}
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// Handle through normal 8 bit handler (for 32 bit cpu)
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return m_program->read_byte(addr);
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}
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WRITE32_MEMBER(igs036_cpu_device::arm7_rt_w_callback)
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{
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arm7_cpu_device::arm7_rt_w_callback(space, offset, data, mem_mask);
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@ -231,16 +231,16 @@ protected:
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int detect_fault(int desc_lvl1, int ap, int flags);
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void arm7_check_irq_state();
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void update_irq_state();
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void arm7_cpu_write32(uint32_t addr, uint32_t data);
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void arm7_cpu_write16(uint32_t addr, uint16_t data);
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void arm7_cpu_write8(uint32_t addr, uint8_t data);
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uint32_t arm7_cpu_read32(uint32_t addr);
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uint16_t arm7_cpu_read16(uint32_t addr);
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uint8_t arm7_cpu_read8(uint32_t addr);
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virtual void arm7_cpu_write32(uint32_t addr, uint32_t data);
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virtual void arm7_cpu_write16(uint32_t addr, uint16_t data);
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virtual void arm7_cpu_write8(uint32_t addr, uint8_t data);
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virtual uint32_t arm7_cpu_read32(uint32_t addr);
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virtual uint16_t arm7_cpu_read16(uint32_t addr);
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virtual uint8_t arm7_cpu_read8(uint32_t addr);
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// Coprocessor support
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DECLARE_WRITE32_MEMBER( arm7_do_callback );
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DECLARE_READ32_MEMBER( arm7_rt_r_callback );
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virtual DECLARE_READ32_MEMBER( arm7_rt_r_callback );
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virtual DECLARE_WRITE32_MEMBER( arm7_rt_w_callback );
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void arm7_dt_r_callback(uint32_t insn, uint32_t *prn);
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void arm7_dt_w_callback(uint32_t insn, uint32_t *prn);
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@ -613,6 +613,25 @@ class arm946es_cpu_device : public arm9_cpu_device
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public:
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// construction/destruction
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arm946es_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
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// 946E-S has Protection Unit instead of ARM MMU so CP15 is quite different
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virtual DECLARE_READ32_MEMBER( arm7_rt_r_callback ) override;
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virtual DECLARE_WRITE32_MEMBER( arm7_rt_w_callback ) override;
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virtual void arm7_cpu_write32(uint32_t addr, uint32_t data) override;
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virtual void arm7_cpu_write16(uint32_t addr, uint16_t data) override;
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virtual void arm7_cpu_write8(uint32_t addr, uint8_t data) override;
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virtual uint32_t arm7_cpu_read32(uint32_t addr) override;
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virtual uint16_t arm7_cpu_read16(uint32_t addr) override;
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virtual uint8_t arm7_cpu_read8(uint32_t addr) override;
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private:
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uint32_t cp15_control, cp15_itcm_base, cp15_dtcm_base, cp15_itcm_size, cp15_dtcm_size;
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uint32_t cp15_itcm_end, cp15_dtcm_end, cp15_itcm_reg, cp15_dtcm_reg;
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uint8_t ITCM[0x8000], DTCM[0x4000];
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void RefreshITCM();
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void RefreshDTCM();
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};
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