mirror of
https://github.com/holub/mame
synced 2025-04-16 13:34:55 +03:00
M1COMM - initial commit
This commit is contained in:
Ariane Fugmann
parent
c35c1f8e5c
commit
c4c906f509
@ -2421,6 +2421,7 @@ files {
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MAME_DIR .. "src/mame/drivers/model1.c",
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MAME_DIR .. "src/mame/machine/model1.c",
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MAME_DIR .. "src/mame/video/model1.c",
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MAME_DIR .. "src/mame/machine/m1comm.c",
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MAME_DIR .. "src/mame/audio/dsbz80.c",
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MAME_DIR .. "src/mame/drivers/model2.c",
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MAME_DIR .. "src/mame/video/model2.c",
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@ -742,6 +742,9 @@ TIMER_DEVICE_CALLBACK_MEMBER(model1_state::model1_interrupt)
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irq_raise(m_sound_irq);
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m_m1audio->check_fifo_irq();
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if (m_m1comm != NULL)
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m_m1comm->check_vint_irq();
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}
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}
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@ -902,6 +905,10 @@ static ADDRESS_MAP_START( model1_mem, AS_PROGRAM, 16, model1_state )
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AM_RANGE(0x900000, 0x903fff) AM_RAM_WRITE(p_w) AM_SHARE("palette")
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AM_RANGE(0x910000, 0x91bfff) AM_RAM AM_SHARE("color_xlat")
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AM_RANGE(0xb00000, 0xb00fff) AM_DEVREADWRITE8("m1comm", m1comm_device, share_r, share_w, 0xffff)
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AM_RANGE(0xb01000, 0xb01001) AM_DEVREADWRITE8("m1comm", m1comm_device, cn_r, cn_w, 0x00ff)
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AM_RANGE(0xb01002, 0xb01003) AM_DEVREADWRITE8("m1comm", m1comm_device, fg_r, fg_w, 0x00ff)
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AM_RANGE(0xc00000, 0xc0003f) AM_READWRITE(io_r, io_w)
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AM_RANGE(0xc00040, 0xc00043) AM_READWRITE(network_ctl_r, network_ctl_w)
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@ -950,6 +957,10 @@ static ADDRESS_MAP_START( model1_vr_mem, AS_PROGRAM, 16, model1_state )
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AM_RANGE(0x900000, 0x903fff) AM_RAM_WRITE(p_w) AM_SHARE("palette")
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AM_RANGE(0x910000, 0x91bfff) AM_RAM AM_SHARE("color_xlat")
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AM_RANGE(0xb00000, 0xb00fff) AM_DEVREADWRITE8("m1comm", m1comm_device, share_r, share_w, 0xffff)
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AM_RANGE(0xb01000, 0xb01001) AM_DEVREADWRITE8("m1comm", m1comm_device, cn_r, cn_w, 0x00ff)
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AM_RANGE(0xb01002, 0xb01003) AM_DEVREADWRITE8("m1comm", m1comm_device, fg_r, fg_w, 0x00ff)
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AM_RANGE(0xc00000, 0xc0003f) AM_READWRITE(io_r, io_w)
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AM_RANGE(0xc00040, 0xc00043) AM_READWRITE(network_ctl_r, network_ctl_w)
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@ -1541,6 +1552,8 @@ static MACHINE_CONFIG_START( model1, model1_state )
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MCFG_VIDEO_START_OVERRIDE(model1_state,model1)
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MCFG_SEGAM1AUDIO_ADD("m1audio")
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MCFG_M1COMM_ADD("m1comm")
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MACHINE_CONFIG_END
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static MACHINE_CONFIG_DERIVED(swa, model1)
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@ -1586,6 +1599,8 @@ static MACHINE_CONFIG_START( model1_vr, model1_state )
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MCFG_VIDEO_START_OVERRIDE(model1_state,model1)
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MCFG_SEGAM1AUDIO_ADD("m1audio")
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MCFG_M1COMM_ADD("m1comm")
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MACHINE_CONFIG_END
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GAME( 1993, vf, 0, model1, vf, driver_device, 0, ROT0, "Sega", "Virtua Fighter", GAME_IMPERFECT_GRAPHICS )
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@ -2,6 +2,7 @@
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// copyright-holders:Olivier Galibert
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#include "audio/dsbz80.h"
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#include "audio/segam1audio.h"
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#include "machine/m1comm.h"
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#include "cpu/v60/v60.h"
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#define DECLARE_TGP_FUNCTION(name) void name()
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@ -16,6 +17,7 @@ public:
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: driver_device(mconfig, type, tag),
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m_maincpu(*this, "maincpu"),
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m_m1audio(*this, "m1audio"),
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m_m1comm(*this, "m1comm"),
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m_dsbz80(*this, DSBZ80_TAG),
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m_tgp(*this, "tgp"),
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m_screen(*this, "screen"),
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@ -29,6 +31,7 @@ public:
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required_device<v60_device> m_maincpu; // V60
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required_device<segam1audio_device> m_m1audio; // Model 1 standard sound board
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optional_device<m1comm_device> m_m1comm; // Model 1 communication board
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optional_device<dsbz80_device> m_dsbz80; // Digital Sound Board
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optional_device<mb86233_cpu_device> m_tgp;
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required_device<screen_device> m_screen;
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290
src/mame/machine/m1comm.c
Normal file
290
src/mame/machine/m1comm.c
Normal file
@ -0,0 +1,290 @@
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// license:BSD-3-Clause
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// copyright-holders:Ariane Fugmann
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/*
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Comm PCB
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--------
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MODEL-1 COMMUNICATION BD 837-8842 171-6293B (C) SEGA 1992
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|--------------------------------------------------------------------------------|
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| |
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| MB89237A MB89374 |
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| JP4 LED1 |
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| 15112.17 Z80 |
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| JP2 JP3 75179 |
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| MB8464 315-5624 JP6 |
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| 315-5547 |
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| 315-5611 SW1 PC910 CN4|
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| |
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| PC910 CN5|
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| MB8421 MB8431 JP7 |
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| JP5 |
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| JP8 CN7|
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| CN1 CN2 |
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| |---------------------------------| |---------------------------------| CN6|
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| |---------------------------------| |---------------------------------| |
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|--------------------------------------------------------------------------------|
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Notes:
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15112.17 - AMD AM27C100 128k x8 EPROM (DIP32, labelled 'EPR-15112')
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Z80 - Zilog Z0840004PSC Z80 CPU, running at 4.000MHz (DIP40)
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MB8464 - Fujitsu MB8464 8k x8 SRAM (DIP28)
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MB8421 - Fujitsu MB8421-12LP 2k x8 SRAM (SDIP52)
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MB8431 - Fujitsu MB8431-90LP 2k x8 SRAM (SDIP52)
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MB89237A - Fujitsu MB89237A DMA-Controller (DIP20) [most likely i8237A clone]
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MB89374 - Fujitsu MB89374 Data Link Controller (SDIP42)
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75179 - Texas Instruments SN75179 Differential Driver and Receiver Pair (DIP8)
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315-5547 - AMI 18CV8PC-25 PAL (DIP20)
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315-5624 - MMI PAL16L8BCN PAL (DIP20)
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315-5611 - Lattice GAL16V8A PAL (DIP20)
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PC910 - Sharp PC910 opto-isolator (x2, DIP8)
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SW1 - Push Button Switch (enables board)
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CN1, CN2 - Connectors to join Comm board to Video board
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CN4 - 8 pin connector (DIFFERENTIAL port)
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CN5 - 6 pin connector (SERIAL port)
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CN6, CN7 - TOSLINK-Connectors for network optical cable link
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JP2 - Jumper, set to 2-3 (connected to EPROM A15)
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JP3 - Jumper, set to 1-2 (connected to EPROM A16)
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JP4 - Jumper, set to 1-2
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JP5 - Jumper, shorted (enables TOSLINK RX channel)
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JP6 - Jumper, not shorted (enables DIFFERERENTIAL RX channel)
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JP7 - Jumper, not shorted (enables SERIAL RX channel)
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JP8 - Jumper, set to 1-2 (selects CLOCK SOURCE)
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*/
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#include "machine/m1comm.h"
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#define Z80_TAG "m1commcpu"
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#define __M1COMM_VERBOSE__
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/*************************************
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* M1COMM Memory Map
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*************************************/
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static ADDRESS_MAP_START( m1comm_mem, AS_PROGRAM, 8, m1comm_device )
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AM_RANGE(0x0000, 0x7fff) AM_ROM
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AM_RANGE(0x8000, 0x9fff) AM_RAM
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AM_RANGE(0xC000, 0xffff) AM_READWRITE(share_r, share_w)
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ADDRESS_MAP_END
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/*************************************
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* M1COMM I/O Map
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*************************************/
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static ADDRESS_MAP_START( m1comm_io, AS_IO, 8, m1comm_device )
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ADDRESS_MAP_GLOBAL_MASK(0xff)
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AM_RANGE(0x00, 0x1F) AM_READWRITE(dlc_reg_r, dlc_reg_w)
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AM_RANGE(0x20, 0x2F) AM_READWRITE(dma_reg_r, dma_reg_w)
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AM_RANGE(0x40, 0x40) AM_READWRITE(syn_r, syn_w)
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AM_RANGE(0x60, 0x60) AM_READWRITE(zfg_r, zfg_w)
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AM_RANGE(0xFFFF, 0xFFFF) AM_RAM
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ADDRESS_MAP_END
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MACHINE_CONFIG_FRAGMENT( m1comm )
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MCFG_CPU_ADD(Z80_TAG, Z80, 4000000) /* 32 MHz / 8 */
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MCFG_CPU_PROGRAM_MAP(m1comm_mem)
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MCFG_CPU_IO_MAP(m1comm_io)
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MACHINE_CONFIG_END
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ROM_START( m1comm )
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ROM_REGION( 0x20000, Z80_TAG, ROMREGION_ERASEFF )
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ROM_LOAD( "epr-15112.17", 0x0000, 0x20000, CRC(4950E771) )
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ROM_END
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//**************************************************************************
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// GLOBAL VARIABLES
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//**************************************************************************
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const device_type M1COMM = &device_creator<m1comm_device>;
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//-------------------------------------------------
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// machine_config_additions - device-specific
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// machine configurations
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//-------------------------------------------------
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machine_config_constructor m1comm_device::device_mconfig_additions() const
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{
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return MACHINE_CONFIG_NAME( m1comm );
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}
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//-------------------------------------------------
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// rom_region - device-specific ROM region
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//-------------------------------------------------
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const rom_entry *m1comm_device::device_rom_region() const
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{
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return ROM_NAME( m1comm );
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}
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//**************************************************************************
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// LIVE DEVICE
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//**************************************************************************
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//-------------------------------------------------
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// m1comm_device - constructor
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//-------------------------------------------------
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m1comm_device::m1comm_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
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device_t(mconfig, M1COMM, "MODEL-1 COMMUNICATION BD", tag, owner, clock, "m1comm", __FILE__),
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m_commcpu(*this, Z80_TAG)
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{
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}
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//-------------------------------------------------
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// device_start - device-specific startup
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//-------------------------------------------------
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void m1comm_device::device_start()
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{
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}
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//-------------------------------------------------
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// device_reset - device-specific reset
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//-------------------------------------------------
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void m1comm_device::device_reset()
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{
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m_syn = 0;
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m_zfg = 0;
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m_cn = 0;
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m_fg = 0;
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m_commcpu->set_input_line(INPUT_LINE_RESET, ASSERT_LINE);
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}
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READ8_MEMBER(m1comm_device::dlc_reg_r)
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{
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// dirty hack to keep Z80 in RESET state
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if (!m_cn)
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{
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device_reset();
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return 0xFF;
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}
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// dirty hack to keep Z80 in RESET state
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UINT8 result = m_dlc_reg[offset];
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#ifdef __M1COMM_VERBOSE__
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printf("m1comm-dlc_reg_r: read register %02x for value %02x\n", offset, result);
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#endif
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return result;
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}
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WRITE8_MEMBER(m1comm_device::dlc_reg_w)
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{
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m_dlc_reg[offset] = data;
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#ifdef __M1COMM_VERBOSE__
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printf("m1comm-dlc_reg_w: write register %02x for value %02x\n", offset, data);
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#endif
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}
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READ8_MEMBER(m1comm_device::dma_reg_r)
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{
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UINT8 result = m_dma_reg[offset];
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#ifdef __M1COMM_VERBOSE__
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printf("m1comm-dma_reg_r: read register %02x for value %02x\n", offset, result);
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#endif
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return result;
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}
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WRITE8_MEMBER(m1comm_device::dma_reg_w)
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{
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#ifdef __M1COMM_VERBOSE__
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printf("m1comm-dma_reg_w: %02x %02x\n", offset, data);
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#endif
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m_dma_reg[offset] = data;
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}
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READ8_MEMBER(m1comm_device::syn_r)
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{
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UINT8 result = m_syn | 0xFC;
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#ifdef __M1COMM_VERBOSE__
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printf("m1comm-syn_r: read register %02x for value %02x\n", offset, result);
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#endif
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return result;
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}
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WRITE8_MEMBER(m1comm_device::syn_w)
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{
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m_syn = data & 0x03;
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#ifdef __M1COMM_VERBOSE__
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switch (data & 0x02)
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{
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case 0x00:
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printf("m1comm-syn_w: VINT disabled\n");
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break;
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case 0x02:
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printf("m1comm-syn_w: VINT enabled\n");
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break;
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default:
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printf("m1comm-syn_w: %02x\n", data);
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break;
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}
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#endif
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}
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READ8_MEMBER(m1comm_device::zfg_r)
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{
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UINT8 result = m_zfg | 0xFE;
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#ifdef __M1COMM_VERBOSE__
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printf("m1comm-zfg_r: read register %02x for value %02x\n", offset, result);
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#endif
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return result;
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}
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WRITE8_MEMBER(m1comm_device::zfg_w)
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{
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#ifdef __M1COMM_VERBOSE__
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printf("m1comm-zfg_w: %02x\n", data);
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#endif
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m_zfg = data & 0x01;
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}
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READ8_MEMBER(m1comm_device::share_r)
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{
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return m_shared[offset];
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}
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WRITE8_MEMBER(m1comm_device::share_w)
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{
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m_shared[offset] = data;
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}
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READ8_MEMBER(m1comm_device::cn_r)
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{
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return m_cn | 0xFE;
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}
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WRITE8_MEMBER(m1comm_device::cn_w)
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{
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m_cn = data & 0x01;
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if (!m_cn)
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device_reset();
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else
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m_commcpu->set_input_line(INPUT_LINE_RESET, CLEAR_LINE);
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}
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READ8_MEMBER(m1comm_device::fg_r)
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{
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return m_fg | (~m_zfg << 7) | 0x7E;
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}
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WRITE8_MEMBER(m1comm_device::fg_w)
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{
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if (!m_cn)
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return;
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m_fg = data & 0x01;
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}
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void m1comm_device::check_vint_irq()
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{
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if (m_syn & 0x02)
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{
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m_commcpu->set_input_line_and_vector(0, HOLD_LINE, 0xEF);
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#ifdef __M1COMM_VERBOSE__
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printf("m1comm-INT5\n");
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#endif
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}
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}
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80
src/mame/machine/m1comm.h
Normal file
80
src/mame/machine/m1comm.h
Normal file
@ -0,0 +1,80 @@
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// license:BSD-3-Clause
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// copyright-holders:Ariane Fugmann
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#pragma once
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#ifndef __M1COMM_H__
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#define __M1COMM_H__
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#include "emu.h"
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#include "cpu/z80/z80.h"
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#define MCFG_M1COMM_ADD(_tag ) \
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MCFG_DEVICE_ADD(_tag, M1COMM, 0)
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//**************************************************************************
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// TYPE DEFINITIONS
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//**************************************************************************
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class m1comm_device : public device_t
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{
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public:
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// construction/destruction
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m1comm_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
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// optional information overrides
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virtual machine_config_constructor device_mconfig_additions() const;
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required_device<z80_device> m_commcpu;
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// internal API - stuff that happens on the comm board
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// MB89374 registers
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DECLARE_READ8_MEMBER(dlc_reg_r);
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DECLARE_WRITE8_MEMBER(dlc_reg_w);
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// MB89237A registers
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DECLARE_READ8_MEMBER(dma_reg_r);
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DECLARE_WRITE8_MEMBER(dma_reg_w);
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// single bit registers (74LS74)
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DECLARE_READ8_MEMBER(syn_r);
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DECLARE_WRITE8_MEMBER(syn_w);
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DECLARE_READ8_MEMBER(zfg_r);
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DECLARE_WRITE8_MEMBER(zfg_w);
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// shared memory 4k
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DECLARE_READ8_MEMBER(share_r);
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DECLARE_WRITE8_MEMBER(share_w);
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// public API - stuff that gets called from the model1
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// shared memory 4k
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// reads/writes at I/O 0xB00xxx
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// - share_r
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// - share_w
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// single bit registers (74LS74)
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// reads/writes at I/O 0xB01000
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DECLARE_READ8_MEMBER(cn_r);
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DECLARE_WRITE8_MEMBER(cn_w);
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// reads/writes at I/O 0xB01002
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DECLARE_READ8_MEMBER(fg_r);
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DECLARE_WRITE8_MEMBER(fg_w);
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// IRQ logic - 5 = VINT, 7 = DLC
|
||||
void check_vint_irq();
|
||||
|
||||
protected:
|
||||
// device-level overrides
|
||||
virtual void device_start();
|
||||
virtual void device_reset();
|
||||
virtual const rom_entry *device_rom_region() const;
|
||||
|
||||
private:
|
||||
UINT8 m_shared[0x1000]; // 2x 2k = 4k; model1 accesses this with 16bit data and 11bit address (A0 to A10)
|
||||
UINT8 m_dlc_reg[0x20]; // MB89374 registers
|
||||
UINT8 m_dma_reg[0x20]; // MB89237A registers
|
||||
UINT8 m_syn; // bit0 is stored; purpose unknown, bit1 is used to enable/disable VINT/IRQ5
|
||||
UINT8 m_zfg; // z80 flip gate? purpose unknown, bit0 is stored
|
||||
UINT8 m_cn; // bit0 is used to enable/disable the comm board
|
||||
UINT8 m_fg; // flip gate? purpose unknown, bit0 is stored, bit7 is connected to ZFG bit 0
|
||||
};
|
||||
|
||||
// device type definition
|
||||
extern const device_type M1COMM;
|
||||
|
||||
#endif /* __M1COMM_H__ */
|
||||
Loading…
Reference in New Issue
Block a user