Sprinter/mame
2
0
Fork 0
mirror of https://github.com/holub/mame synced 2025-10-05 08:41:31 +03:00
Code Issues Actions 3 Packages Projects Releases Wiki Activity

nds: add IPCSYNC, both CPUs now pass first checkpoint and ARM7 makes it to second. [R. Belmont]

Browse Source
This commit is contained in:
arbee 2017-11-17 08:12:48 -05:00
parent 3166f52c3f
commit c5028af1e5
2 changed files with 25 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

24
src/mame/drivers/nds.cpp
View File

@ -30,11 +30,15 @@ READ32_MEMBER(nds_state::arm7_io_r)
{
switch(offset)
{
case IPCSYNC_OFFSET:
return m_arm7_ipcsync;
case POSTFLG_OFFSET:
/* Bit Use
* 0 0=Booting, 1=Booted (set by BIOS/firmware)
*/
return m_arm7_postflg;
default:
verboselog(*this, 0, "[ARM7] [IO] Unknown read: %08x (%08x)\n", offset*4, mem_mask);
break;
@ -47,6 +51,14 @@ WRITE32_MEMBER(nds_state::arm7_io_w)
{
switch(offset)
{
case IPCSYNC_OFFSET:
printf("ARM7: %x to IPCSYNC\n", data);
m_arm9_ipcsync &= ~0xf;
m_arm9_ipcsync |= ((data >> 8) & 0xf);
m_arm7_ipcsync &= 0xf;
m_arm7_ipcsync |= (data & ~0xf);
break;
case POSTFLG_OFFSET:
/* Bit Use
* 0 0=Booting, 1=Booted (set by BIOS/firmware)
@ -67,6 +79,9 @@ READ32_MEMBER(nds_state::arm9_io_r)
{
switch(offset)
{
case IPCSYNC_OFFSET:
return m_arm9_ipcsync;
case POSTFLG_OFFSET:
/* Bit Use
* 0 0=Booting, 1=Booted (set by BIOS/firmware)
@ -85,6 +100,14 @@ WRITE32_MEMBER(nds_state::arm9_io_w)
{
switch(offset)
{
case IPCSYNC_OFFSET:
printf("ARM9: %x to IPCSYNC\n", data);
m_arm7_ipcsync &= ~0xf;
m_arm7_ipcsync |= ((data >> 8) & 0xf);
m_arm9_ipcsync &= 0xf;
m_arm9_ipcsync |= (data & ~0xf);
break;
case POSTFLG_OFFSET:
/* Bit Use
* 0 0=Booting, 1=Booted (set by BIOS/firmware)
@ -135,7 +158,6 @@ void nds_state::machine_start()
static MACHINE_CONFIG_START( nds )
MCFG_CPU_ADD("arm7", ARM7, XTAL_33_333MHz)
MCFG_CPU_PROGRAM_MAP(nds_arm7_map)
MCFG_DEVICE_DISABLE()
MCFG_CPU_ADD("arm9", ARM946ES, XTAL_66_6667MHz)
MCFG_ARM_HIGH_VECTORS()

2
src/mame/includes/nds.h
View File

@ -34,6 +34,7 @@ protected:
required_region_ptr<uint32_t> m_firmware;
enum {
IPCSYNC_OFFSET = 0x180/4,
POSTFLG_OFFSET = 0x300/4,
POSTFLG_PBF_SHIFT = 0,
POSTFLG_RAM_SHIFT = 1,
@ -43,6 +44,7 @@ protected:
uint32_t m_arm7_postflg;
uint32_t m_arm9_postflg;
uint16_t m_arm7_ipcsync, m_arm9_ipcsync;
};
#endif // INCLUDES_NDS_H