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Made the PCI bus a device. The bus is declared in the machine

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config, and the devices attached to it are enumerated there.
Eventually, the PCI config read/write functions should be moved 
to well-known functions within the device, but for now they are
kept separate.

activecpu -= 138
This commit is contained in:
Aaron Giles 2008-12-07 06:14:33 +00:00
parent f351a7d88f
commit c5f3e70c14
22 changed files with 534 additions and 438 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
src/emu/cpu/mb86233/mb86233.c
View File

@ -51,8 +51,8 @@ typedef struct
/* FIFO */
int fifo_wait;
int (*fifo_read_cb)( UINT32 *data );
void (*fifo_write_cb)( UINT32 data );
mb86233_fifo_read_func fifo_read_cb;
mb86233_fifo_write_func fifo_write_cb;
/* internal RAM */
UINT32 *RAM;
@ -677,7 +677,7 @@ static UINT32 GETREGS( UINT32 reg, int source )
if ( mb86233.fifo_read_cb )
{
if ( mb86233.fifo_read_cb(&fifo_data) )
if ( mb86233.fifo_read_cb(mb86233.device, &fifo_data) )
{
return fifo_data;
}
@ -860,7 +860,7 @@ static void SETREGS( UINT32 reg, UINT32 val )
case 0x22: /* FOut */
if ( mb86233.fifo_write_cb )
{
mb86233.fifo_write_cb( val );
mb86233.fifo_write_cb( mb86233.device, val );
}
break;

7
src/emu/cpu/mb86233/mb86233.h
View File

@ -43,11 +43,14 @@ enum
STRUCTURES
***************************************************************************/
typedef int (*mb86233_fifo_read_func)(const device_config *device, UINT32 *data);
typedef void (*mb86233_fifo_write_func)(const device_config *device, UINT32 data);
typedef struct _mb86233_cpu_core mb86233_cpu_core;
struct _mb86233_cpu_core
{
int (*fifo_read_cb)( UINT32* data );
void (*fifo_write_cb)( UINT32 data );
mb86233_fifo_read_func fifo_read_cb;
mb86233_fifo_write_func fifo_write_cb;
const char *tablergn;
};

218
src/emu/machine/pci.c
View File

@ -70,128 +70,214 @@
***************************************************************************/
#include "driver.h"
#include "memconv.h"
#include "devconv.h"
#include "machine/pci.h"
#define LOG_PCI 0
struct pci_device_entry
typedef struct _pci_bus_state pci_bus_state;
struct _pci_bus_state
{
struct pci_device_entry *next;
int bus, device, function;
struct pci_device_info callbacks;
const device_config * busdevice;
const pci_bus_config * config;
const device_config * device[32];
offs_t address;
INT8 devicenum;
};
static struct pci_device_entry *pci_devices;
static struct pci_device_entry *pci_current_device;
static UINT32 pci_address;
/***************************************************************************
INLINE FUNCTIONS
***************************************************************************/
void pci_init(void)
/*-------------------------------------------------
get_safe_token - makes sure that the passed
in device is, in fact, an IDE controller
-------------------------------------------------*/
INLINE pci_bus_state *get_safe_token(const device_config *device)
{
pci_devices = NULL;
pci_current_device = NULL;
pci_address = 0;
assert(device != NULL);
assert(device->token != NULL);
assert(device->type == PCI_BUS);
return (pci_bus_state *)device->token;
}
void pci_add_device(int bus, int device, const struct pci_device_info *devinfo)
READ32_DEVICE_HANDLER( pci_32le_r )
{
struct pci_device_entry *pfi;
pfi = (struct pci_device_entry *) auto_malloc(sizeof(*pfi));
pfi->next = pci_devices;
pfi->bus = bus;
pfi->device = device;
pfi->callbacks = *devinfo;
pci_devices = pfi;
}
READ32_HANDLER(pci_32le_r)
{
UINT32 result = 0xFFFFFFFF;
pci_bus_state *pcibus = get_safe_token(device);
UINT32 result = 0xffffffff;
int function, reg;
offset %= 2;
switch(offset)
switch (offset)
{
case 0:
result = pci_address;
result = pcibus->address;
break;
case 1:
if (pci_current_device && pci_current_device->callbacks.read_callback)
if (pcibus->devicenum != -1)
{
function = (pci_address >> 8) & 0x07;
reg = (pci_address >> 0) & 0xFC;
result = pci_current_device->callbacks.read_callback(function, reg, mem_mask);
pci_read_func read = pcibus->config->device[pcibus->devicenum].read_callback;
if (read != NULL)
{
function = (pcibus->address >> 8) & 0x07;
reg = (pcibus->address >> 0) & 0xfc;
result = (*read)(device, pcibus->device[pcibus->devicenum], function, reg, mem_mask);
}
}
break;
}
if (LOG_PCI)
{
logerror("pci_32le_r(): CPU '%s' pc=0x%08X offset=%d result=0x%08X\n",
space->cpu->tag, (unsigned) cpu_get_reg(space->cpu, REG_PC), offset, result);
}
logerror("pci_32le_r('%s'): offset=%d result=0x%08X\n", device->tag, offset, result);
return result;
}
WRITE32_HANDLER(pci_32le_w)
WRITE32_DEVICE_HANDLER( pci_32le_w )
{
struct pci_device_entry *pfi;
int bus, device, function, reg;
pci_bus_state *pcibus = get_safe_token(device);
offset %= 2;
if (LOG_PCI)
{
logerror("pci_32le_w(): CPU '%s' pc=0x%08X offset=%d data=0x%08X\n",
space->cpu->tag, (unsigned) cpu_get_reg(space->cpu, REG_PC), offset, data);
}
logerror("pci_32le_w('%s'): offset=%d data=0x%08X\n", device->tag, offset, data);
switch(offset)
switch (offset)
{
case 0:
pci_address = data;
pfi = NULL;
pcibus->address = data;
/* lookup current device */
if (pci_address & 0x80000000)
if (pcibus->address & 0x80000000)
{
bus = (pci_address >> 16) & 0xFF;
device = (pci_address >> 11) & 0x1F;
for (pfi = pci_devices; pfi; pfi = pfi->next)
{
if ((pfi->bus == bus) && (pfi->device == device))
break;
}
int busnum = (pcibus->address >> 16) & 0xff;
int devicenum = (pcibus->address >> 11) & 0x1f;
pcibus->devicenum = (busnum == pcibus->config->busnum) ? devicenum : -1;
}
pci_current_device = pfi;
break;
case 1:
if (pci_current_device && pci_current_device->callbacks.write_callback)
if (pcibus->devicenum != -1)
{
function = (pci_address >> 8) & 0x07;
reg = (pci_address >> 0) & 0xFC;
pci_current_device->callbacks.write_callback(function, reg, data, mem_mask);
pci_write_func write = pcibus->config->device[pcibus->devicenum].write_callback;
if (write != NULL)
{
int function = (pcibus->address >> 8) & 0x07;
int reg = (pcibus->address >> 0) & 0xfc;
(*write)(device, pcibus->device[pcibus->devicenum], function, reg, data, mem_mask);
}
}
break;
}
}
READ64_HANDLER(pci_64be_r) { return read64be_with_32le_handler(pci_32le_r, space, offset, mem_mask); }
WRITE64_HANDLER(pci_64be_w) { write64be_with_32le_handler(pci_32le_w, space, offset, data, mem_mask); }
READ64_DEVICE_HANDLER(pci_64be_r) { return read64be_with_32le_device_handler(pci_32le_r, device, offset, mem_mask); }
WRITE64_DEVICE_HANDLER(pci_64be_w) { write64be_with_32le_device_handler(pci_32le_w, device, offset, data, mem_mask); }
/***************************************************************************
DEVICE INTERFACE
***************************************************************************/
/*-------------------------------------------------
device start callback
-------------------------------------------------*/
static DEVICE_START( pci_bus )
{
pci_bus_state *pcibus = get_safe_token(device);
int devicenum;
/* validate some basic stuff */
assert(device != NULL);
assert(device->static_config == NULL);
assert(device->inline_config != NULL);
assert(device->machine != NULL);
assert(device->machine->config != NULL);
/* store a pointer back to the device */
pcibus->config = device->inline_config;
pcibus->busdevice = device;
pcibus->devicenum = -1;
/* find all our devices */
for (devicenum = 0; devicenum < ARRAY_LENGTH(pcibus->device); devicenum++)
if (pcibus->config->device[devicenum].devtag != NULL)
pcibus->device[devicenum] = devtag_get_device(device->machine, pcibus->config->device[devicenum].devtype, pcibus->config->device[devicenum].devtag);
/* register pci states */
state_save_register_device_item(device, 0, pcibus->address);
state_save_register_device_item(device, 0, pcibus->devicenum);
return DEVICE_START_OK;
}
/*-------------------------------------------------
device reset callback
-------------------------------------------------*/
static DEVICE_RESET( pci_bus )
{
pci_bus_state *pcibus = get_safe_token(device);
/* reset the drive state */
pcibus->devicenum = -1;
pcibus->address = 0;
}
/*-------------------------------------------------
device set info callback
-------------------------------------------------*/
static DEVICE_SET_INFO( pci_bus )
{
switch (state)
{
/* no parameters to set */
}
}
/*-------------------------------------------------
device get info callback
-------------------------------------------------*/
DEVICE_GET_INFO( pci_bus )
{
switch (state)
{
/* --- the following bits of info are returned as 64-bit signed integers --- */
case DEVINFO_INT_TOKEN_BYTES: info->i = sizeof(pci_bus_state); break;
case DEVINFO_INT_INLINE_CONFIG_BYTES: info->i = sizeof(pci_bus_config); break;
case DEVINFO_INT_CLASS: info->i = DEVICE_CLASS_PERIPHERAL; break;
/* --- the following bits of info are returned as pointers to data or functions --- */
case DEVINFO_FCT_SET_INFO: info->set_info = DEVICE_SET_INFO_NAME(pci_bus); break;
case DEVINFO_FCT_START: info->start = DEVICE_START_NAME(pci_bus); break;
case DEVINFO_FCT_RESET: info->reset = DEVICE_RESET_NAME(pci_bus);break;
/* --- the following bits of info are returned as NULL-terminated strings --- */
case DEVINFO_STR_NAME: info->s = "PCI Bus"; break;
case DEVINFO_STR_FAMILY: info->s = "Peripherial Bus"; break;
case DEVINFO_STR_VERSION: info->s = "1.0"; break;
case DEVINFO_STR_SOURCE_FILE: info->s = __FILE__; break;
case DEVINFO_STR_CREDITS: info->s = "Copyright Nicola Salmoria and the MAME Team"; break;
}
}

61
src/emu/machine/pci.h
View File

@ -9,21 +9,64 @@
#ifndef PCI_H
#define PCI_H
struct pci_device_info
/***************************************************************************
TYPE DEFINITIONS
***************************************************************************/
typedef UINT32 (*pci_read_func)(const device_config *pcibus, const device_config *device, int function, int reg, UINT32 mem_mask);
typedef void (*pci_write_func)(const device_config *pcibus, const device_config *device, int function, int reg, UINT32 data, UINT32 mem_mask);
typedef struct _pci_device_entry pci_device_entry;
struct _pci_device_entry
{
UINT32 (*read_callback)(int function, int reg, UINT32 mem_mask);
void (*write_callback)(int function, int reg, UINT32 data, UINT32 mem_mask);
device_type devtype;
const char * devtag;
pci_read_func read_callback;
pci_write_func write_callback;
};
typedef struct _pci_bus_config pci_bus_config;
struct _pci_bus_config
{
UINT8 busnum;
pci_device_entry device[32];
};
void pci_init(void);
void pci_add_device(int bus, int device, const struct pci_device_info *devinfo);
READ32_HANDLER(pci_32le_r);
WRITE32_HANDLER(pci_32le_w);
/***************************************************************************
DEVICE CONFIGURATION MACROS
***************************************************************************/
READ64_HANDLER(pci_64be_r);
WRITE64_HANDLER(pci_64be_w);
#define MDRV_PCI_BUS_ADD(_tag, _busnum) \
MDRV_DEVICE_ADD(_tag, PCI_BUS) \
MDRV_DEVICE_CONFIG_DATA32(pci_bus_config, busnum, _busnum)
#define MDRV_PCI_BUS_DEVICE(_devnum, _devtype, _devtag, _configread, _configwrite) \
MDRV_DEVICE_CONFIG_DATA32_ARRAY_MEMBER(pci_bus_config, device, _devnum, pci_device_entry, devtype, _devtype) \
MDRV_DEVICE_CONFIG_DATA32_ARRAY_MEMBER(pci_bus_config, device, _devnum, pci_device_entry, devtag, _devtag) \
MDRV_DEVICE_CONFIG_DATAPTR_ARRAY_MEMBER(pci_bus_config, device, _devnum, pci_device_entry, read_callback, _configread) \
MDRV_DEVICE_CONFIG_DATAPTR_ARRAY_MEMBER(pci_bus_config, device, _devnum, pci_device_entry, write_callback, _configwrite)
/***************************************************************************
FUNCTION PROTOTYPES
***************************************************************************/
READ32_DEVICE_HANDLER( pci_32le_r );
WRITE32_DEVICE_HANDLER( pci_32le_w );
READ64_DEVICE_HANDLER( pci_64be_r );
WRITE64_DEVICE_HANDLER( pci_64be_w );
/* ----- device interface ----- */
/* device get info callback */
#define PCI_BUS DEVICE_GET_INFO_NAME(pci_bus)
DEVICE_GET_INFO( pci_bus );
#endif /* PCI_H */

74
src/mame/drivers/gamecstl.c
View File

@ -176,14 +176,14 @@ static WRITE32_DEVICE_HANDLER(at32_dma8237_2_w)
// Intel 82439TX System Controller (MXTC)
static UINT8 mxtc_config_reg[256];
static UINT8 mxtc_config_r(int function, int reg)
static UINT8 mxtc_config_r(const device_config *busdevice, const device_config *device, int function, int reg)
{
// mame_printf_debug("MXTC: read %d, %02X\n", function, reg);
return mxtc_config_reg[reg];
}
static void mxtc_config_w(running_machine *machine, int function, int reg, UINT8 data)
static void mxtc_config_w(const device_config *busdevice, const device_config *device, int function, int reg, UINT8 data)
{
// mame_printf_debug("MXTC: write %d, %02X, %02X at %08X\n", function, reg, data, cpu_get_pc(machine->activecpu));
@ -193,11 +193,11 @@ static void mxtc_config_w(running_machine *machine, int function, int reg, UINT8
{
if (data & 0x10) // enable RAM access to region 0xf0000 - 0xfffff
{
memory_set_bankptr(machine, 1, bios_ram);
memory_set_bankptr(busdevice->machine, 1, bios_ram);
}
else // disable RAM access (reads go to BIOS ROM)
{
memory_set_bankptr(machine, 1, memory_region(machine, "user1") + 0x30000);
memory_set_bankptr(busdevice->machine, 1, memory_region(busdevice->machine, "user1") + 0x30000);
}
break;
}
@ -216,102 +216,102 @@ static void intel82439tx_init(void)
mxtc_config_reg[0x65] = 0x02;
}
static UINT32 intel82439tx_pci_r(int function, int reg, UINT32 mem_mask)
static UINT32 intel82439tx_pci_r(const device_config *busdevice, const device_config *device, int function, int reg, UINT32 mem_mask)
{
UINT32 r = 0;
if (ACCESSING_BITS_24_31)
{
r |= mxtc_config_r(function, reg + 3) << 24;
r |= mxtc_config_r(busdevice, device, function, reg + 3) << 24;
}
if (ACCESSING_BITS_16_23)
{
r |= mxtc_config_r(function, reg + 2) << 16;
r |= mxtc_config_r(busdevice, device, function, reg + 2) << 16;
}
if (ACCESSING_BITS_8_15)
{
r |= mxtc_config_r(function, reg + 1) << 8;
r |= mxtc_config_r(busdevice, device, function, reg + 1) << 8;
}
if (ACCESSING_BITS_0_7)
{
r |= mxtc_config_r(function, reg + 0) << 0;
r |= mxtc_config_r(busdevice, device, function, reg + 0) << 0;
}
return r;
}
static void intel82439tx_pci_w(int function, int reg, UINT32 data, UINT32 mem_mask)
static void intel82439tx_pci_w(const device_config *busdevice, const device_config *device, int function, int reg, UINT32 data, UINT32 mem_mask)
{
if (ACCESSING_BITS_24_31)
{
mxtc_config_w(Machine, function, reg + 3, (data >> 24) & 0xff);
mxtc_config_w(busdevice, device, function, reg + 3, (data >> 24) & 0xff);
}
if (ACCESSING_BITS_16_23)
{
mxtc_config_w(Machine, function, reg + 2, (data >> 16) & 0xff);
mxtc_config_w(busdevice, device, function, reg + 2, (data >> 16) & 0xff);
}
if (ACCESSING_BITS_8_15)
{
mxtc_config_w(Machine, function, reg + 1, (data >> 8) & 0xff);
mxtc_config_w(busdevice, device, function, reg + 1, (data >> 8) & 0xff);
}
if (ACCESSING_BITS_0_7)
{
mxtc_config_w(Machine, function, reg + 0, (data >> 0) & 0xff);
mxtc_config_w(busdevice, device, function, reg + 0, (data >> 0) & 0xff);
}
}
// Intel 82371AB PCI-to-ISA / IDE bridge (PIIX4)
static UINT8 piix4_config_reg[4][256];
static UINT8 piix4_config_r(int function, int reg)
static UINT8 piix4_config_r(const device_config *busdevice, const device_config *device, int function, int reg)
{
// mame_printf_debug("PIIX4: read %d, %02X\n", function, reg);
return piix4_config_reg[function][reg];
}
static void piix4_config_w(int function, int reg, UINT8 data)
static void piix4_config_w(const device_config *busdevice, const device_config *device, int function, int reg, UINT8 data)
{
// mame_printf_debug("PIIX4: write %d, %02X, %02X at %08X\n", function, reg, data, cpu_get_pc(machine->activecpu));
piix4_config_reg[function][reg] = data;
}
static UINT32 intel82371ab_pci_r(int function, int reg, UINT32 mem_mask)
static UINT32 intel82371ab_pci_r(const device_config *busdevice, const device_config *device, int function, int reg, UINT32 mem_mask)
{
UINT32 r = 0;
if (ACCESSING_BITS_24_31)
{
r |= piix4_config_r(function, reg + 3) << 24;
r |= piix4_config_r(busdevice, device, function, reg + 3) << 24;
}
if (ACCESSING_BITS_16_23)
{
r |= piix4_config_r(function, reg + 2) << 16;
r |= piix4_config_r(busdevice, device, function, reg + 2) << 16;
}
if (ACCESSING_BITS_8_15)
{
r |= piix4_config_r(function, reg + 1) << 8;
r |= piix4_config_r(busdevice, device, function, reg + 1) << 8;
}
if (ACCESSING_BITS_0_7)
{
r |= piix4_config_r(function, reg + 0) << 0;
r |= piix4_config_r(busdevice, device, function, reg + 0) << 0;
}
return r;
}
static void intel82371ab_pci_w(int function, int reg, UINT32 data, UINT32 mem_mask)
static void intel82371ab_pci_w(const device_config *busdevice, const device_config *device, int function, int reg, UINT32 data, UINT32 mem_mask)
{
if (ACCESSING_BITS_24_31)
{
piix4_config_w(function, reg + 3, (data >> 24) & 0xff);
piix4_config_w(busdevice, device, function, reg + 3, (data >> 24) & 0xff);
}
if (ACCESSING_BITS_16_23)
{
piix4_config_w(function, reg + 2, (data >> 16) & 0xff);
piix4_config_w(busdevice, device, function, reg + 2, (data >> 16) & 0xff);
}
if (ACCESSING_BITS_8_15)
{
piix4_config_w(function, reg + 1, (data >> 8) & 0xff);
piix4_config_w(busdevice, device, function, reg + 1, (data >> 8) & 0xff);
}
if (ACCESSING_BITS_0_7)
{
piix4_config_w(function, reg + 0, (data >> 0) & 0xff);
piix4_config_w(busdevice, device, function, reg + 0, (data >> 0) & 0xff);
}
}
@ -514,7 +514,7 @@ static ADDRESS_MAP_START(gamecstl_io, ADDRESS_SPACE_IO, 32)
AM_RANGE(0x0278, 0x027b) AM_WRITE(pnp_config_w)
AM_RANGE(0x03f0, 0x03ff) AM_DEVREADWRITE(IDE_CONTROLLER, "ide", fdc_r, fdc_w)
AM_RANGE(0x0a78, 0x0a7b) AM_WRITE(pnp_data_w)
AM_RANGE(0x0cf8, 0x0cff) AM_READWRITE(pci_32le_r, pci_32le_w)
AM_RANGE(0x0cf8, 0x0cff) AM_DEVREADWRITE(PCI_BUS, "pcibus", pci_32le_r, pci_32le_w)
ADDRESS_MAP_END
/*****************************************************************************/
@ -662,6 +662,10 @@ static MACHINE_DRIVER_START(gamecstl)
MDRV_MACHINE_RESET(gamecstl)
MDRV_PCI_BUS_ADD("pcibus", 0)
MDRV_PCI_BUS_DEVICE(0, NULL, NULL, intel82439tx_pci_r, intel82439tx_pci_w)
MDRV_PCI_BUS_DEVICE(7, NULL, NULL, intel82371ab_pci_r, intel82371ab_pci_w)
MDRV_DEVICE_ADD( "pit8254", PIT8254 )
MDRV_DEVICE_CONFIG( gamecstl_pit8254_config )
@ -697,18 +701,6 @@ static MACHINE_DRIVER_START(gamecstl)
MACHINE_DRIVER_END
static const struct pci_device_info intel82439tx =
{
intel82439tx_pci_r,
intel82439tx_pci_w
};
static const struct pci_device_info intel82371ab =
{
intel82371ab_pci_r,
intel82371ab_pci_w
};
static void set_gate_a20(int a20)
{
cpu_set_input_line(Machine->cpu[0], INPUT_LINE_A20, a20);
@ -746,10 +738,6 @@ static DRIVER_INIT( gamecstl )
intel82439tx_init();
pci_init();
pci_add_device(0, 0, &intel82439tx);
pci_add_device(0, 7, &intel82371ab);
kbdc8042_init(&at8042);
}

19
src/mame/drivers/mediagx.c
View File

@ -612,7 +612,7 @@ static WRITE32_HANDLER( parallel_port_w )
}
}
static UINT32 cx5510_pci_r(int function, int reg, UINT32 mem_mask)
static UINT32 cx5510_pci_r(const device_config *busdevice, const device_config *device, int function, int reg, UINT32 mem_mask)
{
// mame_printf_debug("CX5510: PCI read %d, %02X, %08X\n", function, reg, mem_mask);
@ -624,7 +624,7 @@ static UINT32 cx5510_pci_r(int function, int reg, UINT32 mem_mask)
return cx5510_regs[reg/4];
}
static void cx5510_pci_w(int function, int reg, UINT32 data, UINT32 mem_mask)
static void cx5510_pci_w(const device_config *busdevice, const device_config *device, int function, int reg, UINT32 data, UINT32 mem_mask)
{
// mame_printf_debug("CX5510: PCI write %d, %02X, %08X, %08X\n", function, reg, data, mem_mask);
COMBINE_DATA(cx5510_regs + (reg/4));
@ -854,7 +854,7 @@ static ADDRESS_MAP_START(mediagx_io, ADDRESS_SPACE_IO, 32)
AM_RANGE(0x0378, 0x037b) AM_READWRITE(parallel_port_r, parallel_port_w)
AM_RANGE(0x03f0, 0x03ff) AM_DEVREADWRITE(IDE_CONTROLLER, "ide", fdc_r, fdc_w)
AM_RANGE(0x0400, 0x04ff) AM_READWRITE(ad1847_r, ad1847_w)
AM_RANGE(0x0cf8, 0x0cff) AM_READWRITE(pci_32le_r, pci_32le_w)
AM_RANGE(0x0cf8, 0x0cff) AM_DEVREADWRITE(PCI_BUS, "pcibus", pci_32le_r, pci_32le_w)
ADDRESS_MAP_END
/*****************************************************************************/
@ -964,6 +964,7 @@ static MACHINE_RESET(mediagx)
cpu_set_irq_callback(machine->cpu[0], irq_callback);
memcpy(bios_ram, rom, 0x40000);
cpu_reset(machine->cpu[0]);
dacl = auto_malloc(65536 * sizeof(INT16));
dacr = auto_malloc(65536 * sizeof(INT16));
@ -1040,6 +1041,9 @@ static MACHINE_DRIVER_START(mediagx)
MDRV_MACHINE_START(mediagx)
MDRV_MACHINE_RESET(mediagx)
MDRV_PCI_BUS_ADD("pcibus", 0)
MDRV_PCI_BUS_DEVICE(18, NULL, NULL, cx5510_pci_r, cx5510_pci_w)
MDRV_DEVICE_ADD( "pit8254", PIT8254 )
MDRV_DEVICE_CONFIG( mediagx_pit8254_config )
@ -1106,12 +1110,6 @@ static const struct kbdc8042_interface at8042 =
KBDC8042_AT386, set_gate_a20, keyboard_interrupt, mediagx_get_out2
};
static const struct pci_device_info cx5510 =
{
cx5510_pci_r,
cx5510_pci_w
};
static void mediagx_set_keyb_int(int state) {
pic8259_set_irq_line(mediagx_devices.pic8259_1, 1, state);
}
@ -1123,9 +1121,6 @@ static void init_mediagx(running_machine *machine)
init_pc_common(machine, PCCOMMON_KEYBOARD_AT,mediagx_set_keyb_int);
mc146818_init(machine, MC146818_STANDARD);
pci_init();
pci_add_device(0, 18, &cx5510);
kbdc8042_init(&at8042);
}

36
src/mame/drivers/model2.c
View File

@ -91,7 +91,7 @@ static int dsp_type;
static int copro_fifoin_rpos, copro_fifoin_wpos;
static UINT32 copro_fifoin_data[COPRO_FIFOIN_SIZE];
static int copro_fifoin_num = 0;
static int copro_fifoin_pop(UINT32 *result)
static int copro_fifoin_pop(const device_config *device, UINT32 *result)
{
UINT32 r;
@ -100,7 +100,7 @@ static int copro_fifoin_pop(UINT32 *result)
if (dsp_type == DSP_TYPE_TGP)
return 0;
fatalerror("Copro FIFOIN underflow (at %08X)", cpu_get_pc(Machine->activecpu));
fatalerror("Copro FIFOIN underflow (at %08X)", cpu_get_pc(device));
return 0;
}
@ -116,13 +116,13 @@ static int copro_fifoin_pop(UINT32 *result)
{
if (copro_fifoin_num == 0)
{
cpu_push_context(Machine->cpu[2]);
cpu_push_context(device);
sharc_set_flag_input(0, ASSERT_LINE);
cpu_pop_context();
}
else
{
cpu_push_context(Machine->cpu[2]);
cpu_push_context(device);
sharc_set_flag_input(0, CLEAR_LINE);
cpu_pop_context();
}
@ -133,15 +133,15 @@ static int copro_fifoin_pop(UINT32 *result)
return 1;
}
static void copro_fifoin_push(UINT32 data)
static void copro_fifoin_push(const device_config *device, UINT32 data)
{
if (copro_fifoin_num == COPRO_FIFOIN_SIZE)
{
fatalerror("Copro FIFOIN overflow (at %08X)", cpu_get_pc(Machine->activecpu));
fatalerror("Copro FIFOIN overflow (at %08X)", cpu_get_pc(device));
return;
}
//mame_printf_debug("COPRO FIFOIN at %08X, %08X, %f\n", cpu_get_pc(Machine->activecpu), data, *(float*)&data);
//mame_printf_debug("COPRO FIFOIN at %08X, %08X, %f\n", cpu_get_pc(device), data, *(float*)&data);
copro_fifoin_data[copro_fifoin_wpos++] = data;
if (copro_fifoin_wpos == COPRO_FIFOIN_SIZE)
@ -154,7 +154,7 @@ static void copro_fifoin_push(UINT32 data)
// clear FIFO empty flag on SHARC
if (dsp_type == DSP_TYPE_SHARC)
{
cpu_push_context(Machine->cpu[2]);
cpu_push_context(device);
sharc_set_flag_input(0, CLEAR_LINE);
cpu_pop_context();
}
@ -211,12 +211,12 @@ static UINT32 copro_fifoout_pop(void)
return r;
}
static void copro_fifoout_push(UINT32 data)
static void copro_fifoout_push(const device_config *device, UINT32 data)
{
//if (copro_fifoout_wpos == copro_fifoout_rpos)
if (copro_fifoout_num == COPRO_FIFOOUT_SIZE)
{
fatalerror("Copro FIFOOUT overflow (at %08X)", cpu_get_pc(Machine->activecpu));
fatalerror("Copro FIFOOUT overflow (at %08X)", cpu_get_pc(device));
return;
}
@ -235,19 +235,19 @@ static void copro_fifoout_push(UINT32 data)
{
if (copro_fifoout_num == COPRO_FIFOOUT_SIZE)
{
cpu_push_context(Machine->cpu[2]);
cpu_push_context(device);
sharc_set_flag_input(1, ASSERT_LINE);
cpu_pop_context();
//cpu_set_input_line(Machine->cpu[2], SHARC_INPUT_FLAG1, ASSERT_LINE);
//cpu_set_input_line(device, SHARC_INPUT_FLAG1, ASSERT_LINE);
}
else
{
cpu_push_context(Machine->cpu[2]);
cpu_push_context(device);
sharc_set_flag_input(1, CLEAR_LINE);
cpu_pop_context();
//cpu_set_input_line(Machine->cpu[2], SHARC_INPUT_FLAG1, CLEAR_LINE);
//cpu_set_input_line(device, SHARC_INPUT_FLAG1, CLEAR_LINE);
}
}
}
@ -556,7 +556,7 @@ static WRITE32_HANDLER(copro_function_port_w)
d |= a << 23;
//logerror("copro_function_port_w: %08X, %08X, %08X\n", data, offset, mem_mask);
copro_fifoin_push(d);
copro_fifoin_push(space->machine->cpu[2], d);
}
static READ32_HANDLER(copro_fifo_r)
@ -585,7 +585,7 @@ static WRITE32_HANDLER(copro_fifo_w)
else
{
//mame_printf_debug("copro_fifo_w: %08X, %08X, %08X at %08X\n", data, offset, mem_mask, cpu_get_pc(space->cpu));
copro_fifoin_push(data);
copro_fifoin_push(space->machine->cpu[2], data);
}
}
@ -1747,14 +1747,14 @@ static READ32_HANDLER(copro_sharc_input_fifo_r)
UINT32 result;
//mame_printf_debug("SHARC FIFOIN pop at %08X\n", cpu_get_pc(space->cpu));
copro_fifoin_pop(&result);
copro_fifoin_pop(space->machine->cpu[2], &result);
return result;
}
static WRITE32_HANDLER(copro_sharc_output_fifo_w)
{
//mame_printf_debug("SHARC FIFOOUT push %08X\n", data);
copro_fifoout_push(data);
copro_fifoout_push(space->machine->cpu[2], data);
}
static READ32_HANDLER(copro_sharc_buffer_r)

9
src/mame/drivers/qdrmfgp.c
View File

@ -241,16 +241,17 @@ static WRITE16_DEVICE_HANDLER( ide_alt_w )
}
static READ16_DEVICE_HANDLER( gp2_ide_std_r )
static READ16_HANDLER( gp2_ide_std_r )
{
const device_config *device = devtag_get_device(space->machine, IDE_CONTROLLER, "ide");
if (offset & 0x01)
{
if (offset == 0x07)
{
switch (cpu_get_previouspc(device->machine->activecpu))
switch (cpu_get_previouspc(space->cpu))
{
case 0xdb4c:
if ((workram[0x5fa4/2] - cpu_get_reg(device->machine->activecpu, M68K_D0)) <= 0x10)
if ((workram[0x5fa4/2] - cpu_get_reg(space->cpu, M68K_D0)) <= 0x10)
gp2_irq_control = 1;
break;
case 0xdec2:
@ -387,7 +388,7 @@ static ADDRESS_MAP_START( gp2_readmem, ADDRESS_SPACE_PROGRAM, 16 )
AM_RANGE(0x880000, 0x881fff) AM_READ(gp2_vram_r) /* vram */
AM_RANGE(0x89f000, 0x8a0fff) AM_READ(gp2_vram_mirror_r) /* vram (mirror) */
AM_RANGE(0x900000, 0x901fff) AM_READ(v_rom_r) /* gfxrom through */
AM_RANGE(0xa00000, 0xa0000f) AM_DEVREAD(IDE_CONTROLLER, "ide", gp2_ide_std_r) /* IDE control regs */
AM_RANGE(0xa00000, 0xa0000f) AM_READ(gp2_ide_std_r) /* IDE control regs */
AM_RANGE(0xa4000c, 0xa4000f) AM_DEVREAD(IDE_CONTROLLER, "ide", ide_alt_r) /* IDE status control reg */
AM_RANGE(0xc00000, 0xcbffff) AM_READ(sndram_r) /* sound ram */
ADDRESS_MAP_END

16
src/mame/drivers/quizpun2.c
View File

@ -135,9 +135,9 @@ static MACHINE_RESET( quizpun2 )
prot.addr = 0;
}
static void log_protection( running_machine *machine, const char *warning )
static void log_protection( const address_space *space, const char *warning )
{
logerror("%04x: protection - %s (state %x, wait %x, param %02x, cmd %02x, addr %02x)\n", cpu_get_pc(machine->activecpu), warning,
logerror("%04x: protection - %s (state %x, wait %x, param %02x, cmd %02x, addr %02x)\n", cpu_get_pc(space->cpu), warning,
prot.state,
prot.wait_param,
prot.param,
@ -174,7 +174,7 @@ static READ8_HANDLER( quizpun2_protection_r )
break;
default:
log_protection(space->machine, "unknown address");
log_protection(space, "unknown address");
ret = 0x2e59 >> ((prot.addr & 1) ? 0 : 8); // return the address of: XOR A, RET
}
break;
@ -187,12 +187,12 @@ static READ8_HANDLER( quizpun2_protection_r )
}
default:
log_protection(space->machine, "unknown read");
log_protection(space, "unknown read");
ret = 0x00;
}
#if VERBOSE_PROTECTION_LOG
log_protection(space->machine, "info READ");
log_protection(space, "info READ");
#endif
prot.addr++;
@ -235,7 +235,7 @@ static WRITE8_HANDLER( quizpun2_protection_w )
prot.addr = 0;
}
else
log_protection(space->machine, "unknown command");
log_protection(space, "unknown command");
}
else if (prot.cmd >= 0x00 && prot.cmd <= 0x0f )
{
@ -250,7 +250,7 @@ static WRITE8_HANDLER( quizpun2_protection_w )
else
{
prot.state = STATE_IDLE;
log_protection(space->machine, "unknown command");
log_protection(space, "unknown command");
}
}
else
@ -262,7 +262,7 @@ static WRITE8_HANDLER( quizpun2_protection_w )
}
#if VERBOSE_PROTECTION_LOG
log_protection(space->machine, "info WRITE");
log_protection(space, "info WRITE");
#endif
}

12
src/mame/drivers/raiden2.c
View File

@ -682,18 +682,18 @@ WRITE16_HANDLER(sprcpt_flags_2_w)
// XXX
// write only: 4c0 4c1 500 501 502 503
static UINT16 handle_io_r(running_machine *machine, int offset)
static UINT16 handle_io_r(const address_space *space, int offset)
{
logerror("io_r %04x, %04x (%x)\n", offset*2, mainram[offset], cpu_get_pc(machine->activecpu));
logerror("io_r %04x, %04x (%x)\n", offset*2, mainram[offset], cpu_get_pc(space->cpu));
return mainram[offset];
}
static void handle_io_w(running_machine *machine, int offset, UINT16 data, UINT16 mem_mask)
static void handle_io_w(const address_space *space, int offset, UINT16 data, UINT16 mem_mask)
{
COMBINE_DATA(&mainram[offset]);
switch(offset) {
default:
logerror("io_w %04x, %04x & %04x (%x)\n", offset*2, data, mem_mask, cpu_get_pc(machine->activecpu));
logerror("io_w %04x, %04x & %04x (%x)\n", offset*2, data, mem_mask, cpu_get_pc(space->cpu));
}
}
@ -702,7 +702,7 @@ static READ16_HANDLER(any_r)
c_r[offset]++;
if(offset >= 0x400/2 && offset < 0x800/2)
return handle_io_r(space->machine, offset);
return handle_io_r(space, offset);
return mainram[offset];
}
@ -711,7 +711,7 @@ static WRITE16_HANDLER(any_w)
{
int show = 0;
if(offset >= 0x400/2 && offset < 0x800/2)
handle_io_w(space->machine, offset, data, mem_mask);
handle_io_w(space, offset, data, mem_mask);
c_w[offset]++;
// logerror("mainram_w %04x, %02x (%x)\n", offset, data, cpu_get_pc(space->cpu));

48
src/mame/drivers/seattle.c
View File

@ -769,7 +769,7 @@ static void vblank_assert(const device_config *device, int state)
*
*************************************/
static UINT32 pci_bridge_r(running_machine *machine, UINT8 reg, UINT8 type)
static UINT32 pci_bridge_r(const address_space *space, UINT8 reg, UINT8 type)
{
UINT32 result = galileo.pci_bridge_regs[reg];
@ -785,16 +785,16 @@ static UINT32 pci_bridge_r(running_machine *machine, UINT8 reg, UINT8 type)
}
if (LOG_PCI)
logerror("%08X:PCI bridge read: reg %d type %d = %08X\n", cpu_get_pc(machine->activecpu), reg, type, result);
logerror("%08X:PCI bridge read: reg %d type %d = %08X\n", cpu_get_pc(space->cpu), reg, type, result);
return result;
}
static void pci_bridge_w(running_machine *machine, UINT8 reg, UINT8 type, UINT32 data)
static void pci_bridge_w(const address_space *space, UINT8 reg, UINT8 type, UINT32 data)
{
galileo.pci_bridge_regs[reg] = data;
if (LOG_PCI)
logerror("%08X:PCI bridge write: reg %d type %d = %08X\n", cpu_get_pc(machine->activecpu), reg, type, data);
logerror("%08X:PCI bridge write: reg %d type %d = %08X\n", cpu_get_pc(space->cpu), reg, type, data);
}
@ -805,7 +805,7 @@ static void pci_bridge_w(running_machine *machine, UINT8 reg, UINT8 type, UINT32
*
*************************************/
static UINT32 pci_3dfx_r(running_machine *machine, UINT8 reg, UINT8 type)
static UINT32 pci_3dfx_r(const address_space *space, UINT8 reg, UINT8 type)
{
UINT32 result = galileo.pci_3dfx_regs[reg];
@ -821,12 +821,12 @@ static UINT32 pci_3dfx_r(running_machine *machine, UINT8 reg, UINT8 type)
}
if (LOG_PCI)
logerror("%08X:PCI 3dfx read: reg %d type %d = %08X\n", cpu_get_pc(machine->activecpu), reg, type, result);
logerror("%08X:PCI 3dfx read: reg %d type %d = %08X\n", cpu_get_pc(space->cpu), reg, type, result);
return result;
}
static void pci_3dfx_w(running_machine *machine, UINT8 reg, UINT8 type, UINT32 data)
static void pci_3dfx_w(const address_space *space, UINT8 reg, UINT8 type, UINT32 data)
{
galileo.pci_3dfx_regs[reg] = data;
@ -843,7 +843,7 @@ static void pci_3dfx_w(running_machine *machine, UINT8 reg, UINT8 type, UINT32 d
break;
}
if (LOG_PCI)
logerror("%08X:PCI 3dfx write: reg %d type %d = %08X\n", cpu_get_pc(machine->activecpu), reg, type, data);
logerror("%08X:PCI 3dfx write: reg %d type %d = %08X\n", cpu_get_pc(space->cpu), reg, type, data);
}
@ -854,7 +854,7 @@ static void pci_3dfx_w(running_machine *machine, UINT8 reg, UINT8 type, UINT32 d
*
*************************************/
static UINT32 pci_ide_r(running_machine *machine, UINT8 reg, UINT8 type)
static UINT32 pci_ide_r(const address_space *space, UINT8 reg, UINT8 type)
{
UINT32 result = galileo.pci_ide_regs[reg];
@ -870,16 +870,16 @@ static UINT32 pci_ide_r(running_machine *machine, UINT8 reg, UINT8 type)
}
if (LOG_PCI)
logerror("%08X:PCI IDE read: reg %d type %d = %08X\n", cpu_get_pc(machine->activecpu), reg, type, result);
logerror("%08X:PCI IDE read: reg %d type %d = %08X\n", cpu_get_pc(space->cpu), reg, type, result);
return result;
}
static void pci_ide_w(running_machine *machine, UINT8 reg, UINT8 type, UINT32 data)
static void pci_ide_w(const address_space *space, UINT8 reg, UINT8 type, UINT32 data)
{
galileo.pci_ide_regs[reg] = data;
if (LOG_PCI)
logerror("%08X:PCI bridge write: reg %d type %d = %08X\n", cpu_get_pc(machine->activecpu), reg, type, data);
logerror("%08X:PCI bridge write: reg %d type %d = %08X\n", cpu_get_pc(space->cpu), reg, type, data);
}
@ -1126,15 +1126,15 @@ static READ32_HANDLER( galileo_r )
/* unit 0 is the PCI bridge */
if (unit == 0 && func == 0)
result = pci_bridge_r(space->machine, reg, type);
result = pci_bridge_r(space, reg, type);
/* unit 8 is the 3dfx card */
else if (unit == 8 && func == 0)
result = pci_3dfx_r(space->machine, reg, type);
result = pci_3dfx_r(space, reg, type);
/* unit 9 is the IDE controller */
else if (unit == 9 && func == 0)
result = pci_ide_r(space->machine, reg, type);
result = pci_ide_r(space, reg, type);
/* anything else, just log */
else
@ -1264,15 +1264,15 @@ static WRITE32_HANDLER( galileo_w )
/* unit 0 is the PCI bridge */
if (unit == 0 && func == 0)
pci_bridge_w(space->machine, reg, type, data);
pci_bridge_w(space, reg, type, data);
/* unit 8 is the 3dfx card */
else if (unit == 8 && func == 0)
pci_3dfx_w(space->machine, reg, type, data);
pci_3dfx_w(space, reg, type, data);
/* unit 9 is the IDE controller */
else if (unit == 9 && func == 0)
pci_ide_w(space->machine, reg, type, data);
pci_ide_w(space, reg, type, data);
/* anything else, just log */
else
@ -1304,12 +1304,12 @@ static WRITE32_HANDLER( galileo_w )
*
*************************************/
static WRITE32_DEVICE_HANDLER( seattle_voodoo_w )
static WRITE32_HANDLER( seattle_voodoo_w )
{
/* if we're not stalled, just write and get out */
if (!voodoo_stalled)
{
voodoo_w(device, offset, data, mem_mask);
voodoo_w(voodoo_device, offset, data, mem_mask);
return;
}
@ -1324,8 +1324,8 @@ static WRITE32_DEVICE_HANDLER( seattle_voodoo_w )
cpu_stalled_mem_mask = mem_mask;
/* spin until we send the magic trigger */
cpu_spinuntil_trigger(device->machine->cpu[0], 45678);
if (LOG_DMA) logerror("%08X:Stalling CPU on voodoo (already stalled)\n", cpu_get_pc(device->machine->activecpu));
cpu_spinuntil_trigger(space->cpu, 45678);
if (LOG_DMA) logerror("%08X:Stalling CPU on voodoo (already stalled)\n", cpu_get_pc(space->cpu));
}
@ -1344,7 +1344,7 @@ static void voodoo_stall(const device_config *device, int stall)
}
else
{
if (LOG_DMA) logerror("%08X:Stalling CPU on voodoo\n", cpu_get_pc(device->machine->activecpu));
if (LOG_DMA) logerror("%08X:Stalling CPU on voodoo\n", cpu_get_pc(device->machine->cpu[0]));
cpu_spinuntil_trigger(device->machine->cpu[0], 45678);
}
}
@ -1732,7 +1732,7 @@ PCI Mem = 08000000-09FFFFFF
static ADDRESS_MAP_START( seattle_map, ADDRESS_SPACE_PROGRAM, 32 )
ADDRESS_MAP_UNMAP_HIGH
AM_RANGE(0x00000000, 0x007fffff) AM_RAM AM_BASE(&rambase) // wg3dh only has 4MB; sfrush, blitz99 8MB
AM_RANGE(0x08000000, 0x08ffffff) AM_DEVREADWRITE(VOODOO_GRAPHICS, "voodoo", voodoo_r, seattle_voodoo_w)
AM_RANGE(0x08000000, 0x08ffffff) AM_DEVREAD(VOODOO_GRAPHICS, "voodoo", voodoo_r) AM_WRITE(seattle_voodoo_w)
AM_RANGE(0x0a000000, 0x0a0003ff) AM_DEVREADWRITE(IDE_CONTROLLER, "ide", ide_controller32_r, ide_controller32_w)
AM_RANGE(0x0a00040c, 0x0a00040f) AM_NOP // IDE-related, but annoying
AM_RANGE(0x0a000f00, 0x0a000f07) AM_DEVREADWRITE(IDE_CONTROLLER, "ide", ide_bus_master32_r, ide_bus_master32_w)

4
src/mame/drivers/segaorun.c
View File

@ -276,7 +276,7 @@ static void log_unknown_ppi_read( running_machine *machine, unsigned port )
{
static const char ports[] = "ABC";
logerror("%06X:read from 8255 port %c\n", cpu_get_pc(machine->activecpu), ports[port]);
logerror("%06X:read from 8255 port %c\n", cpu_get_pc(machine->cpu[0]), ports[port]);
}
@ -284,7 +284,7 @@ static void log_unknown_ppi_write( running_machine *machine, unsigned port, UINT
{
static const char ports[] = "ABC";
logerror("%06X:write %02X to 8255 port %c\n", cpu_get_pc(machine->activecpu), data, ports[port]);
logerror("%06X:write %02X to 8255 port %c\n", cpu_get_pc(machine->cpu[0]), data, ports[port]);
}

2
src/mame/drivers/segas32.c
View File

@ -449,7 +449,7 @@ static void int_control_w(const address_space *space, int offset, UINT8 data)
{
int duration;
// logerror("%06X:int_control_w(%X) = %02X\n", cpu_get_pc(machine->activecpu), offset, data);
// logerror("%06X:int_control_w(%X) = %02X\n", cpu_get_pc(space->cpu), offset, data);
switch (offset)
{
case 0:

24
src/mame/drivers/seibuspi.c
View File

@ -695,12 +695,12 @@ static int fifoout_read_request = 0;
static UINT8 sb_coin_latch = 0;
static UINT8 z80_fifoout_pop(running_machine *machine)
static UINT8 z80_fifoout_pop(const address_space *space)
{
UINT8 r;
if (fifoout_wpos == fifoout_rpos)
{
logerror("Sound FIFOOUT underflow at %08X\n", cpu_get_pc(machine->activecpu));
logerror("Sound FIFOOUT underflow at %08X\n", cpu_get_pc(space->cpu));
}
r = fifoout_data[fifoout_rpos++];
if(fifoout_rpos == FIFO_SIZE)
@ -716,7 +716,7 @@ static UINT8 z80_fifoout_pop(running_machine *machine)
return r;
}
static void z80_fifoout_push(running_machine *machine, UINT8 data)
static void z80_fifoout_push(const address_space *space, UINT8 data)
{
fifoout_data[fifoout_wpos++] = data;
if (fifoout_wpos == FIFO_SIZE)
@ -725,18 +725,18 @@ static void z80_fifoout_push(running_machine *machine, UINT8 data)
}
if(fifoout_wpos == fifoout_rpos)
{
fatalerror("Sound FIFOOUT overflow at %08X", cpu_get_pc(machine->activecpu));
fatalerror("Sound FIFOOUT overflow at %08X", cpu_get_pc(space->cpu));
}
fifoout_read_request = 1;
}
static UINT8 z80_fifoin_pop(running_machine *machine)
static UINT8 z80_fifoin_pop(const address_space *space)
{
UINT8 r;
if (fifoin_wpos == fifoin_rpos)
{
fatalerror("Sound FIFOIN underflow at %08X", cpu_get_pc(machine->activecpu));
fatalerror("Sound FIFOIN underflow at %08X", cpu_get_pc(space->cpu));
}
r = fifoin_data[fifoin_rpos++];
if(fifoin_rpos == FIFO_SIZE)
@ -752,7 +752,7 @@ static UINT8 z80_fifoin_pop(running_machine *machine)
return r;
}
static void z80_fifoin_push(running_machine *machine, UINT8 data)
static void z80_fifoin_push(const address_space *space, UINT8 data)
{
fifoin_data[fifoin_wpos++] = data;
if(fifoin_wpos == FIFO_SIZE)
@ -761,7 +761,7 @@ static void z80_fifoin_push(running_machine *machine, UINT8 data)
}
if(fifoin_wpos == fifoin_rpos)
{
fatalerror("Sound FIFOIN overflow at %08X", cpu_get_pc(machine->activecpu));
fatalerror("Sound FIFOIN overflow at %08X", cpu_get_pc(space->cpu));
}
fifoin_read_request = 1;
@ -785,7 +785,7 @@ static WRITE8_HANDLER( sb_coin_w )
static READ32_HANDLER( sound_fifo_r )
{
UINT8 r = z80_fifoout_pop(space->machine);
UINT8 r = z80_fifoout_pop(space);
return r;
}
@ -793,7 +793,7 @@ static READ32_HANDLER( sound_fifo_r )
static WRITE32_HANDLER( sound_fifo_w )
{
if( ACCESSING_BITS_0_7 ) {
z80_fifoin_push(space->machine, data & 0xff);
z80_fifoin_push(space, data & 0xff);
}
}
@ -934,14 +934,14 @@ static WRITE32_HANDLER( spi_6295_1_w )
static READ8_HANDLER( z80_soundfifo_r )
{
UINT8 r = z80_fifoin_pop(space->machine);
UINT8 r = z80_fifoin_pop(space);
return r;
}
static WRITE8_HANDLER( z80_soundfifo_w )
{
z80_fifoout_push(space->machine, data);
z80_fifoout_push(space, data);
}
static READ8_HANDLER( z80_soundfifo_status_r )

8
src/mame/drivers/seta.c
View File

@ -1322,7 +1322,7 @@ static struct st_chip {
/*------------------------------
uppdate timer
------------------------------*/
static void uPD71054_update_timer( running_machine *machine, int no )
static void uPD71054_update_timer( running_machine *machine, const device_config *cpu, int no )
{
UINT16 max = uPD71054.max[no]&0xffff;
@ -1332,7 +1332,7 @@ static void uPD71054_update_timer( running_machine *machine, int no )
} else {
timer_adjust_oneshot( uPD71054.timer[no], attotime_never, no);
logerror( "CPU #0 PC %06X: uPD71054 error, timer %d duration is 0\n",
cpu_get_pc(machine->activecpu), no );
(cpu != NULL) ? cpu_get_pc(cpu) : -1, no );
}
}
@ -1344,7 +1344,7 @@ static void uPD71054_update_timer( running_machine *machine, int no )
static TIMER_CALLBACK( uPD71054_timer_callback )
{
cpu_set_input_line(machine->cpu[0], 4, HOLD_LINE );
uPD71054_update_timer( machine, param );
uPD71054_update_timer( machine, NULL, param );
}
@ -1390,7 +1390,7 @@ static WRITE16_HANDLER( timer_regs_w )
uPD71054.max[offset] = (uPD71054.max[offset]&0x00ff)+(data<<8);
}
if( uPD71054.max[offset] != 0 ) {
uPD71054_update_timer( space->machine, offset );
uPD71054_update_timer( space->machine, space->cpu, offset );
}
break;
case 0x0003:

24
src/mame/drivers/smstrv.c
View File

@ -293,44 +293,44 @@ INPUT_PORTS_EXTERN(ettrivia);
static READ8_DEVICE_HANDLER( r1 )
{
int pc = cpu_get_pc(device->machine->activecpu);
int pc = cpu_get_pc(device->machine->cpu[0]);
if(pc != 0x81cb)
printf("r1 @ %X\n",cpu_get_pc(device->machine->activecpu));
printf("r1 @ %X\n",pc);
return mame_rand(device->machine);
}
static READ8_DEVICE_HANDLER( r2 )
{
int pc = cpu_get_pc(device->machine->activecpu);
int pc = cpu_get_pc(device->machine->cpu[0]);
if(pc != 0x81cb)
printf("r2 @ %X\n",cpu_get_pc(device->machine->activecpu));
printf("r2 @ %X\n",pc);
return mame_rand(device->machine);
}
static READ8_DEVICE_HANDLER( r3 )
{
int pc = cpu_get_pc(device->machine->activecpu);
int pc = cpu_get_pc(device->machine->cpu[0]);
if(pc != 0x81cb && pc != 0x90fa && pc != 0x911b && pc != 0x90d3 && pc != 0x90c4)
printf("r3 @ %X\n",cpu_get_pc(device->machine->activecpu));
printf("r3 @ %X\n",pc);
return mame_rand(device->machine) & ~1; //with 1 jumps back (infinite loop): a status ready for something?
}
static READ8_DEVICE_HANDLER( r4 )
{
int pc = cpu_get_pc(device->machine->activecpu);
int pc = cpu_get_pc(device->machine->cpu[0]);
if(pc != 0x81cb)
printf("r4 @ %X\n",cpu_get_pc(device->machine->activecpu));
printf("r4 @ %X\n",pc);
return mame_rand(device->machine);
}
static READ8_DEVICE_HANDLER( r5 )
{
int pc = cpu_get_pc(device->machine->activecpu);
int pc = cpu_get_pc(device->machine->cpu[0]);
if(pc != 0x81cb)
printf("r5 @ %X\n",cpu_get_pc(device->machine->activecpu));
printf("r5 @ %X\n",pc);
return mame_rand(device->machine);
}
static READ8_DEVICE_HANDLER( r6 )
{
int pc = cpu_get_pc(device->machine->activecpu);
int pc = cpu_get_pc(device->machine->cpu[0]);
if(pc != 0x81cb)
printf("r6 @ %X\n",cpu_get_pc(device->machine->activecpu));
printf("r6 @ %X\n",pc);
return mame_rand(device->machine);
}

16
src/mame/drivers/stv.c
View File

@ -460,7 +460,7 @@ static void system_reset()
/*Order is surely wrong but whatever...*/
}
static UINT8 stv_SMPC_r8 (running_machine *machine, int offset)
static UINT8 stv_SMPC_r8 (const address_space *space, int offset)
{
int return_data;
@ -471,7 +471,7 @@ static UINT8 stv_SMPC_r8 (running_machine *machine, int offset)
return_data = 0x20 ^ 0xff;
if (offset == 0x75)//PDR1 read
return_data = input_port_read(machine, "DSW1");
return_data = input_port_read(space->machine, "DSW1");
if (offset == 0x77)//PDR2 read
return_data= (0xfe | eeprom_read_bit());
@ -479,9 +479,9 @@ static UINT8 stv_SMPC_r8 (running_machine *machine, int offset)
// if (offset == 0x33) //country code
// return_data = input_port_read(machine, "FAKE");
if (cpu_get_pc(machine->activecpu)==0x060020E6) return_data = 0x10;//???
if (cpu_get_pc(space->cpu)==0x060020E6) return_data = 0x10;//???
//if(LOG_SMPC) logerror ("cpu %s (PC=%08X) SMPC: Read from Byte Offset %02x Returns %02x\n", space->cpu->tag, cpu_get_pc(machine->activecpu), offset, return_data);
//if(LOG_SMPC) logerror ("cpu %s (PC=%08X) SMPC: Read from Byte Offset %02x Returns %02x\n", space->cpu->tag, cpu_get_pc(space->cpu), offset, return_data);
return return_data;
@ -721,10 +721,10 @@ static READ32_HANDLER ( stv_SMPC_r32 )
/* registers are all byte accesses, convert here */
offset = offset << 2; // multiply offset by 4
if (ACCESSING_BITS_24_31) { byte = 0; readdata = stv_SMPC_r8(space->machine, offset+byte) << 24; }
if (ACCESSING_BITS_16_23) { byte = 1; readdata = stv_SMPC_r8(space->machine, offset+byte) << 16; }
if (ACCESSING_BITS_8_15) { byte = 2; readdata = stv_SMPC_r8(space->machine, offset+byte) << 8; }
if (ACCESSING_BITS_0_7) { byte = 3; readdata = stv_SMPC_r8(space->machine, offset+byte) << 0; }
if (ACCESSING_BITS_24_31) { byte = 0; readdata = stv_SMPC_r8(space, offset+byte) << 24; }
if (ACCESSING_BITS_16_23) { byte = 1; readdata = stv_SMPC_r8(space, offset+byte) << 16; }
if (ACCESSING_BITS_8_15) { byte = 2; readdata = stv_SMPC_r8(space, offset+byte) << 8; }
if (ACCESSING_BITS_0_7) { byte = 3; readdata = stv_SMPC_r8(space, offset+byte) << 0; }
return readdata;
}

24
src/mame/drivers/taitojc.c
View File

@ -505,7 +505,7 @@ static WRITE32_HANDLER (jc_control1_w)
static UINT8 mcu_comm_reg_r(int reg)
static UINT8 mcu_comm_reg_r(const address_space *space, int reg)
{
UINT8 r = 0;
@ -523,7 +523,7 @@ static UINT8 mcu_comm_reg_r(int reg)
}
default:
{
//mame_printf_debug("hc11_reg_r: %02X at %08X\n", reg, cpu_get_pc(machine->activecpu));
//mame_printf_debug("hc11_reg_r: %02X at %08X\n", reg, cpu_get_pc(space->cpu));
break;
}
}
@ -531,7 +531,7 @@ static UINT8 mcu_comm_reg_r(int reg)
return r;
}
static void mcu_comm_reg_w(int reg, UINT8 data)
static void mcu_comm_reg_w(const address_space *space, int reg, UINT8 data)
{
switch (reg)
{
@ -548,7 +548,7 @@ static void mcu_comm_reg_w(int reg, UINT8 data)
}
default:
{
//mame_printf_debug("hc11_reg_w: %02X, %02X at %08X\n", reg, data, cpu_get_pc(machine->activecpu));
//mame_printf_debug("hc11_reg_w: %02X, %02X at %08X\n", reg, data, cpu_get_pc(space->cpu));
break;
}
}
@ -561,19 +561,19 @@ static READ32_HANDLER(mcu_comm_r)
if (ACCESSING_BITS_24_31)
{
r |= mcu_comm_reg_r(reg + 0) << 24;
r |= mcu_comm_reg_r(space, reg + 0) << 24;
}
if (ACCESSING_BITS_16_23)
{
r |= mcu_comm_reg_r(reg + 1) << 16;
r |= mcu_comm_reg_r(space, reg + 1) << 16;
}
if (ACCESSING_BITS_8_15)
{
r |= mcu_comm_reg_r(reg + 2) << 8;
r |= mcu_comm_reg_r(space, reg + 2) << 8;
}
if (ACCESSING_BITS_0_7)
{
r |= mcu_comm_reg_r(reg + 3) << 0;
r |= mcu_comm_reg_r(space, reg + 3) << 0;
}
return r;
@ -585,19 +585,19 @@ static WRITE32_HANDLER(mcu_comm_w)
if (ACCESSING_BITS_24_31)
{
mcu_comm_reg_w(reg + 0, (data >> 24) & 0xff);
mcu_comm_reg_w(space, reg + 0, (data >> 24) & 0xff);
}
if (ACCESSING_BITS_16_23)
{
mcu_comm_reg_w(reg + 1, (data >> 16) & 0xff);
mcu_comm_reg_w(space, reg + 1, (data >> 16) & 0xff);
}
if (ACCESSING_BITS_8_15)
{
mcu_comm_reg_w(reg + 2, (data >> 8) & 0xff);
mcu_comm_reg_w(space, reg + 2, (data >> 8) & 0xff);
}
if (ACCESSING_BITS_0_7)
{
mcu_comm_reg_w(reg + 3, (data >> 0) & 0xff);
mcu_comm_reg_w(space, reg + 3, (data >> 0) & 0xff);
}
}

74
src/mame/drivers/taitowlf.c
View File

@ -121,14 +121,14 @@ static WRITE32_DEVICE_HANDLER(at32_dma8237_2_w)
// Intel 82439TX System Controller (MXTC)
static UINT8 mxtc_config_reg[256];
static UINT8 mxtc_config_r(int function, int reg)
static UINT8 mxtc_config_r(const device_config *busdevice, const device_config *device, int function, int reg)
{
// mame_printf_debug("MXTC: read %d, %02X\n", function, reg);
return mxtc_config_reg[reg];
}
static void mxtc_config_w(running_machine *machine, int function, int reg, UINT8 data)
static void mxtc_config_w(const device_config *busdevice, const device_config *device, int function, int reg, UINT8 data)
{
// mame_printf_debug("MXTC: write %d, %02X, %02X at %08X\n", function, reg, data, cpu_get_pc(machine->activecpu));
@ -138,11 +138,11 @@ static void mxtc_config_w(running_machine *machine, int function, int reg, UINT8
{
if (data & 0x10) // enable RAM access to region 0xf0000 - 0xfffff
{
memory_set_bankptr(machine, 1, bios_ram);
memory_set_bankptr(busdevice->machine, 1, bios_ram);
}
else // disable RAM access (reads go to BIOS ROM)
{
memory_set_bankptr(machine, 1, memory_region(machine, "user1") + 0x30000);
memory_set_bankptr(busdevice->machine, 1, memory_region(busdevice->machine, "user1") + 0x30000);
}
break;
}
@ -161,102 +161,102 @@ static void intel82439tx_init(void)
mxtc_config_reg[0x65] = 0x02;
}
static UINT32 intel82439tx_pci_r(int function, int reg, UINT32 mem_mask)
static UINT32 intel82439tx_pci_r(const device_config *busdevice, const device_config *device, int function, int reg, UINT32 mem_mask)
{
UINT32 r = 0;
if (ACCESSING_BITS_24_31)
{
r |= mxtc_config_r(function, reg + 3) << 24;
r |= mxtc_config_r(busdevice, device, function, reg + 3) << 24;
}
if (ACCESSING_BITS_16_23)
{
r |= mxtc_config_r(function, reg + 2) << 16;
r |= mxtc_config_r(busdevice, device, function, reg + 2) << 16;
}
if (ACCESSING_BITS_8_15)
{
r |= mxtc_config_r(function, reg + 1) << 8;
r |= mxtc_config_r(busdevice, device, function, reg + 1) << 8;
}
if (ACCESSING_BITS_0_7)
{
r |= mxtc_config_r(function, reg + 0) << 0;
r |= mxtc_config_r(busdevice, device, function, reg + 0) << 0;
}
return r;
}
static void intel82439tx_pci_w(int function, int reg, UINT32 data, UINT32 mem_mask)
static void intel82439tx_pci_w(const device_config *busdevice, const device_config *device, int function, int reg, UINT32 data, UINT32 mem_mask)
{
if (ACCESSING_BITS_24_31)
{
mxtc_config_w(Machine, function, reg + 3, (data >> 24) & 0xff);
mxtc_config_w(busdevice, device, function, reg + 3, (data >> 24) & 0xff);
}
if (ACCESSING_BITS_16_23)
{
mxtc_config_w(Machine, function, reg + 2, (data >> 16) & 0xff);
mxtc_config_w(busdevice, device, function, reg + 2, (data >> 16) & 0xff);
}
if (ACCESSING_BITS_8_15)
{
mxtc_config_w(Machine, function, reg + 1, (data >> 8) & 0xff);
mxtc_config_w(busdevice, device, function, reg + 1, (data >> 8) & 0xff);
}
if (ACCESSING_BITS_0_7)
{
mxtc_config_w(Machine, function, reg + 0, (data >> 0) & 0xff);
mxtc_config_w(busdevice, device, function, reg + 0, (data >> 0) & 0xff);
}
}
// Intel 82371AB PCI-to-ISA / IDE bridge (PIIX4)
static UINT8 piix4_config_reg[4][256];
static UINT8 piix4_config_r(int function, int reg)
static UINT8 piix4_config_r(const device_config *busdevice, const device_config *device, int function, int reg)
{
// mame_printf_debug("PIIX4: read %d, %02X\n", function, reg);
return piix4_config_reg[function][reg];
}
static void piix4_config_w(int function, int reg, UINT8 data)
static void piix4_config_w(const device_config *busdevice, const device_config *device, int function, int reg, UINT8 data)
{
// mame_printf_debug("PIIX4: write %d, %02X, %02X at %08X\n", function, reg, data, cpu_get_pc(machine->activecpu));
piix4_config_reg[function][reg] = data;
}
static UINT32 intel82371ab_pci_r(int function, int reg, UINT32 mem_mask)
static UINT32 intel82371ab_pci_r(const device_config *busdevice, const device_config *device, int function, int reg, UINT32 mem_mask)
{
UINT32 r = 0;
if (ACCESSING_BITS_24_31)
{
r |= piix4_config_r(function, reg + 3) << 24;
r |= piix4_config_r(busdevice, device, function, reg + 3) << 24;
}
if (ACCESSING_BITS_16_23)
{
r |= piix4_config_r(function, reg + 2) << 16;
r |= piix4_config_r(busdevice, device, function, reg + 2) << 16;
}
if (ACCESSING_BITS_8_15)
{
r |= piix4_config_r(function, reg + 1) << 8;
r |= piix4_config_r(busdevice, device, function, reg + 1) << 8;
}
if (ACCESSING_BITS_0_7)
{
r |= piix4_config_r(function, reg + 0) << 0;
r |= piix4_config_r(busdevice, device, function, reg + 0) << 0;
}
return r;
}
static void intel82371ab_pci_w(int function, int reg, UINT32 data, UINT32 mem_mask)
static void intel82371ab_pci_w(const device_config *busdevice, const device_config *device, int function, int reg, UINT32 data, UINT32 mem_mask)
{
if (ACCESSING_BITS_24_31)
{
piix4_config_w(function, reg + 3, (data >> 24) & 0xff);
piix4_config_w(busdevice, device, function, reg + 3, (data >> 24) & 0xff);
}
if (ACCESSING_BITS_16_23)
{
piix4_config_w(function, reg + 2, (data >> 16) & 0xff);
piix4_config_w(busdevice, device, function, reg + 2, (data >> 16) & 0xff);
}
if (ACCESSING_BITS_8_15)
{
piix4_config_w(function, reg + 1, (data >> 8) & 0xff);
piix4_config_w(busdevice, device, function, reg + 1, (data >> 8) & 0xff);
}
if (ACCESSING_BITS_0_7)
{
piix4_config_w(function, reg + 0, (data >> 0) & 0xff);
piix4_config_w(busdevice, device, function, reg + 0, (data >> 0) & 0xff);
}
}
@ -459,7 +459,7 @@ static ADDRESS_MAP_START(taitowlf_io, ADDRESS_SPACE_IO, 32)
AM_RANGE(0x0278, 0x027b) AM_WRITE(pnp_config_w)
AM_RANGE(0x03f0, 0x03ff) AM_DEVREADWRITE(IDE_CONTROLLER, "ide", fdc_r, fdc_w)
AM_RANGE(0x0a78, 0x0a7b) AM_WRITE(pnp_data_w)
AM_RANGE(0x0cf8, 0x0cff) AM_READWRITE(pci_32le_r, pci_32le_w)
AM_RANGE(0x0cf8, 0x0cff) AM_DEVREADWRITE(PCI_BUS, "pcibus", pci_32le_r, pci_32le_w)
ADDRESS_MAP_END
/*****************************************************************************/
@ -611,6 +611,10 @@ static MACHINE_DRIVER_START(taitowlf)
MDRV_MACHINE_START(taitowlf)
MDRV_MACHINE_RESET(taitowlf)
MDRV_PCI_BUS_ADD("pcibus", 0)
MDRV_PCI_BUS_DEVICE(0, NULL, NULL, intel82439tx_pci_r, intel82439tx_pci_w)
MDRV_PCI_BUS_DEVICE(7, NULL, NULL, intel82371ab_pci_r, intel82371ab_pci_w)
MDRV_DEVICE_ADD( "pit8254", PIT8254 )
MDRV_DEVICE_CONFIG( taitowlf_pit8254_config )
@ -646,18 +650,6 @@ static MACHINE_DRIVER_START(taitowlf)
MACHINE_DRIVER_END
static const struct pci_device_info intel82439tx =
{
intel82439tx_pci_r,
intel82439tx_pci_w
};
static const struct pci_device_info intel82371ab =
{
intel82371ab_pci_r,
intel82371ab_pci_w
};
static void set_gate_a20(int a20)
{
cpu_set_input_line(Machine->cpu[0], INPUT_LINE_A20, a20);
@ -695,10 +687,6 @@ static DRIVER_INIT( taitowlf )
intel82439tx_init();
pci_init();
pci_add_device(0, 0, &intel82439tx);
pci_add_device(0, 7, &intel82371ab);
kbdc8042_init(&at8042);
}

53
src/mame/drivers/viper.c
View File

@ -49,7 +49,7 @@ static VIDEO_UPDATE(viper)
/*****************************************************************************/
static UINT32 mpc8240_regs[256/4];
static UINT32 mpc8240_pci_r(int function, int reg, UINT32 mem_mask)
static UINT32 mpc8240_pci_r(const device_config *busdevice, const device_config *device, int function, int reg, UINT32 mem_mask)
{
// printf("MPC8240: PCI read %d, %02X, %08X\n", function, reg, mem_mask);
@ -60,31 +60,31 @@ static UINT32 mpc8240_pci_r(int function, int reg, UINT32 mem_mask)
return mpc8240_regs[reg/4];
}
static void mpc8240_pci_w(int function, int reg, UINT32 data, UINT32 mem_mask)
static void mpc8240_pci_w(const device_config *busdevice, const device_config *device, int function, int reg, UINT32 data, UINT32 mem_mask)
{
// printf("MPC8240: PCI write %d, %02X, %08X, %08X\n", function, reg, data, mem_mask);
COMBINE_DATA(mpc8240_regs + (reg/4));
}
static READ64_HANDLER( pci_config_addr_r )
static READ64_DEVICE_HANDLER( pci_config_addr_r )
{
return pci_64be_r(space, 0, U64(0x00000000ffffffff));
return pci_64be_r(device, 0, U64(0x00000000ffffffff));
}
static WRITE64_HANDLER( pci_config_addr_w )
static WRITE64_DEVICE_HANDLER( pci_config_addr_w )
{
pci_64be_w(space, 0, data, U64(0x00000000ffffffff));
pci_64be_w(device, 0, data, U64(0x00000000ffffffff));
}
static READ64_HANDLER( pci_config_data_r )
static READ64_DEVICE_HANDLER( pci_config_data_r )
{
return pci_64be_r(space, 1, U64(0xffffffff00000000)) << 32;
return pci_64be_r(device, 1, U64(0xffffffff00000000)) << 32;
}
static WRITE64_HANDLER( pci_config_data_w )
static WRITE64_DEVICE_HANDLER( pci_config_data_w )
{
pci_64be_w(space, 1, data >> 32, U64(0xffffffff00000000));
pci_64be_w(device, 1, data >> 32, U64(0xffffffff00000000));
}
@ -409,7 +409,7 @@ static WRITE64_HANDLER(unk1b_w)
}
static UINT32 voodoo3_pci_reg[0x100];
static UINT32 voodoo3_pci_r(int function, int reg, UINT32 mem_mask)
static UINT32 voodoo3_pci_r(const device_config *busdevice, const device_config *device, int function, int reg, UINT32 mem_mask)
{
switch (reg)
{
@ -443,12 +443,12 @@ static UINT32 voodoo3_pci_r(int function, int reg, UINT32 mem_mask)
}
default:
fatalerror("voodoo3_pci_r: %08X at %08X", reg, cpu_get_pc(Machine->activecpu));
fatalerror("voodoo3_pci_r: %08X at %08X", reg, cpu_get_pc(device->machine->cpu[0]));
}
return 0;
}
static void voodoo3_pci_w(int function, int reg, UINT32 data, UINT32 mem_mask)
static void voodoo3_pci_w(const device_config *busdevice, const device_config *device, int function, int reg, UINT32 data, UINT32 mem_mask)
{
// printf("voodoo3_pci_w: %08X, %08X\n", reg, data);
@ -511,7 +511,7 @@ static void voodoo3_pci_w(int function, int reg, UINT32 data, UINT32 mem_mask)
}
default:
fatalerror("voodoo3_pci_w: %08X, %08X at %08X", data, reg, cpu_get_pc(Machine->activecpu));
fatalerror("voodoo3_pci_w: %08X, %08X at %08X", data, reg, cpu_get_pc(device->machine->cpu[0]));
}
}
@ -556,8 +556,8 @@ static ADDRESS_MAP_START(viper_map, ADDRESS_SPACE_PROGRAM, 64)
AM_RANGE(0x82000000, 0x83ffffff) AM_DEVREADWRITE32(VOODOO_GRAPHICS, "voodoo", banshee_r, banshee_w, U64(0xffffffffffffffff))
AM_RANGE(0x84000000, 0x85ffffff) AM_DEVREADWRITE32(VOODOO_GRAPHICS, "voodoo", banshee_fb_r, banshee_fb_w, U64(0xffffffffffffffff))
AM_RANGE(0xfe800000, 0xfe8000ff) AM_DEVREADWRITE32(VOODOO_GRAPHICS, "voodoo", banshee_io_r, banshee_io_w, U64(0xffffffffffffffff))
AM_RANGE(0xfec00000, 0xfedfffff) AM_READWRITE(pci_config_addr_r, pci_config_addr_w)
AM_RANGE(0xfee00000, 0xfeefffff) AM_READWRITE(pci_config_data_r, pci_config_data_w)
AM_RANGE(0xfec00000, 0xfedfffff) AM_DEVREADWRITE(PCI_BUS, "pcibus", pci_config_addr_r, pci_config_addr_w)
AM_RANGE(0xfee00000, 0xfeefffff) AM_DEVREADWRITE(PCI_BUS, "pcibus", pci_config_data_r, pci_config_data_w)
AM_RANGE(0xff300000, 0xff300fff) AM_DEVREADWRITE(IDE_CONTROLLER, "ide", ata_r, ata_w)
AM_RANGE(0xffe10000, 0xffe10007) AM_READ(unk1_r)
AM_RANGE(0xffe30000, 0xffe31fff) AM_DEVREADWRITE8(M48T58,"m48t58",timekeeper_r, timekeeper_w, U64(0xffffffffffffffff))
@ -606,6 +606,10 @@ static MACHINE_DRIVER_START(viper)
MDRV_MACHINE_RESET(viper)
MDRV_PCI_BUS_ADD("pcibus", 0)
MDRV_PCI_BUS_DEVICE(0, NULL, NULL, mpc8240_pci_r, mpc8240_pci_w)
MDRV_PCI_BUS_DEVICE(12, VOODOO_GRAPHICS, "voodoo", voodoo3_pci_r, voodoo3_pci_w)
MDRV_IDE_CONTROLLER_ADD("ide", ide_interrupt)
MDRV_3DFX_VOODOO_3_ADD("voodoo", STD_VOODOO_3_CLOCK, 16, "main")
@ -629,28 +633,13 @@ MACHINE_DRIVER_END
/*****************************************************************************/
static const struct pci_device_info mpc8240 =
{
mpc8240_pci_r,
mpc8240_pci_w
};
static const struct pci_device_info voodoo3 =
{
voodoo3_pci_r,
voodoo3_pci_w
};
static DRIVER_INIT(viper)
{
pci_init();
pci_add_device(0, 0, &mpc8240);
pci_add_device(0, 12, &voodoo3);
}
static DRIVER_INIT(vipercf)
{
const device_config *ide = device_list_find_by_tag(machine->config->devicelist, IDE_CONTROLLER, "ide");
const device_config *ide = devtag_get_device(machine, IDE_CONTROLLER, "ide");
DRIVER_INIT_CALL(viper);

227
src/mame/machine/model1.c
View File

@ -13,6 +13,8 @@ enum {MAT_STACK_SIZE = 32};
int model1_dump;
static offs_t pushpc;
static int fifoin_rpos, fifoin_wpos;
static UINT32 fifoin_data[FIFO_SIZE];
static int model1_swa;
@ -36,11 +38,11 @@ static UINT16 ram_adr, ram_latch[2], ram_scanadr;
static UINT32 *ram_data;
static float tgp_vr_base[4];
static UINT32 fifoout_pop(void)
static UINT32 fifoout_pop(const address_space *space)
{
UINT32 v;
if(fifoout_wpos == fifoout_rpos) {
fatalerror("TGP FIFOOUT underflow (%x)", cpu_get_pc(Machine->activecpu));
fatalerror("TGP FIFOOUT underflow (%x)", cpu_get_pc(space->cpu));
}
v = fifoout_data[fifoout_rpos++];
if(fifoout_rpos == FIFO_SIZE)
@ -82,9 +84,9 @@ static UINT32 fifoin_pop(void)
return v;
}
static void fifoin_push(UINT32 data)
static void fifoin_push(const address_space *space, UINT32 data)
{
// logerror("TGP FIFOIN write %08x (%x)\n", data, cpu_get_pc(Machine->activecpu));
// logerror("TGP FIFOIN write %08x (%x)\n", data, cpu_get_pc(space->cpu));
fifoin_data[fifoin_wpos++] = data;
if(fifoin_wpos == FIFO_SIZE)
fifoin_wpos = 0;
@ -148,7 +150,7 @@ static void fadd(void)
float a = fifoin_pop_f();
float b = fifoin_pop_f();
float r = a+b;
logerror("TGP fadd %f+%f=%f (%x)\n", a, b, r, cpu_get_pc(Machine->activecpu));
logerror("TGP fadd %f+%f=%f (%x)\n", a, b, r, pushpc);
fifoout_push_f(r);
next_fn();
}
@ -159,7 +161,7 @@ static void fsub(void)
float b = fifoin_pop_f();
float r = a-b;
model1_dump = 1;
logerror("TGP fsub %f-%f=%f (%x)\n", a, b, r, cpu_get_pc(Machine->activecpu));
logerror("TGP fsub %f-%f=%f (%x)\n", a, b, r, pushpc);
fifoout_push_f(r);
next_fn();
}
@ -169,7 +171,7 @@ static void fmul(void)
float a = fifoin_pop_f();
float b = fifoin_pop_f();
float r = a*b;
logerror("TGP fmul %f*%f=%f (%x)\n", a, b, r, cpu_get_pc(Machine->activecpu));
logerror("TGP fmul %f*%f=%f (%x)\n", a, b, r, pushpc);
fifoout_push_f(r);
next_fn();
}
@ -180,7 +182,7 @@ static void fdiv(void)
float b = fifoin_pop_f();
// float r = !b ? 1e39 : a/b;
float r = !b ? 0 : a * (1/b);
logerror("TGP fdiv %f/%f=%f (%x)\n", a, b, r, cpu_get_pc(Machine->activecpu));
logerror("TGP fdiv %f/%f=%f (%x)\n", a, b, r, pushpc);
fifoout_push_f(r);
next_fn();
}
@ -191,7 +193,7 @@ static void matrix_push(void)
memcpy(mat_stack[mat_stack_pos], cmat, sizeof(cmat));
mat_stack_pos++;
}
logerror("TGP matrix_push (depth=%d, pc=%x)\n", mat_stack_pos, cpu_get_pc(Machine->activecpu));
logerror("TGP matrix_push (depth=%d, pc=%x)\n", mat_stack_pos, pushpc);
next_fn();
}
@ -201,7 +203,7 @@ static void matrix_pop(void)
mat_stack_pos--;
memcpy(cmat, mat_stack[mat_stack_pos], sizeof(cmat));
}
logerror("TGP matrix_pop (depth=%d, pc=%x)\n", mat_stack_pos, cpu_get_pc(Machine->activecpu));
logerror("TGP matrix_pop (depth=%d, pc=%x)\n", mat_stack_pos, pushpc);
next_fn();
}
@ -212,13 +214,13 @@ static void matrix_write(void)
cmat[i] = fifoin_pop_f();
logerror("TGP matrix_write %f, %f, %f, %f, %f, %f, %f, %f, %f, %f, %f, %f) (%x)\n",
cmat[0], cmat[1], cmat[2], cmat[3], cmat[4], cmat[5], cmat[6], cmat[7], cmat[8], cmat[9], cmat[10], cmat[11],
cpu_get_pc(Machine->activecpu));
pushpc);
next_fn();
}
static void clear_stack(void)
{
logerror("TGP clear_stack (%x)\n", cpu_get_pc(Machine->activecpu));
logerror("TGP clear_stack (%x)\n", pushpc);
mat_stack_pos = 0;
next_fn();
}
@ -238,7 +240,7 @@ static void matrix_mul(void)
float j = fifoin_pop_f();
float k = fifoin_pop_f();
float l = fifoin_pop_f();
logerror("TGP matrix_mul %f, %f, %f, %f, %f, %f, %f, %f, %f, %f, %f, %f (%x)\n", a, b, c, d, e, f, g, h, i, j, k, l, cpu_get_pc(Machine->activecpu));
logerror("TGP matrix_mul %f, %f, %f, %f, %f, %f, %f, %f, %f, %f, %f, %f (%x)\n", a, b, c, d, e, f, g, h, i, j, k, l, pushpc);
m[0] = a*cmat[0] + b*cmat[3] + c*cmat[6];
m[1] = a*cmat[1] + b*cmat[4] + c*cmat[7];
m[2] = a*cmat[2] + b*cmat[5] + c*cmat[8];
@ -260,7 +262,7 @@ static void anglev(void)
{
float a = fifoin_pop_f();
float b = fifoin_pop_f();
logerror("TGP anglev %f, %f (%x)\n", a, b, cpu_get_pc(Machine->activecpu));
logerror("TGP anglev %f, %f (%x)\n", a, b, pushpc);
if(!b) {
if(a>=0)
fifoout_push(0);
@ -296,7 +298,7 @@ static void f11(void)
(void)g;
(void)h;
(void)i;
logerror("TGP f11 %f, %f, %f, %f, %f, %f, %f, %f, %f (%x)\n", a, b, c, d, e, f, g, h, i, cpu_get_pc(Machine->activecpu));
logerror("TGP f11 %f, %f, %f, %f, %f, %f, %f, %f, %f (%x)\n", a, b, c, d, e, f, g, h, i, pushpc);
fifoout_push_f(0);
fifoout_push_f(0);
fifoout_push_f(0);
@ -309,7 +311,7 @@ static void normalize(void)
float b = fifoin_pop_f();
float c = fifoin_pop_f();
float n = (a*a+b*b+c*c) / sqrt(a*a+b*b+c*c);
logerror("TGP normalize %f, %f, %f (%x)\n", a, b, c, cpu_get_pc(Machine->activecpu));
logerror("TGP normalize %f, %f, %f (%x)\n", a, b, c, pushpc);
fifoout_push_f(a/n);
fifoout_push_f(b/n);
fifoout_push_f(c/n);
@ -320,7 +322,7 @@ static void acc_seti(void)
{
INT32 a = fifoin_pop();
model1_dump = 1;
logerror("TGP acc_seti %d (%x)\n", a, cpu_get_pc(Machine->activecpu));
logerror("TGP acc_seti %d (%x)\n", a, pushpc);
acc = a;
next_fn();
}
@ -328,7 +330,7 @@ static void acc_seti(void)
static void track_select(void)
{
INT32 a = fifoin_pop();
logerror("TGP track_select %d (%x)\n", a, cpu_get_pc(Machine->activecpu));
logerror("TGP track_select %d (%x)\n", a, pushpc);
tgp_vr_select = a;
next_fn();
}
@ -345,7 +347,7 @@ static void f14(void)
static void f15_swa(void)
{
logerror("TGP f15_swa (%x)\n", cpu_get_pc(Machine->activecpu));
logerror("TGP f15_swa (%x)\n", pushpc);
next_fn();
}
@ -356,7 +358,7 @@ static void anglep(void)
float b = fifoin_pop_f();
float c = fifoin_pop_f();
float d = fifoin_pop_f();
logerror("TGP anglep %f, %f, %f, %f (%x)\n", a, b, c, d, cpu_get_pc(Machine->activecpu));
logerror("TGP anglep %f, %f, %f, %f (%x)\n", a, b, c, d, pushpc);
c = a - c;
d = b - d;
if(!d) {
@ -376,7 +378,7 @@ static void anglep(void)
static void matrix_ident(void)
{
logerror("TGP matrix_ident (%x)\n", cpu_get_pc(Machine->activecpu));
logerror("TGP matrix_ident (%x)\n", pushpc);
memset(cmat, 0, sizeof(cmat));
cmat[0] = 1.0;
cmat[4] = 1.0;
@ -388,7 +390,7 @@ static void matrix_read(void)
{
int i;
logerror("TGP matrix_read (%f, %f, %f, %f, %f, %f, %f, %f, %f, %f, %f, %f) (%x)\n",
cmat[0], cmat[1], cmat[2], cmat[3], cmat[4], cmat[5], cmat[6], cmat[7], cmat[8], cmat[9], cmat[10], cmat[11], cpu_get_pc(Machine->activecpu));
cmat[0], cmat[1], cmat[2], cmat[3], cmat[4], cmat[5], cmat[6], cmat[7], cmat[8], cmat[9], cmat[10], cmat[11], pushpc);
for(i=0; i<12; i++)
fifoout_push_f(cmat[i]);
next_fn();
@ -411,7 +413,7 @@ static void matrix_scale(void)
float a = fifoin_pop_f();
float b = fifoin_pop_f();
float c = fifoin_pop_f();
logerror("TGP matrix_scale %f, %f, %f (%x)\n", a, b, c, cpu_get_pc(Machine->activecpu));
logerror("TGP matrix_scale %f, %f, %f (%x)\n", a, b, c, pushpc);
cmat[0] *= a;
cmat[1] *= a;
cmat[2] *= a;
@ -430,7 +432,7 @@ static void matrix_rotx(void)
float s = tsin(a);
float c = tcos(a);
float t1, t2;
logerror("TGP matrix_rotx %d (%x)\n", a, cpu_get_pc(Machine->activecpu));
logerror("TGP matrix_rotx %d (%x)\n", a, pushpc);
t1 = cmat[3];
t2 = cmat[6];
cmat[3] = c*t1-s*t2;
@ -453,7 +455,7 @@ static void matrix_roty(void)
float c = tcos(a);
float t1, t2;
logerror("TGP matrix_roty %d (%x)\n", a, cpu_get_pc(Machine->activecpu));
logerror("TGP matrix_roty %d (%x)\n", a, pushpc);
t1 = cmat[6];
t2 = cmat[0];
cmat[6] = c*t1-s*t2;
@ -476,7 +478,7 @@ static void matrix_rotz(void)
float c = tcos(a);
float t1, t2;
logerror("TGP matrix_rotz %d (%x)\n", a, cpu_get_pc(Machine->activecpu));
logerror("TGP matrix_rotz %d (%x)\n", a, pushpc);
t1 = cmat[0];
t2 = cmat[3];
cmat[0] = c*t1-s*t2;
@ -498,7 +500,7 @@ static void track_read_quad(void)
UINT32 a = fifoin_pop();
int offd;
logerror("TGP track_read_quad %d (%x)\n", a, cpu_get_pc(Machine->activecpu));
logerror("TGP track_read_quad %d (%x)\n", a, pushpc);
offd = tgp_data[0x20+tgp_vr_select] + 16*a;
fifoout_push(tgp_data[offd]);
@ -532,7 +534,7 @@ static void f24_swa(void)
(void)e;
(void)f;
(void)g;
logerror("TGP f24_swa %f, %f, %f, %f, %f, %f, %x (%x)\n", a, b, c, d, e, f, g, cpu_get_pc(Machine->activecpu));
logerror("TGP f24_swa %f, %f, %f, %f, %f, %f, %x (%x)\n", a, b, c, d, e, f, g, pushpc);
fifoout_push_f(0);
next_fn();
}
@ -542,7 +544,7 @@ static void transform_point(void)
float x = fifoin_pop_f();
float y = fifoin_pop_f();
float z = fifoin_pop_f();
logerror("TGP transform_point %f, %f, %f (%x)\n", x, y, z, cpu_get_pc(Machine->activecpu));
logerror("TGP transform_point %f, %f, %f (%x)\n", x, y, z, pushpc);
fifoout_push_f(cmat[0]*x+cmat[3]*y+cmat[6]*z+cmat[9]);
fifoout_push_f(cmat[1]*x+cmat[4]*y+cmat[7]*z+cmat[10]);
@ -553,7 +555,7 @@ static void transform_point(void)
static void fcos_m1(void)
{
INT16 a = fifoin_pop();
logerror("TGP fcos %d (%x)\n", a, cpu_get_pc(Machine->activecpu));
logerror("TGP fcos %d (%x)\n", a, pushpc);
fifoout_push_f(tcos(a));
next_fn();
}
@ -561,7 +563,7 @@ static void fcos_m1(void)
static void fsin_m1(void)
{
INT16 a = fifoin_pop();
logerror("TGP fsin %d (%x)\n", a, cpu_get_pc(Machine->activecpu));
logerror("TGP fsin %d (%x)\n", a, pushpc);
fifoout_push_f(tsin(a));
next_fn();
}
@ -570,7 +572,7 @@ static void fcosm_m1(void)
{
INT16 a = fifoin_pop();
float b = fifoin_pop_f();
logerror("TGP fcosm %d, %f (%x)\n", a, b, cpu_get_pc(Machine->activecpu));
logerror("TGP fcosm %d, %f (%x)\n", a, b, pushpc);
fifoout_push_f(b*tcos(a));
next_fn();
}
@ -580,7 +582,7 @@ static void fsinm_m1(void)
INT16 a = fifoin_pop();
float b = fifoin_pop_f();
model1_dump = 1;
logerror("TGP fsinm %d, %f (%x)\n", a, b, cpu_get_pc(Machine->activecpu));
logerror("TGP fsinm %d, %f (%x)\n", a, b, pushpc);
fifoout_push_f(b*tsin(a));
next_fn();
}
@ -593,7 +595,7 @@ static void distance3(void)
float d = fifoin_pop_f();
float e = fifoin_pop_f();
float f = fifoin_pop_f();
logerror("TGP distance3 (%f, %f, %f), (%f, %f, %f) (%x)\n", a, b, c, d, e, f, cpu_get_pc(Machine->activecpu));
logerror("TGP distance3 (%f, %f, %f), (%f, %f, %f) (%x)\n", a, b, c, d, e, f, pushpc);
a -= d;
b -= e;
c -= f;
@ -604,7 +606,7 @@ static void distance3(void)
static void ftoi(void)
{
float a = fifoin_pop_f();
logerror("TGP ftoi %f (%x)\n", a, cpu_get_pc(Machine->activecpu));
logerror("TGP ftoi %f (%x)\n", a, pushpc);
fifoout_push((int)a);
next_fn();
}
@ -612,7 +614,7 @@ static void ftoi(void)
static void itof(void)
{
INT32 a = fifoin_pop();
logerror("TGP itof %d (%x)\n", a, cpu_get_pc(Machine->activecpu));
logerror("TGP itof %d (%x)\n", a, pushpc);
fifoout_push_f(a);
next_fn();
}
@ -620,14 +622,14 @@ static void itof(void)
static void acc_set(void)
{
float a = fifoin_pop_f();
logerror("TGP acc_set %f (%x)\n", a, cpu_get_pc(Machine->activecpu));
logerror("TGP acc_set %f (%x)\n", a, pushpc);
acc = a;
next_fn();
}
static void acc_get(void)
{
logerror("TGP acc_get (%x)\n", cpu_get_pc(Machine->activecpu));
logerror("TGP acc_get (%x)\n", pushpc);
fifoout_push_f(acc);
next_fn();
}
@ -635,7 +637,7 @@ static void acc_get(void)
static void acc_add(void)
{
float a = fifoin_pop_f();
logerror("TGP acc_add %f (%x)\n", a, cpu_get_pc(Machine->activecpu));
logerror("TGP acc_add %f (%x)\n", a, pushpc);
acc += a;
next_fn();
}
@ -643,7 +645,7 @@ static void acc_add(void)
static void acc_sub(void)
{
float a = fifoin_pop_f();
logerror("TGP acc_sub %f (%x)\n", a, cpu_get_pc(Machine->activecpu));
logerror("TGP acc_sub %f (%x)\n", a, pushpc);
acc -= a;
next_fn();
}
@ -651,7 +653,7 @@ static void acc_sub(void)
static void acc_mul(void)
{
float a = fifoin_pop_f();
logerror("TGP acc_mul %f (%x)\n", a, cpu_get_pc(Machine->activecpu));
logerror("TGP acc_mul %f (%x)\n", a, pushpc);
acc *= a;
next_fn();
}
@ -659,7 +661,7 @@ static void acc_mul(void)
static void acc_div(void)
{
float a = fifoin_pop_f();
logerror("TGP acc_div %f (%x)\n", a, cpu_get_pc(Machine->activecpu));
logerror("TGP acc_div %f (%x)\n", a, pushpc);
acc /= a;
next_fn();
}
@ -672,7 +674,7 @@ static void f42(void)
(void)a;
(void)b;
(void)c;
logerror("TGP f42 %f, %f, %f (%x)\n", a, b, c, cpu_get_pc(Machine->activecpu));
logerror("TGP f42 %f, %f, %f (%x)\n", a, b, c, pushpc);
// fifoout_push_f((mame_rand(Machine) % 1000) - 500);
fifoout_push_f(0);
fifoout_push_f(0);
@ -695,7 +697,7 @@ static void xyz2rqf(void)
(void)a;
(void)b;
(void)c;
logerror("TGP xyz2rqf %f, %f, %f (%x)\n", a, b, c, cpu_get_pc(Machine->activecpu));
logerror("TGP xyz2rqf %f, %f, %f (%x)\n", a, b, c, pushpc);
fifoout_push_f((a*a+b*b+c*c)/sqrt(a*a+b*b+c*c));
norm = sqrt(a*a+c*c);
if(!c) {
@ -738,7 +740,7 @@ static void f43(void)
(void)d;
(void)e;
(void)f;
logerror("TGP f43 %f, %f, %f, %f, %f, %f (%x)\n", a, b, c, d, e, f, cpu_get_pc(Machine->activecpu));
logerror("TGP f43 %f, %f, %f, %f, %f, %f (%x)\n", a, b, c, d, e, f, pushpc);
fifoout_push_f(0);
fifoout_push_f(0);
fifoout_push_f(0);
@ -754,7 +756,7 @@ static void f43_swa(void)
(void)a;
(void)b;
(void)c;
logerror("TGP f43_swa %f, %d, %d (%x)\n", a, b, c, cpu_get_pc(Machine->activecpu));
logerror("TGP f43_swa %f, %d, %d (%x)\n", a, b, c, pushpc);
fifoout_push_f(0);
fifoout_push_f(0);
fifoout_push_f(0);
@ -765,7 +767,7 @@ static void f44(void)
{
float a = fifoin_pop_f();
(void)a;
logerror("TGP f44 %f (%x)\n", a, cpu_get_pc(Machine->activecpu));
logerror("TGP f44 %f (%x)\n", a, pushpc);
fifoout_push_f(0);
fifoout_push_f(0);
fifoout_push_f(0);
@ -779,7 +781,7 @@ static void matrix_sdir(void)
float c = fifoin_pop_f();
float norm = sqrt(a*a+b*b+c*c);
float t[9], m[9];
logerror("TGP matrix_sdir %f, %f, %f (%x)\n", a, b, c, cpu_get_pc(Machine->activecpu));
logerror("TGP matrix_sdir %f, %f, %f (%x)\n", a, b, c, pushpc);
memset(t, 0, sizeof(t));
@ -826,7 +828,7 @@ static void f45(void)
{
float a = fifoin_pop_f();
(void)a;
logerror("TGP f45 %f (%x)\n", a, cpu_get_pc(Machine->activecpu));
logerror("TGP f45 %f (%x)\n", a, pushpc);
fifoout_push_f(0);
next_fn();
}
@ -836,7 +838,7 @@ static void vlength(void)
float a = fifoin_pop_f() - tgp_vr_base[0];
float b = fifoin_pop_f() - tgp_vr_base[1];
float c = fifoin_pop_f() - tgp_vr_base[2];
logerror("TGP vlength %f, %f, %f (%x)\n", a, b, c, cpu_get_pc(Machine->activecpu));
logerror("TGP vlength %f, %f, %f (%x)\n", a, b, c, pushpc);
a = (a*a+b*b+c*c);
b = 1/sqrt(a);
@ -851,7 +853,7 @@ static void f47(void)
float a = fifoin_pop_f();
float b = fifoin_pop_f();
float c = fifoin_pop_f();
logerror("TGP f47 %f, %f, %f (%x)\n", a, b, c, cpu_get_pc(Machine->activecpu));
logerror("TGP f47 %f, %f, %f (%x)\n", a, b, c, pushpc);
fifoout_push_f(a+c);
fifoout_push_f(b+c);
next_fn();
@ -863,7 +865,7 @@ static void track_read_info(void)
UINT16 a = fifoin_pop();
int offd;
logerror("TGP track_read_info %d (%x)\n", a, cpu_get_pc(Machine->activecpu));
logerror("TGP track_read_info %d (%x)\n", a, pushpc);
offd = tgp_data[0x20+tgp_vr_select] + 16*a;
fifoout_push(tgp_data[offd+15]);
@ -884,7 +886,7 @@ static void colbox_set(void)
float j = fifoin_pop_f();
float k = fifoin_pop_f();
float l = fifoin_pop_f();
logerror("TGP colbox_set %f, %f, %f, %f, %f, %f, %f, %f, %f, %f, %f, %f (%x)\n", a, b, c, d, e, f, g, h, i, j, k, l, cpu_get_pc(Machine->activecpu));
logerror("TGP colbox_set %f, %f, %f, %f, %f, %f, %f, %f, %f, %f, %f, %f (%x)\n", a, b, c, d, e, f, g, h, i, j, k, l, pushpc);
tgp_vr_cbox[ 0] = a;
tgp_vr_cbox[ 1] = b;
tgp_vr_cbox[ 2] = c;
@ -908,7 +910,7 @@ static void colbox_test(void)
(void)a;
(void)b;
(void)c;
logerror("TGP colbox_test %f, %f, %f (%x)\n", a, b, c, cpu_get_pc(Machine->activecpu));
logerror("TGP colbox_test %f, %f, %f (%x)\n", a, b, c, pushpc);
// #### Wrong, need to check with the tgp_vr_cbox coordinates
// Game only test sign, negative = collision
@ -930,7 +932,7 @@ static void f49_swa(void)
(void)d;
(void)e;
(void)f;
logerror("TGP f49_swa %f, %f, %f, %f, %f, %f (%x)\n", a, b, c, d, e, f, cpu_get_pc(Machine->activecpu));
logerror("TGP f49_swa %f, %f, %f, %f, %f, %f (%x)\n", a, b, c, d, e, f, pushpc);
next_fn();
}
@ -944,14 +946,14 @@ static void f50_swa(void)
(void)b;
(void)c;
(void)d;
logerror("TGP f50_swa %f, %f, %f, %f (%x)\n", a, b, c, d, cpu_get_pc(Machine->activecpu));
logerror("TGP f50_swa %f, %f, %f, %f (%x)\n", a, b, c, d, pushpc);
fifoout_push_f(d);
next_fn();
}
static void f52(void)
{
logerror("TGP f52 (%x)\n", cpu_get_pc(Machine->activecpu));
logerror("TGP f52 (%x)\n", pushpc);
next_fn();
}
@ -964,7 +966,7 @@ static void matrix_rdir(void)
float t1, t2;
(void)b;
logerror("TGP matrix_rdir %f, %f, %f (%x)\n", a, b, c, cpu_get_pc(Machine->activecpu));
logerror("TGP matrix_rdir %f, %f, %f (%x)\n", a, b, c, pushpc);
if(!norm) {
c = 1;
@ -1017,7 +1019,7 @@ static void track_lookup(void)
UINT32 behaviour, entry;
float height;
logerror("TGP track_lookup %f, 0x%x, %f, %f (%x)\n", a, b, c, d, cpu_get_pc(Machine->activecpu));
logerror("TGP track_lookup %f, 0x%x, %f, %f (%x)\n", a, b, c, d, pushpc);
offi = tgp_data[0x10+tgp_vr_select] + b;
offd = tgp_data[0x20+tgp_vr_select];
@ -1079,14 +1081,14 @@ static void f56(void)
(void)f;
(void)g;
logerror("TGP f56 %f, %f, %f, %f, %f, %f, %d (%x)\n", a, b, c, d, e, f, g, cpu_get_pc(Machine->activecpu));
logerror("TGP f56 %f, %f, %f, %f, %f, %f, %d (%x)\n", a, b, c, d, e, f, g, pushpc);
fifoout_push(0);
next_fn();
}
static void f57(void)
{
logerror("TGP f57 (%x)\n", cpu_get_pc(Machine->activecpu));
logerror("TGP f57 (%x)\n", pushpc);
fifoout_push_f(0);
fifoout_push_f(0);
fifoout_push_f(0);
@ -1095,7 +1097,7 @@ static void f57(void)
static void matrix_readt(void)
{
logerror("TGP matrix_readt (%x)\n", cpu_get_pc(Machine->activecpu));
logerror("TGP matrix_readt (%x)\n", pushpc);
fifoout_push_f(cmat[9]);
fifoout_push_f(cmat[10]);
fifoout_push_f(cmat[11]);
@ -1104,14 +1106,14 @@ static void matrix_readt(void)
static void acc_geti(void)
{
logerror("TGP acc_geti (%x)\n", cpu_get_pc(Machine->activecpu));
logerror("TGP acc_geti (%x)\n", pushpc);
fifoout_push((int)acc);
next_fn();
}
static void f60(void)
{
logerror("TGP f60 (%x)\n", cpu_get_pc(Machine->activecpu));
logerror("TGP f60 (%x)\n", pushpc);
fifoout_push_f(0);
fifoout_push_f(0);
fifoout_push_f(0);
@ -1123,7 +1125,7 @@ static void col_setcirc(void)
float a = fifoin_pop_f();
float b = fifoin_pop_f();
float c = fifoin_pop_f();
logerror("TGP col_setcirc %f, %f, %f (%x)\n", a, b, c, cpu_get_pc(Machine->activecpu));
logerror("TGP col_setcirc %f, %f, %f (%x)\n", a, b, c, pushpc);
tgp_vr_circx = a;
tgp_vr_circy = b;
tgp_vr_circrad = c;
@ -1135,7 +1137,7 @@ static void col_testpt(void)
float x, y;
float a = fifoin_pop_f();
float b = fifoin_pop_f();
logerror("TGP col_testpt %f, %f (%x)\n", a, b, cpu_get_pc(Machine->activecpu));
logerror("TGP col_testpt %f, %f (%x)\n", a, b, pushpc);
x = a - tgp_vr_circx;
y = b - tgp_vr_circy;
fifoout_push_f(((x*x+y*y)/sqrt(x*x+y*y)) - tgp_vr_circrad);
@ -1148,7 +1150,7 @@ static void push_and_ident(void)
memcpy(mat_stack[mat_stack_pos], cmat, sizeof(cmat));
mat_stack_pos++;
}
logerror("TGP push_and_ident (depth=%d, pc=%x)\n", mat_stack_pos, cpu_get_pc(Machine->activecpu));
logerror("TGP push_and_ident (depth=%d, pc=%x)\n", mat_stack_pos, pushpc);
memset(cmat, 0, sizeof(cmat));
cmat[0] = 1.0;
cmat[4] = 1.0;
@ -1174,7 +1176,7 @@ static void catmull_rom(void)
float m2, m3;
float w1, w2, w3, w4;
logerror("TGP catmull_rom %f, %f, %f, %f, %f, %f, %f, %f, %f, %f, %f, %f, %f (%x)\n", a, b, c, d, e, f, g, h, i, j, k, l, m, cpu_get_pc(Machine->activecpu));
logerror("TGP catmull_rom %f, %f, %f, %f, %f, %f, %f, %f, %f, %f, %f, %f, %f (%x)\n", a, b, c, d, e, f, g, h, i, j, k, l, m, pushpc);
m2 = m*m;
m3 = m*m*m;
@ -1196,7 +1198,7 @@ static void distance(void)
float b = fifoin_pop_f();
float c = fifoin_pop_f();
float d = fifoin_pop_f();
logerror("TGP distance (%f, %f), (%f, %f) (%x)\n", a, b, c, d, cpu_get_pc(Machine->activecpu));
logerror("TGP distance (%f, %f), (%f, %f) (%x)\n", a, b, c, d, pushpc);
c -= a;
d -= b;
fifoout_push_f((c*c+d*d)/sqrt(c*c+d*d));
@ -1210,7 +1212,7 @@ static void car_move(void)
float c = fifoin_pop_f();
float d = fifoin_pop_f();
float dx, dy;
logerror("TGP car_move (%d, %f), (%f, %f) (%x)\n", a, b, c, d, cpu_get_pc(Machine->activecpu));
logerror("TGP car_move (%d, %f), (%f, %f) (%x)\n", a, b, c, d, pushpc);
dx = b*tsin(a);
dy = b*tcos(a);
@ -1238,7 +1240,7 @@ static void cpa(void)
float j = fifoin_pop_f();
float k = fifoin_pop_f();
float l = fifoin_pop_f();
logerror("TGP cpa %f, %f, %f, %f, %f, %f, %f, %f, %f, %f, %f, %f (%x)\n", a, b, c, d, e, f, g, h, i, j, k, l, cpu_get_pc(Machine->activecpu));
logerror("TGP cpa %f, %f, %f, %f, %f, %f, %f, %f, %f, %f, %f, %f (%x)\n", a, b, c, d, e, f, g, h, i, j, k, l, pushpc);
dv_x = (b-a) - (d-c);
dv_y = (f-e) - (h-g);
@ -1273,7 +1275,7 @@ static void vmat_store(void)
memcpy(mat_vector[a], cmat, sizeof(cmat));
else
logerror("TGP ERROR bad vector index\n");
logerror("TGP vmat_store %d (%x)\n", a, cpu_get_pc(Machine->activecpu));
logerror("TGP vmat_store %d (%x)\n", a, pushpc);
next_fn();
}
@ -1284,7 +1286,7 @@ static void vmat_restore(void)
memcpy(cmat, mat_vector[a], sizeof(cmat));
else
logerror("TGP ERROR bad vector index\n");
logerror("TGP vmat_restore %d (%x)\n", a, cpu_get_pc(Machine->activecpu));
logerror("TGP vmat_restore %d (%x)\n", a, pushpc);
next_fn();
}
@ -1307,14 +1309,14 @@ static void vmat_mul(void)
mat_vector[b][11] = mat_vector[a][ 9]*cmat[2] + mat_vector[a][10]*cmat[5] + mat_vector[a][11]*cmat[8] + cmat[11];
} else
logerror("TGP ERROR bad vector index\n");
logerror("TGP vmat_mul %d, %d (%x)\n", a, b, cpu_get_pc(Machine->activecpu));
logerror("TGP vmat_mul %d, %d (%x)\n", a, b, pushpc);
next_fn();
}
static void vmat_read(void)
{
UINT32 a = fifoin_pop();
logerror("TGP vmat_read %d (%x)\n", a, cpu_get_pc(Machine->activecpu));
logerror("TGP vmat_read %d (%x)\n", a, pushpc);
if(a<21) {
int i;
for(i=0; i<12; i++)
@ -1330,7 +1332,7 @@ static void vmat_read(void)
static void matrix_rtrans(void)
{
logerror("TGP matrix_rtrans (%x)\n", cpu_get_pc(Machine->activecpu));
logerror("TGP matrix_rtrans (%x)\n", pushpc);
fifoout_push_f(cmat[ 9]);
fifoout_push_f(cmat[10]);
fifoout_push_f(cmat[11]);
@ -1339,7 +1341,7 @@ static void matrix_rtrans(void)
static void matrix_unrot(void)
{
logerror("TGP matrix_unrot (%x)\n", cpu_get_pc(Machine->activecpu));
logerror("TGP matrix_unrot (%x)\n", pushpc);
memset(cmat, 0, 9*sizeof(cmat[0]));
cmat[0] = 1.0;
cmat[4] = 1.0;
@ -1349,7 +1351,7 @@ static void matrix_unrot(void)
static void f80(void)
{
logerror("TGP f80 (%x)\n", cpu_get_pc(Machine->activecpu));
logerror("TGP f80 (%x)\n", pushpc);
// cmat[9] = cmat[10] = cmat[11] = 0;
next_fn();
}
@ -1358,7 +1360,7 @@ static void vmat_save(void)
{
UINT32 a = fifoin_pop();
int i;
logerror("TGP vmat_save 0x%x (%x)\n", a, cpu_get_pc(Machine->activecpu));
logerror("TGP vmat_save 0x%x (%x)\n", a, pushpc);
for(i=0; i<16; i++)
memcpy(ram_data+a+0x10*i, mat_vector[i], sizeof(cmat));
next_fn();
@ -1368,7 +1370,7 @@ static void vmat_load(void)
{
UINT32 a = fifoin_pop();
int i;
logerror("TGP vmat_load 0x%x (%x)\n", a, cpu_get_pc(Machine->activecpu));
logerror("TGP vmat_load 0x%x (%x)\n", a, pushpc);
for(i=0; i<16; i++)
memcpy(mat_vector[i], ram_data+a+0x10*i, sizeof(cmat));
next_fn();
@ -1377,7 +1379,7 @@ static void vmat_load(void)
static void ram_setadr(void)
{
ram_scanadr = fifoin_pop() - 0x8000;
logerror("TGP f0 ram_setadr 0x%x (%x)\n", ram_scanadr+0x8000, cpu_get_pc(Machine->activecpu));
logerror("TGP f0 ram_setadr 0x%x (%x)\n", ram_scanadr+0x8000, pushpc);
next_fn();
}
@ -1389,7 +1391,7 @@ static void groundbox_test(void)
float b = fifoin_pop_f();
float c = fifoin_pop_f();
logerror("TGP groundbox_test %f, %f, %f (%x)\n", a, b, c, cpu_get_pc(Machine->activecpu));
logerror("TGP groundbox_test %f, %f, %f (%x)\n", a, b, c, pushpc);
x = cmat[0]*a+cmat[3]*b+cmat[6]*c+cmat[9];
y = cmat[1]*a+cmat[4]*b+cmat[7]*c+cmat[10];
z = cmat[2]*a+cmat[5]*b+cmat[8]*c+cmat[11];
@ -1413,7 +1415,7 @@ static void f89(void)
(void)a;
(void)b;
(void)c;
logerror("TGP list set base 0x%x, 0x%x, %d, length=%d (%x)\n", a, b, c, d, cpu_get_pc(Machine->activecpu));
logerror("TGP list set base 0x%x, 0x%x, %d, length=%d (%x)\n", a, b, c, d, pushpc);
list_length = d;
next_fn();
}
@ -1428,7 +1430,7 @@ static void f92(void)
(void)b;
(void)c;
(void)d;
logerror("TGP f92 %f, %f, %f, %f (%x)\n", a, b, c, d, cpu_get_pc(Machine->activecpu));
logerror("TGP f92 %f, %f, %f, %f (%x)\n", a, b, c, d, pushpc);
next_fn();
}
@ -1436,7 +1438,7 @@ static void f93(void)
{
float a = fifoin_pop_f();
(void)a;
logerror("TGP f93 %f (%x)\n", a, cpu_get_pc(Machine->activecpu));
logerror("TGP f93 %f (%x)\n", a, pushpc);
next_fn();
}
@ -1444,7 +1446,7 @@ static void f94(void)
{
UINT32 a = fifoin_pop();
(void)a;
logerror("TGP f94 %d (%x)\n", a, cpu_get_pc(Machine->activecpu));
logerror("TGP f94 %d (%x)\n", a, pushpc);
next_fn();
}
@ -1452,7 +1454,7 @@ static void vmat_flatten(void)
{
int i;
float m[12];
logerror("TGP vmat_flatten (%x)\n", cpu_get_pc(Machine->activecpu));
logerror("TGP vmat_flatten (%x)\n", pushpc);
for(i=0; i<16; i++) {
memcpy(m, mat_vector[i], sizeof(cmat));
@ -1477,7 +1479,7 @@ static void vmat_flatten(void)
static void vmat_load1(void)
{
UINT32 a = fifoin_pop();
logerror("TGP vmat_load1 0x%x (%x)\n", a, cpu_get_pc(Machine->activecpu));
logerror("TGP vmat_load1 0x%x (%x)\n", a, pushpc);
memcpy(cmat, ram_data+a, sizeof(cmat));
next_fn();
}
@ -1487,7 +1489,7 @@ static void ram_trans(void)
float a = ram_get_f();
float b = ram_get_f();
float c = ram_get_f();
logerror("TGP ram_trans (%x)\n", cpu_get_pc(Machine->activecpu));
logerror("TGP ram_trans (%x)\n", pushpc);
cmat[ 9] += cmat[0]*a+cmat[3]*b+cmat[6]*c;
cmat[10] += cmat[1]*a+cmat[4]*b+cmat[7]*c;
cmat[11] += cmat[2]*a+cmat[5]*b+cmat[8]*c;
@ -1500,7 +1502,7 @@ static void f98_load(void)
for(i=0; i<list_length; i++) {
float f = fifoin_pop_f();
(void)f;
logerror("TGP load list (%2d/%2d) %f (%x)\n", i, list_length, f, cpu_get_pc(Machine->activecpu));
logerror("TGP load list (%2d/%2d) %f (%x)\n", i, list_length, f, pushpc);
}
next_fn();
}
@ -1509,21 +1511,21 @@ static void f98(void)
{
UINT32 a = fifoin_pop();
(void)a;
logerror("TGP load list start %d (%x)\n", a, cpu_get_pc(Machine->activecpu));
logerror("TGP load list start %d (%x)\n", a, pushpc);
fifoin_cbcount = list_length;
fifoin_cb = f98_load;
}
static void f99(void)
{
logerror("TGP f99 (%x)\n", cpu_get_pc(Machine->activecpu));
logerror("TGP f99 (%x)\n", pushpc);
next_fn();
}
static void f100(void)
{
int i;
logerror("TGP f100 get list (%x)\n", cpu_get_pc(Machine->activecpu));
logerror("TGP f100 get list (%x)\n", pushpc);
for(i=0; i<list_length; i++)
fifoout_push_f((mame_rand(Machine) % 1000)/100.0);
next_fn();
@ -1538,7 +1540,7 @@ static void groundbox_set(void)
float e = fifoin_pop_f();
float f = fifoin_pop_f();
float g = fifoin_pop_f();
logerror("TGP groundbox_set %f, %f, %f, %f, %f, %f, %f (%x)\n", a, b, c, d, e, f, g, cpu_get_pc(Machine->activecpu));
logerror("TGP groundbox_set %f, %f, %f, %f, %f, %f, %f (%x)\n", a, b, c, d, e, f, g, pushpc);
tgp_vf_xmin = e;
tgp_vf_xmax = d;
tgp_vf_zmin = g;
@ -1565,7 +1567,7 @@ static void f102(void)
ccount++;
logerror("TGP f0 mve_calc %f, %f, %f, %f, %f, %d, %d, %d (%d) (%x)\n", a, b, c, d, e, f, g, h, ccount, cpu_get_pc(Machine->activecpu));
logerror("TGP f0 mve_calc %f, %f, %f, %f, %f, %d, %d, %d (%d) (%x)\n", a, b, c, d, e, f, g, h, ccount, pushpc);
px = u2f(ram_data[ram_scanadr+0x16]);
py = u2f(ram_data[ram_scanadr+0x17]);
@ -1606,7 +1608,7 @@ static void f102(void)
static void f103(void)
{
ram_scanadr = fifoin_pop() - 0x8000;
logerror("TGP f0 mve_setadr 0x%x (%x)\n", ram_scanadr, cpu_get_pc(Machine->activecpu));
logerror("TGP f0 mve_setadr 0x%x (%x)\n", ram_scanadr, pushpc);
ram_get_i();
next_fn();
}
@ -1812,7 +1814,7 @@ static const struct function ftab_swa[] = {
static void dump(void)
{
logerror("TGP FIFOIN write %08x (%x)\n", fifoin_pop(), cpu_get_pc(Machine->activecpu));
logerror("TGP FIFOIN write %08x (%x)\n", fifoin_pop(), pushpc);
fifoin_cbcount = 1;
fifoin_cb = dump;
}
@ -1834,7 +1836,7 @@ static void function_get_vf(void)
if(!fifoin_cbcount)
fifoin_cb();
} else {
logerror("TGP function %d unimplemented (%x)\n", f, cpu_get_pc(Machine->activecpu));
logerror("TGP function %d unimplemented (%x)\n", f, pushpc);
fifoin_cbcount = 1;
fifoin_cb = dump;
}
@ -1857,7 +1859,7 @@ static void function_get_swa(void)
if(!fifoin_cbcount)
fifoin_cb();
} else {
logerror("TGP function %d unimplemented (%x)\n", f, cpu_get_pc(Machine->activecpu));
logerror("TGP function %d unimplemented (%x)\n", f, pushpc);
fifoin_cbcount = 1;
fifoin_cb = dump;
}
@ -1867,7 +1869,7 @@ READ16_HANDLER( model1_tgp_copro_r )
{
static UINT32 cur;
if(!offset) {
cur = fifoout_pop();
cur = fifoout_pop(space);
return cur;
} else
return cur >> 16;
@ -1878,7 +1880,8 @@ WRITE16_HANDLER( model1_tgp_copro_w )
static UINT32 cur;
if(offset) {
cur = (cur & 0x0000ffff) | (data << 16);
fifoin_push(cur);
pushpc = cpu_get_pc(space->cpu);
fifoin_push(space, cur);
} else
cur = (cur & 0xffff0000) | data;
}
@ -1896,7 +1899,7 @@ WRITE16_HANDLER( model1_tgp_copro_adr_w )
READ16_HANDLER( model1_tgp_copro_ram_r )
{
if(!offset) {
logerror("TGP f0 ram read %04x, %08x (%f) (%x)\n", ram_adr, ram_data[ram_adr], u2f(ram_data[ram_adr]), cpu_get_pc(Machine->activecpu));
logerror("TGP f0 ram read %04x, %08x (%f) (%x)\n", ram_adr, ram_data[ram_adr], u2f(ram_data[ram_adr]), cpu_get_pc(space->cpu));
return ram_data[ram_adr];
} else
return ram_data[ram_adr++] >> 16;
@ -1907,7 +1910,7 @@ WRITE16_HANDLER( model1_tgp_copro_ram_w )
COMBINE_DATA(ram_latch+offset);
if(offset) {
UINT32 v = ram_latch[0]|(ram_latch[1]<<16);
logerror("TGP f0 ram write %04x, %08x (%f) (%x)\n", ram_adr, v, u2f(v), cpu_get_pc(Machine->activecpu));
logerror("TGP f0 ram write %04x, %08x (%f) (%x)\n", ram_adr, v, u2f(v), cpu_get_pc(space->cpu));
ram_data[ram_adr] = v;
ram_adr++;
}
@ -1977,7 +1980,7 @@ void model1_vr_tgp_reset( void )
}
/* FIFO */
static int copro_fifoin_pop(UINT32 *result)
static int copro_fifoin_pop(const device_config *device, UINT32 *result)
{
UINT32 r;
@ -2000,11 +2003,11 @@ static int copro_fifoin_pop(UINT32 *result)
return 1;
}
static void copro_fifoin_push(UINT32 data)
static void copro_fifoin_push(const address_space *space, UINT32 data)
{
if (copro_fifoin_num == FIFO_SIZE)
{
fatalerror("Copro FIFOIN overflow (at %08X)", cpu_get_pc(Machine->activecpu));
fatalerror("Copro FIFOIN overflow (at %08X)", cpu_get_pc(space->cpu));
return;
}
@ -2018,7 +2021,7 @@ static void copro_fifoin_push(UINT32 data)
copro_fifoin_num++;
}
static UINT32 copro_fifoout_pop(void)
static UINT32 copro_fifoout_pop(const address_space *space)
{
UINT32 r;
@ -2028,7 +2031,7 @@ static UINT32 copro_fifoout_pop(void)
extern void v60_stall(void);
v60_stall();
timer_call_after_resynch(Machine, NULL, 0, NULL);
timer_call_after_resynch(space->machine, NULL, 0, NULL);
return 0;
}
@ -2045,11 +2048,11 @@ static UINT32 copro_fifoout_pop(void)
return r;
}
static void copro_fifoout_push(UINT32 data)
static void copro_fifoout_push(const device_config *device, UINT32 data)
{
if (copro_fifoout_num == FIFO_SIZE)
{
fatalerror("Copro FIFOOUT overflow (at %08X)", cpu_get_pc(Machine->activecpu));
fatalerror("Copro FIFOOUT overflow (at %08X)", cpu_get_pc(device));
return;
}
@ -2133,7 +2136,7 @@ READ16_HANDLER( model1_vr_tgp_r )
if (!offset)
{
cur = copro_fifoout_pop();
cur = copro_fifoout_pop(space);
return cur;
}
else
@ -2147,7 +2150,7 @@ WRITE16_HANDLER( model1_vr_tgp_w )
if (offset)
{
cur = (cur & 0x0000ffff) | (data << 16);
copro_fifoin_push(cur);
copro_fifoin_push(space, cur);
}
else
cur = (cur & 0xffff0000) | data;

8
src/mame/machine/namcoio.c
View File

@ -1047,11 +1047,11 @@ static void namco_06xx_ctrl_w(running_machine *machine, int chip,int data)
READ8_HANDLER( namco_06xx_0_data_r ) { return namco_06xx_data_r(space->machine,0,offset); }
READ8_HANDLER( namco_06xx_1_data_r ) { return namco_06xx_data_r(space->machine,1,offset); }
READ8_HANDLER( namco_06xx_0_data_r ) { return namco_06xx_data_r(space->machine,0,offset); }
READ8_HANDLER( namco_06xx_1_data_r ) { return namco_06xx_data_r(space->machine,1,offset); }
WRITE8_HANDLER( namco_06xx_0_data_w ) { namco_06xx_data_w(space->machine,0,offset,data); }
WRITE8_HANDLER( namco_06xx_1_data_w ) { namco_06xx_data_w(space->machine,1,offset,data); }
READ8_HANDLER( namco_06xx_0_ctrl_r ) { return namco_06xx_ctrl_r(space->machine,0); }
READ8_HANDLER( namco_06xx_1_ctrl_r ) { return namco_06xx_ctrl_r(space->machine,1); }
READ8_HANDLER( namco_06xx_0_ctrl_r ) { return namco_06xx_ctrl_r(space->machine,0); }
READ8_HANDLER( namco_06xx_1_ctrl_r ) { return namco_06xx_ctrl_r(space->machine,1); }
WRITE8_HANDLER( namco_06xx_0_ctrl_w ) { namco_06xx_ctrl_w(space->machine, 0,data); }
WRITE8_HANDLER( namco_06xx_1_ctrl_w ) { namco_06xx_ctrl_w(space->machine, 1,data); }