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pofo.cpp: Atari Portfolio fixes and improvements. (#8191)

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* Fixed RAM expander reads.
* Implemented magic port 0x61.
* Fixed external drive B: detection.
* Improved control register 0x8051 emulation.
This commit is contained in:
Jaen 2021-06-15 12:58:48 -07:00 committed by GitHub
parent 3c1ca80a75
commit c6088eebee
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GPG Key ID: 4AEE18F83AFDEB23
2 changed files with 45 additions and 18 deletions
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2
src/devices/bus/pofo/hpc104.cpp
View File

@ -169,7 +169,7 @@ uint8_t pofo_hpc104_device::nrdi_r(offs_t offset, uint8_t data, bool iom, bool b
{
if (offset >= 0x1f000 && offset < 0x5f000)
{
data = m_nvram[offset - 0x1f000] = data;
data = m_nvram[offset - 0x1f000];
}
}
}

61
src/mame/drivers/pofo.cpp
View File

@ -113,10 +113,10 @@ private:
enum
{
ROM_APP,
CCM_A,
CCM_B,
ROM_EXT
ROM_APP = 0b000, // 0
CCM_A = 0b011, // 3
CCM_B = 0b111, // 7
ROM_EXT = 0b010, // 2
};
uint8_t mem_r(offs_t offset);
@ -233,9 +233,17 @@ WRITE_LINE_MEMBER( portfolio_state::keyboard_int_w )
uint8_t portfolio_state::irq_status_r()
{
return m_ip;
}
uint8_t data = m_ip;
/*
The BIOS interrupt 11h (Equipment list) reports that the second floppy drive (B:) is
installed if the 3rd bit is set (which is also the external interrupt line).
It is not clear if the ~NMD1 line is OR or XORed or muxed with the interrupt line,
but this way seems to work.
*/
data |= !m_exp->nmd1_r() << 3;
return data;
}
//-------------------------------------------------
// irq_mask_w - interrupt enable mask
@ -361,10 +369,10 @@ uint8_t portfolio_state::battery_r()
bit signal description
0 ? 1=boots from B:
1 ? 1=boots from external ROM
2 ? 1=boots from B:
3 ? 1=boots from ???
0 ? bit 0 from bus select (m_rom_b)
1 ?
2 ? bit 2 from bus select (m_rom_b)
3 ?
4 ?
5 PDET 1=peripheral connected
6 LOWB 0=battery low
@ -374,6 +382,14 @@ uint8_t portfolio_state::battery_r()
uint8_t data = 0;
/*
Partially stores what has been written into this port.
Used by interrupt 61h service 24h (Get ROM/CCM state).
Setting bit 1 here causes the BIOS to permanently wedge the external ROM
select on, so mask it out as a workaround.
*/
data |= (m_rom_b & 0b101);
// peripheral detect
data |= m_exp->pdet_r() << 5;
@ -407,13 +423,7 @@ void portfolio_state::select_w(uint8_t data)
if (LOG) logerror("%s %s SELECT %02x\n", machine().time().as_string(), machine().describe_context(), data);
switch (data & 0x0f)
{
case 3: m_rom_b = CCM_A; break;
case 7: m_rom_b = CCM_B; break;
case 0: m_rom_b = ROM_APP; break;
case 2: m_rom_b = ROM_EXT; break;
}
m_rom_b = data & 0x0f;
}
@ -530,6 +540,10 @@ uint8_t portfolio_state::mem_r(offs_t offset)
case ROM_EXT:
// TODO
break;
default:
logerror("%s %s Invalid bus read %05x\n", machine().time().as_string(), machine().describe_context(), offset & 0x1ffff);
break;
}
}
else if (offset >= 0xe0000)
@ -574,6 +588,14 @@ void portfolio_state::mem_w(offs_t offset, uint8_t data)
case CCM_B:
ncc1 = 0;
break;
case ROM_EXT:
case ROM_APP:
break;
default:
logerror("%s %s Invalid bus write %05x\n", machine().time().as_string(), machine().describe_context(), offset & 0x1ffff);
break;
}
}
@ -632,6 +654,11 @@ uint8_t portfolio_state::io_r(offs_t offset)
break;
}
}
else if (offset == 0x61)
{
// Magic port to detect the Pofo
data = 0x61;
}
data = m_exp->nrdi_r(offset, data, iom, bcom, ncc1);