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m68k: preliminary support for ColdFire family and MCF5206E

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This commit is contained in:
R. Belmont 2011-09-30 03:33:36 +00:00
parent 259a42d69e
commit c67a422620
8 changed files with 993 additions and 648 deletions
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4
src/emu/cpu/m68000/m68000.h
View File

@ -34,7 +34,8 @@ enum
M68K_CPU_TYPE_68LC040, M68K_CPU_TYPE_68LC040,
M68K_CPU_TYPE_68040, M68K_CPU_TYPE_68040,
M68K_CPU_TYPE_SCC68070, M68K_CPU_TYPE_SCC68070,
M68K_CPU_TYPE_68340 M68K_CPU_TYPE_68340,
M68K_CPU_TYPE_COLDFIRE
}; };
// function codes // function codes
@ -105,6 +106,7 @@ DECLARE_LEGACY_CPU_DEVICE(M68LC040, m68lc040);
DECLARE_LEGACY_CPU_DEVICE(M68040, m68040); DECLARE_LEGACY_CPU_DEVICE(M68040, m68040);
DECLARE_LEGACY_CPU_DEVICE(SCC68070, scc68070); DECLARE_LEGACY_CPU_DEVICE(SCC68070, scc68070);
DECLARE_LEGACY_CPU_DEVICE(M68340, m68340); DECLARE_LEGACY_CPU_DEVICE(M68340, m68340);
DECLARE_LEGACY_CPU_DEVICE(MCF5206E, mcf5206e);
void m68k_set_encrypted_opcode_range(device_t *device, offs_t start, offs_t end); void m68k_set_encrypted_opcode_range(device_t *device, offs_t start, offs_t end);

1242
src/emu/cpu/m68000/m68k_in.c
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File diff suppressed because it is too large Load Diff

138
src/emu/cpu/m68000/m68kcpu.c
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@ -5,8 +5,8 @@
#if 0 #if 0
static const char copyright_notice[] = static const char copyright_notice[] =
"MUSASHI\n" "MUSASHI\n"
"Version 4.80 (2010-08-27)\n" "Version 4.90 (2011-09-22)\n"
"A portable Motorola M68xxx processor emulation engine.\n" "A portable Motorola M68xxx/CPU32/ColdFire processor emulation engine.\n"
"Copyright Karl Stenerud. All rights reserved.\n" "Copyright Karl Stenerud. All rights reserved.\n"
"\n" "\n"
"This code may be freely used for non-commercial purpooses as long as this\n" "This code may be freely used for non-commercial purpooses as long as this\n"
@ -89,7 +89,7 @@ const UINT32 m68ki_shift_32_table[65] =
/* Number of clock cycles to use for exception processing. /* Number of clock cycles to use for exception processing.
* I used 4 for any vectors that are undocumented for processing times. * I used 4 for any vectors that are undocumented for processing times.
*/ */
const UINT8 m68ki_exception_cycle_table[6][256] = const UINT8 m68ki_exception_cycle_table[7][256] =
{ {
{ /* 000 */ { /* 000 */
40, /* 0: Reset - Initial Stack Pointer */ 40, /* 0: Reset - Initial Stack Pointer */
@ -529,6 +529,79 @@ const UINT8 m68ki_exception_cycle_table[6][256] =
4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4, 4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,
4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4 4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4
}, },
{ /* ColdFire - not correct */
4, /* 0: Reset - Initial Stack Pointer */
4, /* 1: Reset - Initial Program Counter */
50, /* 2: Bus Error (unemulated) */
50, /* 3: Address Error (unemulated) */
20, /* 4: Illegal Instruction */
38, /* 5: Divide by Zero */
40, /* 6: CHK */
20, /* 7: TRAPV */
34, /* 8: Privilege Violation */
25, /* 9: Trace */
20, /* 10: 1010 */
20, /* 11: 1111 */
4, /* 12: RESERVED */
4, /* 13: Coprocessor Protocol Violation (unemulated) */
4, /* 14: Format Error */
30, /* 15: Uninitialized Interrupt */
4, /* 16: RESERVED */
4, /* 17: RESERVED */
4, /* 18: RESERVED */
4, /* 19: RESERVED */
4, /* 20: RESERVED */
4, /* 21: RESERVED */
4, /* 22: RESERVED */
4, /* 23: RESERVED */
30, /* 24: Spurious Interrupt */
30, /* 25: Level 1 Interrupt Autovector */
30, /* 26: Level 2 Interrupt Autovector */
30, /* 27: Level 3 Interrupt Autovector */
30, /* 28: Level 4 Interrupt Autovector */
30, /* 29: Level 5 Interrupt Autovector */
30, /* 30: Level 6 Interrupt Autovector */
30, /* 31: Level 7 Interrupt Autovector */
20, /* 32: TRAP #0 */
20, /* 33: TRAP #1 */
20, /* 34: TRAP #2 */
20, /* 35: TRAP #3 */
20, /* 36: TRAP #4 */
20, /* 37: TRAP #5 */
20, /* 38: TRAP #6 */
20, /* 39: TRAP #7 */
20, /* 40: TRAP #8 */
20, /* 41: TRAP #9 */
20, /* 42: TRAP #10 */
20, /* 43: TRAP #11 */
20, /* 44: TRAP #12 */
20, /* 45: TRAP #13 */
20, /* 46: TRAP #14 */
20, /* 47: TRAP #15 */
4, /* 48: FP Branch or Set on Unknown Condition (unemulated) */
4, /* 49: FP Inexact Result (unemulated) */
4, /* 50: FP Divide by Zero (unemulated) */
4, /* 51: FP Underflow (unemulated) */
4, /* 52: FP Operand Error (unemulated) */
4, /* 53: FP Overflow (unemulated) */
4, /* 54: FP Signaling NAN (unemulated) */
4, /* 55: FP Unimplemented Data Type (unemulated) */
4, /* 56: MMU Configuration Error (unemulated) */
4, /* 57: MMU Illegal Operation Error (unemulated) */
4, /* 58: MMU Access Level Violation Error (unemulated) */
4, /* 59: RESERVED */
4, /* 60: RESERVED */
4, /* 61: RESERVED */
4, /* 62: RESERVED */
4, /* 63: RESERVED */
/* 64-255: User Defined */
4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,
4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,
4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,
4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,
4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,
4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4
},
}; };
const UINT8 m68ki_ea_idx_cycle_table[64] = const UINT8 m68ki_ea_idx_cycle_table[64] =
@ -581,6 +654,7 @@ INLINE m68ki_cpu_core *get_safe_token(device_t *device)
device->type() == M68EC040 || device->type() == M68EC040 ||
device->type() == M68040 || device->type() == M68040 ||
device->type() == SCC68070 || device->type() == SCC68070 ||
device->type() == COLDFIRE ||
device->type() == M68340); device->type() == M68340);
return (m68ki_cpu_core *)downcast<legacy_cpu_device *>(device)->token(); return (m68ki_cpu_core *)downcast<legacy_cpu_device *>(device)->token();
} }
@ -1154,7 +1228,7 @@ static CPU_GET_INFO( m68k )
/* --- the following bits of info are returned as NULL-terminated strings --- */ /* --- the following bits of info are returned as NULL-terminated strings --- */
case DEVINFO_STR_NAME: /* set per-core */ break; case DEVINFO_STR_NAME: /* set per-core */ break;
case DEVINFO_STR_FAMILY: strcpy(info->s, "Motorola 68K"); break; case DEVINFO_STR_FAMILY: strcpy(info->s, "Motorola 68K"); break;
case DEVINFO_STR_VERSION: strcpy(info->s, "4.60"); break; case DEVINFO_STR_VERSION: strcpy(info->s, "4.90"); break;
case DEVINFO_STR_SOURCE_FILE: strcpy(info->s, __FILE__); break; case DEVINFO_STR_SOURCE_FILE: strcpy(info->s, __FILE__); break;
case DEVINFO_STR_CREDITS: strcpy(info->s, "Copyright Karl Stenerud. All rights reserved. (2.1 fixes HJB, FPU+MMU by RB+HO)"); break; case DEVINFO_STR_CREDITS: strcpy(info->s, "Copyright Karl Stenerud. All rights reserved. (2.1 fixes HJB, FPU+MMU by RB+HO)"); break;
} }
@ -2367,7 +2441,62 @@ CPU_GET_INFO( m68340 )
} }
} }
/*
ColdFire
*/
static CPU_INIT( coldfire )
{
m68ki_cpu_core *m68k = get_safe_token(device);
CPU_INIT_CALL(m68k);
m68k->cpu_type = CPU_TYPE_COLDFIRE;
m68k->dasm_type = M68K_CPU_TYPE_COLDFIRE;
// hack alert: we use placement new to ensure we are properly initialized
// because we live in the device state which is allocated as bytes
// remove me when we have a real C++ device
new(&m68k->memory) m68k_memory_interface;
m68k->memory.init32(*m68k->program);
m68k->sr_mask = 0xf71f; /* T1 T0 S M -- I2 I1 I0 -- -- -- X N Z V C */
m68k->jump_table = m68ki_instruction_jump_table[6];
m68k->cyc_instruction = m68ki_cycles[6];
m68k->cyc_exception = m68ki_exception_cycle_table[6];
m68k->cyc_bcc_notake_b = -2;
m68k->cyc_bcc_notake_w = 0;
m68k->cyc_dbcc_f_noexp = 0;
m68k->cyc_dbcc_f_exp = 4;
m68k->cyc_scc_r_true = 0;
m68k->cyc_movem_w = 2;
m68k->cyc_movem_l = 2;
m68k->cyc_shift = 0;
m68k->cyc_reset = 518;
define_state(device);
}
CPU_GET_INFO( mcf5206e )
{
switch (state)
{
/* --- the following bits of info are returned as 64-bit signed integers --- */
case CPUINFO_INT_MAX_INSTRUCTION_BYTES: info->i = 20; break;
case CPUINFO_INT_MIN_CYCLES: info->i = 2; break;
case CPUINFO_INT_MAX_CYCLES: info->i = 158; break;
case DEVINFO_INT_DATABUS_WIDTH + AS_PROGRAM: info->i = 32; break;
case DEVINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 32; break;
/* --- the following bits of info are returned as pointers to data or functions --- */
case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(coldfire); break;
/* --- the following bits of info are returned as NULL-terminated strings --- */
case DEVINFO_STR_NAME: strcpy(info->s, "MCF5206E"); break;
default: CPU_GET_INFO_CALL(m68k); break;
}
}
DEFINE_LEGACY_CPU_DEVICE(M68000, m68000); DEFINE_LEGACY_CPU_DEVICE(M68000, m68000);
DEFINE_LEGACY_CPU_DEVICE(M68008, m68008); DEFINE_LEGACY_CPU_DEVICE(M68008, m68008);
@ -2383,4 +2512,5 @@ DEFINE_LEGACY_CPU_DEVICE(M68LC040, m68lc040);
DEFINE_LEGACY_CPU_DEVICE(M68040, m68040); DEFINE_LEGACY_CPU_DEVICE(M68040, m68040);
DEFINE_LEGACY_CPU_DEVICE(SCC68070, scc68070); DEFINE_LEGACY_CPU_DEVICE(SCC68070, scc68070);
DEFINE_LEGACY_CPU_DEVICE(M68340, m68340); DEFINE_LEGACY_CPU_DEVICE(M68340, m68340);
DEFINE_LEGACY_CPU_DEVICE(MCF5206E, mcf5206e);

11
src/emu/cpu/m68000/m68kcpu.h
View File

@ -87,6 +87,7 @@ typedef struct _m68ki_cpu_core m68ki_cpu_core;
#define CPU_TYPE_040 (0x00000200) #define CPU_TYPE_040 (0x00000200)
#define CPU_TYPE_SCC070 (0x00000400) #define CPU_TYPE_SCC070 (0x00000400)
#define CPU_TYPE_68340 (0x00000800) #define CPU_TYPE_68340 (0x00000800)
#define CPU_TYPE_COLDFIRE (0x00001000)
/* Different ways to stop the CPU */ /* Different ways to stop the CPU */
#define STOP_LEVEL_STOP 1 #define STOP_LEVEL_STOP 1
@ -234,22 +235,24 @@ typedef struct _m68ki_cpu_core m68ki_cpu_core;
/* These defines are dependant on the configuration defines in m68kconf.h */ /* These defines are dependant on the configuration defines in m68kconf.h */
/* Disable certain comparisons if we're not using all CPU types */ /* Disable certain comparisons if we're not using all CPU types */
#define CPU_TYPE_IS_COLDFIRE(A) ((A) & (CPU_TYPE_COLDFIRE))
#define CPU_TYPE_IS_040_PLUS(A) ((A) & (CPU_TYPE_040 | CPU_TYPE_EC040)) #define CPU_TYPE_IS_040_PLUS(A) ((A) & (CPU_TYPE_040 | CPU_TYPE_EC040))
#define CPU_TYPE_IS_040_LESS(A) 1 #define CPU_TYPE_IS_040_LESS(A) 1
#define CPU_TYPE_IS_030_PLUS(A) ((A) & (CPU_TYPE_030 | CPU_TYPE_EC030 | CPU_TYPE_040 | CPU_TYPE_EC040)) #define CPU_TYPE_IS_030_PLUS(A) ((A) & (CPU_TYPE_030 | CPU_TYPE_EC030 | CPU_TYPE_040 | CPU_TYPE_EC040))
#define CPU_TYPE_IS_030_LESS(A) 1 #define CPU_TYPE_IS_030_LESS(A) 1
#define CPU_TYPE_IS_020_PLUS(A) ((A) & (CPU_TYPE_020 | CPU_TYPE_030 | CPU_TYPE_EC030 | CPU_TYPE_040 | CPU_TYPE_EC040 | CPU_TYPE_68340)) #define CPU_TYPE_IS_020_PLUS(A) ((A) & (CPU_TYPE_020 | CPU_TYPE_030 | CPU_TYPE_EC030 | CPU_TYPE_040 | CPU_TYPE_EC040 | CPU_TYPE_68340 | CPU_TYPE_COLDFIRE))
#define CPU_TYPE_IS_020_LESS(A) 1 #define CPU_TYPE_IS_020_LESS(A) 1
#define CPU_TYPE_IS_020_VARIANT(A) ((A) & (CPU_TYPE_EC020 | CPU_TYPE_020 | CPU_TYPE_68340)) #define CPU_TYPE_IS_020_VARIANT(A) ((A) & (CPU_TYPE_EC020 | CPU_TYPE_020 | CPU_TYPE_68340))
#define CPU_TYPE_IS_EC020_PLUS(A) ((A) & (CPU_TYPE_EC020 | CPU_TYPE_020 | CPU_TYPE_030 | CPU_TYPE_EC030 | CPU_TYPE_040 | CPU_TYPE_EC040 | CPU_TYPE_68340)) #define CPU_TYPE_IS_EC020_PLUS(A) ((A) & (CPU_TYPE_EC020 | CPU_TYPE_020 | CPU_TYPE_030 | CPU_TYPE_EC030 | CPU_TYPE_040 | CPU_TYPE_EC040 | CPU_TYPE_68340 | CPU_TYPE_COLDFIRE))
#define CPU_TYPE_IS_EC020_LESS(A) ((A) & (CPU_TYPE_000 | CPU_TYPE_008 | CPU_TYPE_010 | CPU_TYPE_EC020)) #define CPU_TYPE_IS_EC020_LESS(A) ((A) & (CPU_TYPE_000 | CPU_TYPE_008 | CPU_TYPE_010 | CPU_TYPE_EC020))
#define CPU_TYPE_IS_010(A) ((A) == CPU_TYPE_010) #define CPU_TYPE_IS_010(A) ((A) == CPU_TYPE_010)
#define CPU_TYPE_IS_010_PLUS(A) ((A) & (CPU_TYPE_010 | CPU_TYPE_EC020 | CPU_TYPE_020 | CPU_TYPE_EC030 | CPU_TYPE_030 | CPU_TYPE_040 | CPU_TYPE_EC040 | CPU_TYPE_68340)) #define CPU_TYPE_IS_010_PLUS(A) ((A) & (CPU_TYPE_010 | CPU_TYPE_EC020 | CPU_TYPE_020 | CPU_TYPE_EC030 | CPU_TYPE_030 | CPU_TYPE_040 | CPU_TYPE_EC040 | CPU_TYPE_68340 | CPU_TYPE_COLDFIRE))
#define CPU_TYPE_IS_010_LESS(A) ((A) & (CPU_TYPE_000 | CPU_TYPE_008 | CPU_TYPE_010)) #define CPU_TYPE_IS_010_LESS(A) ((A) & (CPU_TYPE_000 | CPU_TYPE_008 | CPU_TYPE_010))
#define CPU_TYPE_IS_000(A) ((A) == CPU_TYPE_000 || (A) == CPU_TYPE_008) #define CPU_TYPE_IS_000(A) ((A) == CPU_TYPE_000 || (A) == CPU_TYPE_008)
@ -694,6 +697,8 @@ public:
UINT32 mmu_atc_tag[MMU_ATC_ENTRIES], mmu_atc_data[MMU_ATC_ENTRIES]; UINT32 mmu_atc_tag[MMU_ATC_ENTRIES], mmu_atc_data[MMU_ATC_ENTRIES];
UINT32 mmu_atc_rr; UINT32 mmu_atc_rr;
UINT32 mmu_tt0, mmu_tt1; UINT32 mmu_tt0, mmu_tt1;
UINT32 mmu_itt0, mmu_itt1, mmu_dtt0, mmu_dtt1;
UINT32 mmu_acr0, mmu_acr1, mmu_acr2, mmu_acr3;
UINT16 mmu_tmp_sr; /* temporary hack: status code for ptest and to handle write protection */ UINT16 mmu_tmp_sr; /* temporary hack: status code for ptest and to handle write protection */
UINT16 mmu_tmp_fc; /* temporary hack: function code for the mmu (moves) */ UINT16 mmu_tmp_fc; /* temporary hack: function code for the mmu (moves) */

97
src/emu/cpu/m68000/m68kdasm.c
View File

@ -82,17 +82,18 @@
#define TYPE_68020 8 #define TYPE_68020 8
#define TYPE_68030 16 #define TYPE_68030 16
#define TYPE_68040 32 #define TYPE_68040 32
#define TYPE_68340 64 #define TYPE_68340 64 // (CPU32)
#define TYPE_COLDFIRE 128
#define M68000_ONLY (TYPE_68000 | TYPE_68008) #define M68000_ONLY (TYPE_68000 | TYPE_68008)
#define M68010_ONLY TYPE_68010 #define M68010_ONLY TYPE_68010
#define M68010_LESS (TYPE_68000 | TYPE_68008 | TYPE_68010) #define M68010_LESS (TYPE_68000 | TYPE_68008 | TYPE_68010)
#define M68010_PLUS (TYPE_68010 | TYPE_68020 | TYPE_68030 | TYPE_68040 | TYPE_68340) #define M68010_PLUS (TYPE_68010 | TYPE_68020 | TYPE_68030 | TYPE_68040 | TYPE_68340 | TYPE_COLDFIRE)
#define M68020_ONLY (TYPE_68020 | TYPE_68340) #define M68020_ONLY (TYPE_68020 | TYPE_68340)
#define M68020_LESS (TYPE_68010 | TYPE_68020 | TYPE_68340) #define M68020_LESS (TYPE_68010 | TYPE_68020 | TYPE_68340)
#define M68020_PLUS (TYPE_68020 | TYPE_68030 | TYPE_68040 | TYPE_68340) #define M68020_PLUS (TYPE_68020 | TYPE_68030 | TYPE_68040 | TYPE_68340 | TYPE_COLDFIRE)
#define M68030_ONLY TYPE_68030 #define M68030_ONLY TYPE_68030
#define M68030_LESS (TYPE_68010 | TYPE_68020 | TYPE_68030 | TYPE_68340 ) #define M68030_LESS (TYPE_68010 | TYPE_68020 | TYPE_68030 | TYPE_68340 )
@ -100,6 +101,7 @@
#define M68040_PLUS TYPE_68040 #define M68040_PLUS TYPE_68040
#define COLDFIRE TYPE_COLDFIRE
/* Extension word formats */ /* Extension word formats */
#define EXT_8BIT_DISPLACEMENT(A) ((A)&0xff) #define EXT_8BIT_DISPLACEMENT(A) ((A)&0xff)
@ -2133,20 +2135,52 @@ static void d68010_movec(void)
processor = "4+"; processor = "4+";
break; break;
case 0x004: case 0x004:
reg_name = "ITT0"; if(g_cpu_type & COLDFIRE)
processor = "4+"; {
reg_name = "ACR0";
processor = "CF";
}
else
{
reg_name = "ITT0";
processor = "4+";
}
break; break;
case 0x005: case 0x005:
reg_name = "ITT1"; if(g_cpu_type & COLDFIRE)
processor = "4+"; {
reg_name = "ACR1";
processor = "CF";
}
else
{
reg_name = "ITT1";
processor = "4+";
}
break; break;
case 0x006: case 0x006:
reg_name = "DTT0"; if(g_cpu_type & COLDFIRE)
processor = "4+"; {
reg_name = "ACR2";
processor = "CF";
}
else
{
reg_name = "DTT0";
processor = "4+";
}
break; break;
case 0x007: case 0x007:
reg_name = "DTT1"; if(g_cpu_type & COLDFIRE)
processor = "4+"; {
reg_name = "ACR3";
processor = "CF";
}
else
{
reg_name = "DTT1";
processor = "4+";
}
break; break;
case 0x805: case 0x805:
reg_name = "MMUSR"; reg_name = "MMUSR";
@ -2160,6 +2194,38 @@ static void d68010_movec(void)
reg_name = "SRP"; reg_name = "SRP";
processor = "4+"; processor = "4+";
break; break;
case 0xc00:
reg_name = "ROMBAR0";
processor = "CF";
break;
case 0xc01:
reg_name = "ROMBAR1";
processor = "CF";
break;
case 0xc04:
reg_name = "RAMBAR0";
processor = "CF";
break;
case 0xc05:
reg_name = "RAMBAR1";
processor = "CF";
break;
case 0xc0c:
reg_name = "MPCR";
processor = "CF";
break;
case 0xc0d:
reg_name = "EDRAMBAR";
processor = "CF";
break;
case 0xc0e:
reg_name = "SECMBAR";
processor = "CF";
break;
case 0xc0f:
reg_name = "MBAR";
processor = "CF";
break;
default: default:
reg_name = make_signed_hex_str_16(extension & 0xfff); reg_name = make_signed_hex_str_16(extension & 0xfff);
processor = "?"; processor = "?";
@ -3759,6 +3825,9 @@ static unsigned int m68k_disassemble(char* str_buff, unsigned int pc, unsigned i
case M68K_CPU_TYPE_68340: case M68K_CPU_TYPE_68340:
g_cpu_type = TYPE_68340; g_cpu_type = TYPE_68340;
break; break;
case M68K_CPU_TYPE_COLDFIRE:
g_cpu_type = TYPE_COLDFIRE;
break;
default: default:
return 0; return 0;
} }
@ -3951,6 +4020,7 @@ unsigned int m68k_is_valid_instruction(unsigned int instruction, unsigned int cp
case M68K_CPU_TYPE_68030: case M68K_CPU_TYPE_68030:
case M68K_CPU_TYPE_68EC030: case M68K_CPU_TYPE_68EC030:
case M68K_CPU_TYPE_68340: case M68K_CPU_TYPE_68340:
case M68K_CPU_TYPE_COLDFIRE:
if(g_instruction_table[instruction] == d68040_cinv) if(g_instruction_table[instruction] == d68040_cinv)
return 0; return 0;
if(g_instruction_table[instruction] == d68040_cpush) if(g_instruction_table[instruction] == d68040_cpush)
@ -4035,7 +4105,10 @@ CPU_DISASSEMBLE( m68340 )
return m68k_disassemble_raw(buffer, pc, oprom, opram, M68K_CPU_TYPE_68340); return m68k_disassemble_raw(buffer, pc, oprom, opram, M68K_CPU_TYPE_68340);
} }
// f028 2215 0008 CPU_DISASSEMBLE( coldfire )
{
return m68k_disassemble_raw(buffer, pc, oprom, opram, M68K_CPU_TYPE_COLDFIRE);
}
/* ======================================================================== */ /* ======================================================================== */
/* ============================== END OF FILE ============================= */ /* ============================== END OF FILE ============================= */

48
src/emu/cpu/m68000/m68kmake.c
View File

@ -3,11 +3,10 @@
/* ======================================================================== */ /* ======================================================================== */
/* /*
* MUSASHI * MUSASHI
* Version 4.80 * Version 4.90
* *
* A portable Motorola M680x0 processor emulation engine. * A portable Motorola M680x0 processor emulation engine.
* Copyright Karl Stenerud. All rights reserved. * Copyright Karl Stenerud. All rights reserved.
* FPU and MMU by R. Belmont.
* *
* This code may be freely used for non-commercial purposes as long as this * This code may be freely used for non-commercial purposes as long as this
* copyright notice remains unaltered in the source code and any binary files * copyright notice remains unaltered in the source code and any binary files
@ -21,11 +20,10 @@
*/ */
/* /*
* Modified For OpenVMS By: Robert Alan Byer
* byer@mail.ourservers.net
*
* 68030 and PMMU by R. Belmont and Hans Ostermeyer * 68030 and PMMU by R. Belmont and Hans Ostermeyer
* 68040 and FPU by Ville Linde, R. Belmont, and Hans Ostermeyer * 68040 and FPU by Ville Linde, R. Belmont, and Hans Ostermeyer
* CPU32 by David Haywood. ColdFire by R. Belmont.
*
*/ */
@ -56,7 +54,7 @@
*/ */
static const char g_version[] = "4.80"; static const char g_version[] = "4.90";
/* ======================================================================== */ /* ======================================================================== */
/* =============================== INCLUDES =============================== */ /* =============================== INCLUDES =============================== */
@ -139,6 +137,7 @@ enum
CPU_TYPE_030, // 3 CPU_TYPE_030, // 3
CPU_TYPE_040, // 4 CPU_TYPE_040, // 4
CPU_TYPE_68340, // 5 CPU_TYPE_68340, // 5
CPU_TYPE_COLDFIRE, // 6
NUM_CPUS NUM_CPUS
}; };
@ -1079,9 +1078,11 @@ static void populate_table(void)
buff[0] = 0; buff[0] = 0;
/* Find the start of the table */ /* Find the start of the table */
while(strcmp(buff, ID_TABLE_START) != 0) while (strncmp(buff, ID_TABLE_START, strlen(ID_TABLE_START)) != 0)
{
if(fgetline(buff, MAX_LINE_LENGTH, g_input_file) < 0) if(fgetline(buff, MAX_LINE_LENGTH, g_input_file) < 0)
error_exit("(table_start) Premature EOF while reading table"); error_exit("(table_start) Premature EOF while reading table");
}
/* Process the entire table */ /* Process the entire table */
for(op = g_opcode_input_table;;op++) for(op = g_opcode_input_table;;op++)
@ -1246,8 +1247,8 @@ int main(int argc, char *argv[])
int table_body_read = 0; int table_body_read = 0;
int ophandler_body_read = 0; int ophandler_body_read = 0;
printf("\n\tMusashi v%s 68000, 68008, 68010, 68EC020, 68020, 68EC030, 68030, 68EC040, 68040 emulator\n", g_version); printf("\n\tMusashi v%s 680x0, CPU32, and ColdFire emulator\n", g_version);
printf("\tCopyright Karl Stenerud\n\n"); printf("\tCopyright Karl Stenerud and the MAME team.\n\n");
/* Check if output path and source for the input file are given */ /* Check if output path and source for the input file are given */
if(argc > 1) if(argc > 1)
@ -1257,45 +1258,22 @@ int main(int argc, char *argv[])
for(ptr = strchr(output_path, '\\'); ptr; ptr = strchr(ptr, '\\')) for(ptr = strchr(output_path, '\\'); ptr; ptr = strchr(ptr, '\\'))
*ptr = '/'; *ptr = '/';
#if !(defined(__DECC) && defined(VMS))
if(output_path[strlen(output_path)-1] != '/')
strcat(output_path, "/");
#endif
} }
strcpy(g_input_filename, (argc > 2) ? argv[2] : FILENAME_INPUT); strcpy(g_input_filename, (argc > 2) ? argv[2] : FILENAME_INPUT);
#if defined(__DECC) && defined(VMS)
/* Open the files we need */ /* Open the files we need */
sprintf(filename, "%s%s", output_path, FILENAME_PROTOTYPE); sprintf(filename, "%s/%s", output_path, FILENAME_PROTOTYPE);
if((g_prototype_file = fopen(filename, "w")) == NULL)
perror_exit("Unable to create prototype file (%s)\n", filename);
sprintf(filename, "%s%s", output_path, FILENAME_TABLE);
if((g_table_file = fopen(filename, "w")) == NULL)
perror_exit("Unable to create table file (%s)\n", filename);
if((g_input_file=fopen(g_input_filename, "r")) == NULL)
perror_exit("can't open %s for input", g_input_filename);
#else
/* Open the files we need */
sprintf(filename, "%s%s", output_path, FILENAME_PROTOTYPE);
if((g_prototype_file = fopen(filename, "wt")) == NULL) if((g_prototype_file = fopen(filename, "wt")) == NULL)
perror_exit("Unable to create prototype file (%s)\n", filename); perror_exit("Unable to create prototype file (%s)\n", filename);
sprintf(filename, "%s%s", output_path, FILENAME_TABLE); sprintf(filename, "%s/%s", output_path, FILENAME_TABLE);
if((g_table_file = fopen(filename, "wt")) == NULL) if((g_table_file = fopen(filename, "wt")) == NULL)
perror_exit("Unable to create table file (%s)\n", filename); perror_exit("Unable to create table file (%s)\n", filename);
if((g_input_file=fopen(g_input_filename, "rt")) == NULL) if((g_input_file=fopen(g_input_filename, "rt")) == NULL)
perror_exit("can't open %s for input", g_input_filename); perror_exit("can't open %s for input", g_input_filename);
#endif
/* Get to the first section of the input file */ /* Get to the first section of the input file */
section_id[0] = 0; section_id[0] = 0;

87
src/emu/cpu/m68000/m68kmmu.h
View File

@ -148,7 +148,7 @@ void pmmu_atc_add(m68ki_cpu_core *m68k, UINT32 logical, UINT32 physical, int fc)
} }
// add the entry // add the entry
// logerror("ATC[%2d] add: log %08x -> phys %08x (fc=%d)\n", found, (logical>>ps) << ps, (physical >> ps) << ps, fc); // printf("ATC[%2d] add: log %08x -> phys %08x (fc=%d)\n", found, (logical>>ps) << ps, (physical >> ps) << ps, fc);
m68k->mmu_atc_tag[found] = atc_tag; m68k->mmu_atc_tag[found] = atc_tag;
m68k->mmu_atc_data[found] = (physical >> ps) << (ps-8); m68k->mmu_atc_data[found] = (physical >> ps) << (ps-8);
@ -166,7 +166,7 @@ void pmmu_atc_add(m68ki_cpu_core *m68k, UINT32 logical, UINT32 physical, int fc)
void pmmu_atc_flush(m68ki_cpu_core *m68k) void pmmu_atc_flush(m68ki_cpu_core *m68k)
{ {
int i; int i;
// logerror("ATC flush: pc=%08x\n", REG_PPC(m68k)); // printf("ATC flush: pc=%08x\n", REG_PPC(m68k));
for (i = 0; i < MMU_ATC_ENTRIES; i++) for (i = 0; i < MMU_ATC_ENTRIES; i++)
{ {
@ -255,13 +255,13 @@ INLINE UINT32 get_dt3_table_entry(m68ki_cpu_core *m68k, UINT32 tptr, UINT8 fc, U
UINT32 address_mask = ((m68k->mmu_tt0 << 8) & 0xff000000) ^ 0xff000000; UINT32 address_mask = ((m68k->mmu_tt0 << 8) & 0xff000000) ^ 0xff000000;
if ((addr_in & address_mask) == address_base) if ((addr_in & address_mask) == address_base)
{ {
// logerror("PMMU: pc=%x TT0 fc=%x addr_in=%08x address_mask=%08x address_base=%08x\n", m68k->ppc, fc, addr_in, address_mask, address_base); // printf("PMMU: pc=%x TT0 fc=%x addr_in=%08x address_mask=%08x address_base=%08x\n", m68k->ppc, fc, addr_in, address_mask, address_base);
return addr_in; return addr_in;
} }
} }
// if ((++pmmu_access_count % 10000000) == 0) { // if ((++pmmu_access_count % 10000000) == 0) {
// logerror("pmmu_translate_addr_with_fc: atc usage = %d%%\n", pmmu_atc_count*100/pmmu_access_count); // printf("pmmu_translate_addr_with_fc: atc usage = %d%%\n", pmmu_atc_count*100/pmmu_access_count);
// pmmu_atc_count = pmmu_access_count = 0; // pmmu_atc_count = pmmu_access_count = 0;
// } // }
@ -298,7 +298,7 @@ INLINE UINT32 get_dt3_table_entry(m68ki_cpu_core *m68k, UINT32 tptr, UINT8 fc, U
m68k->mmu_tmp_sr = M68K_MMU_SR_MODIFIED; m68k->mmu_tmp_sr = M68K_MMU_SR_MODIFIED;
} }
addr_out = (m68k->mmu_atc_data[i] << 8) | (addr_in & ~(~0 << ps)); addr_out = (m68k->mmu_atc_data[i] << 8) | (addr_in & ~(~0 << ps));
// logerror("ATC[%2d] hit: log %08x -> phys %08x pc=%08x fc=%d\n", i, addr_in, addr_out, REG_PPC(m68k), fc); // printf("ATC[%2d] hit: log %08x -> phys %08x pc=%08x fc=%d\n", i, addr_in, addr_out, REG_PPC(m68k), fc);
// pmmu_atc_count++; // pmmu_atc_count++;
return addr_out; return addr_out;
} }
@ -323,7 +323,7 @@ INLINE UINT32 get_dt3_table_entry(m68ki_cpu_core *m68k, UINT32 tptr, UINT8 fc, U
bbits = (m68k->mmu_tc >> 8) & 0xf; bbits = (m68k->mmu_tc >> 8) & 0xf;
cbits = (m68k->mmu_tc >> 4) & 0xf; cbits = (m68k->mmu_tc >> 4) & 0xf;
// logerror("PMMU: tcr %08x limit %08x aptr %08x is %x abits %d bbits %d cbits %d\n", m68k->mmu_tc, root_limit, root_aptr, is, abits, bbits, cbits); // printf("PMMU: tcr %08x limit %08x aptr %08x is %x abits %d bbits %d cbits %d\n", m68k->mmu_tc, root_limit, root_aptr, is, abits, bbits, cbits);
// get table A offset // get table A offset
tofs = (addr_in<<is)>>(32-abits); tofs = (addr_in<<is)>>(32-abits);
@ -338,23 +338,23 @@ INLINE UINT32 get_dt3_table_entry(m68ki_cpu_core *m68k, UINT32 tptr, UINT8 fc, U
case M68K_MMU_DF_DT1: // page descriptor, will cause direct mapping case M68K_MMU_DF_DT1: // page descriptor, will cause direct mapping
addr_out = tptr + addr_in; addr_out = tptr + addr_in;
// logerror("PMMU: PC=%x root mode %d (addr_in %08x -> %08x)\n", m68k->ppc, M68K_MMU_DF_DT1, addr_in, addr_out); // printf("PMMU: PC=%x root mode %d (addr_in %08x -> %08x)\n", m68k->ppc, M68K_MMU_DF_DT1, addr_in, addr_out);
return addr_out; return addr_out;
case M68K_MMU_DF_DT2: // valid 4 byte descriptors case M68K_MMU_DF_DT2: // valid 4 byte descriptors
tofs *= 4; tofs *= 4;
// if (verbose) logerror("PMMU: reading table A entry at %08x\n", tofs + tptr); // if (verbose) printf("PMMU: reading table A entry at %08x\n", tofs + tptr);
tbl_entry = get_dt2_table_entry(m68k, tptr + tofs, ptest); tbl_entry = get_dt2_table_entry(m68k, tptr + tofs, ptest);
tamode = tbl_entry & M68K_MMU_DF_DT; tamode = tbl_entry & M68K_MMU_DF_DT;
// if (verbose) logerror("PMMU: addr %08x entry %08x mode %x tofs %x\n", addr_in, tbl_entry, tamode, tofs); // if (verbose) printf("PMMU: addr %08x entry %08x mode %x tofs %x\n", addr_in, tbl_entry, tamode, tofs);
break; break;
case M68K_MMU_DF_DT3: // valid 8 byte descriptors case M68K_MMU_DF_DT3: // valid 8 byte descriptors
tofs *= 8; tofs *= 8;
// if (verbose) logerror("PMMU: reading table A entries at %08x\n", tofs + tptr); // if (verbose) printf("PMMU: reading table A entries at %08x\n", tofs + tptr);
tbl_entry = get_dt3_table_entry(m68k, tofs + tptr, fc, ptest); tbl_entry = get_dt3_table_entry(m68k, tofs + tptr, fc, ptest);
tamode = tbl_entry & M68K_MMU_DF_DT; tamode = tbl_entry & M68K_MMU_DF_DT;
// if (verbose) logerror("PMMU: addr %08x entry %08x entry2 %08x mode %x tofs %x\n", addr_in, tbl_entry, tbl_entry2, tamode, tofs); // if (verbose) printf("PMMU: addr %08x entry %08x entry2 %08x mode %x tofs %x\n", addr_in, tbl_entry, tbl_entry2, tamode, tofs);
break; break;
} }
@ -376,19 +376,19 @@ INLINE UINT32 get_dt3_table_entry(m68ki_cpu_core *m68k, UINT32 tptr, UINT8 fc, U
case M68K_MMU_DF_DT2: // 4-byte table B descriptor case M68K_MMU_DF_DT2: // 4-byte table B descriptor
tofs *= 4; tofs *= 4;
// if (verbose) logerror("PMMU: reading table B entry at %08x\n", tofs + tptr); // if (verbose) printf("PMMU: reading table B entry at %08x\n", tofs + tptr);
tbl_entry = get_dt2_table_entry(m68k, tptr + tofs, ptest); tbl_entry = get_dt2_table_entry(m68k, tptr + tofs, ptest);
tbmode = tbl_entry & M68K_MMU_DF_DT; tbmode = tbl_entry & M68K_MMU_DF_DT;
// if (verbose) logerror("PMMU: addr %08x entry %08x mode %x tofs %x\n", addr_in, tbl_entry, tbmode, tofs); // if (verbose) printf("PMMU: addr %08x entry %08x mode %x tofs %x\n", addr_in, tbl_entry, tbmode, tofs);
break; break;
case M68K_MMU_DF_DT3: // 8-byte table B descriptor case M68K_MMU_DF_DT3: // 8-byte table B descriptor
tofs *= 8; tofs *= 8;
// if (verbose) logerror("PMMU: reading table B entries at %08x\n", tofs + tptr); // if (verbose) printf("PMMU: reading table B entries at %08x\n", tofs + tptr);
tbl_entry = get_dt3_table_entry(m68k, tptr + tofs, fc, ptest); tbl_entry = get_dt3_table_entry(m68k, tptr + tofs, fc, ptest);
tbmode = tbl_entry & M68K_MMU_DF_DT; tbmode = tbl_entry & M68K_MMU_DF_DT;
tbl_entry &= ~M68K_MMU_DF_DT; tbl_entry &= ~M68K_MMU_DF_DT;
// if (verbose) logerror("PMMU: addr %08x entry %08x entry2 %08x mode %x tofs %x\n", addr_in, tbl_entry, tbl_entry2, tbmode, tofs); // if (verbose) printf("PMMU: addr %08x entry %08x entry2 %08x mode %x tofs %x\n", addr_in, tbl_entry, tbl_entry2, tbmode, tofs);
break; break;
case M68K_MMU_DF_DT1: // early termination descriptor case M68K_MMU_DF_DT1: // early termination descriptor
@ -420,18 +420,18 @@ INLINE UINT32 get_dt3_table_entry(m68ki_cpu_core *m68k, UINT32 tptr, UINT8 fc, U
case M68K_MMU_DF_DT2: // 4-byte table C descriptor case M68K_MMU_DF_DT2: // 4-byte table C descriptor
tofs *= 4; tofs *= 4;
// if (verbose) logerror("PMMU: reading table C entry at %08x\n", tofs + tptr); // if (verbose) printf("PMMU: reading table C entry at %08x\n", tofs + tptr);
tbl_entry = get_dt2_table_entry(m68k, tptr + tofs, ptest); tbl_entry = get_dt2_table_entry(m68k, tptr + tofs, ptest);
tcmode = tbl_entry & M68K_MMU_DF_DT; tcmode = tbl_entry & M68K_MMU_DF_DT;
// if (verbose) logerror("PMMU: addr %08x entry %08x mode %x tofs %x\n", addr_in, tbl_entry, tbmode, tofs); // if (verbose) printf("PMMU: addr %08x entry %08x mode %x tofs %x\n", addr_in, tbl_entry, tbmode, tofs);
break; break;
case M68K_MMU_DF_DT3: // 8-byte table C descriptor case M68K_MMU_DF_DT3: // 8-byte table C descriptor
tofs *= 8; tofs *= 8;
// if (verbose) logerror("PMMU: reading table C entries at %08x\n", tofs + tptr); // if (verbose) printf("PMMU: reading table C entries at %08x\n", tofs + tptr);
tbl_entry = get_dt3_table_entry(m68k, tptr+ tofs, fc, ptest); tbl_entry = get_dt3_table_entry(m68k, tptr+ tofs, fc, ptest);
tcmode = tbl_entry & M68K_MMU_DF_DT; tcmode = tbl_entry & M68K_MMU_DF_DT;
// if (verbose) logerror("PMMU: addr %08x entry %08x entry2 %08x mode %x tofs %x\n", addr_in, tbl_entry, tbl_entry2, tcmode, tofs); // if (verbose) printf("PMMU: addr %08x entry %08x entry2 %08x mode %x tofs %x\n", addr_in, tbl_entry, tbl_entry2, tcmode, tofs);
break; break;
case M68K_MMU_DF_DT1: // termination descriptor case M68K_MMU_DF_DT1: // termination descriptor
@ -500,7 +500,7 @@ INLINE UINT32 get_dt3_table_entry(m68ki_cpu_core *m68k, UINT32 tptr, UINT8 fc, U
} }
} }
//logerror("PMMU: [%08x] => [%08x]\n", addr_in, addr_out); //printf("PMMU: [%08x] => [%08x]\n", addr_in, addr_out);
return addr_out; return addr_out;
} }
@ -513,7 +513,7 @@ INLINE UINT32 get_dt3_table_entry(m68ki_cpu_core *m68k, UINT32 tptr, UINT8 fc, U
UINT32 addr_out = pmmu_translate_addr_with_fc(m68k, addr_in, m68k->mmu_tmp_fc, 0); UINT32 addr_out = pmmu_translate_addr_with_fc(m68k, addr_in, m68k->mmu_tmp_fc, 0);
// if (m68k->mmu_tmp_buserror_occurred > 0) { // if (m68k->mmu_tmp_buserror_occurred > 0) {
// logerror("PMMU: pc=%08x sp=%08x va=%08x pa=%08x - invalid Table mode for level=%d (buserror %d)\n", // printf("PMMU: pc=%08x sp=%08x va=%08x pa=%08x - invalid Table mode for level=%d (buserror %d)\n",
// REG_PPC(m68k), REG_A(m68k)[7], addr_in, addr_out, m68k->mmu_tmp_sr & M68K_MMU_SR_LEVEL_3, // REG_PPC(m68k), REG_A(m68k)[7], addr_in, addr_out, m68k->mmu_tmp_sr & M68K_MMU_SR_LEVEL_3,
// m68k->mmu_tmp_buserror_occurred); // m68k->mmu_tmp_buserror_occurred);
// } // }
@ -532,16 +532,15 @@ void m68881_mmu_ops(m68ki_cpu_core *m68k)
UINT32 ea = m68k->ir & 0x3f; UINT32 ea = m68k->ir & 0x3f;
UINT64 temp64; UINT64 temp64;
// catch the 2 "weird" encodings up front (PBcc) // catch the 2 "weird" encodings up front (PBcc)
if ((m68k->ir & 0xffc0) == 0xf0c0) if ((m68k->ir & 0xffc0) == 0xf0c0)
{ {
logerror("680x0: unhandled PBcc\n"); printf("680x0: unhandled PBcc\n");
return; return;
} }
else if ((m68k->ir & 0xffc0) == 0xf080) else if ((m68k->ir & 0xffc0) == 0xf080)
{ {
logerror("680x0: unhandled PBcc\n"); printf("680x0: unhandled PBcc\n");
return; return;
} }
else // the rest are 1111000xxxXXXXXX where xxx is the instruction family else // the rest are 1111000xxxXXXXXX where xxx is the instruction family
@ -562,7 +561,7 @@ void m68881_mmu_ops(m68ki_cpu_core *m68k)
ptmp = pmmu_translate_addr_with_fc(m68k, ltmp, modes & 0x07, 0); ptmp = pmmu_translate_addr_with_fc(m68k, ltmp, modes & 0x07, 0);
} }
logerror("680x0: PLOADing ATC with logical %08x => phys %08x\n", ltmp, ptmp); printf("680x0: PLOADing ATC with logical %08x => phys %08x\n", ltmp, ptmp);
// FIXME: rw bit? // FIXME: rw bit?
pmmu_atc_add(m68k, ltmp, ptmp, modes & 0x07); pmmu_atc_add(m68k, ltmp, ptmp, modes & 0x07);
return; return;
@ -579,12 +578,12 @@ void m68881_mmu_ops(m68ki_cpu_core *m68k)
} }
else if (modes == 0x2800) // PVALID (FORMAT 1) else if (modes == 0x2800) // PVALID (FORMAT 1)
{ {
logerror("680x0: unhandled PVALID1\n"); printf("680x0: unhandled PVALID1\n");
return; return;
} }
else if ((modes & 0xfff8) == 0x2c00) // PVALID (FORMAT 2) else if ((modes & 0xfff8) == 0x2c00) // PVALID (FORMAT 2)
{ {
logerror("680x0: unhandled PVALID2\n"); printf("680x0: unhandled PVALID2\n");
return; return;
} }
else if ((modes & 0xe000) == 0x8000) // PTEST else if ((modes & 0xe000) == 0x8000) // PTEST
@ -607,7 +606,7 @@ void m68881_mmu_ops(m68ki_cpu_core *m68k)
p_addr = pmmu_translate_addr_with_fc(m68k, v_addr, fc, 1); p_addr = pmmu_translate_addr_with_fc(m68k, v_addr, fc, 1);
m68k->mmu_sr = m68k->mmu_tmp_sr; m68k->mmu_sr = m68k->mmu_tmp_sr;
// logerror("PMMU: pc=%08x sp=%08x va=%08x pa=%08x PTEST fc=%x level=%x mmu_sr=%04x\n", // printf("PMMU: pc=%08x sp=%08x va=%08x pa=%08x PTEST fc=%x level=%x mmu_sr=%04x\n",
// m68k->ppc, REG_A(m68k)[7], v_addr, p_addr, fc, (modes >> 10) & 0x07, m68k->mmu_sr); // m68k->ppc, REG_A(m68k)[7], v_addr, p_addr, fc, (modes >> 10) & 0x07, m68k->mmu_sr);
if (modes & 0x100) if (modes & 0x100)
@ -629,29 +628,29 @@ void m68881_mmu_ops(m68ki_cpu_core *m68k)
{ {
case 0x02: // transparent translation register 0 case 0x02: // transparent translation register 0
WRITE_EA_32(m68k, ea, m68k->mmu_tt0); WRITE_EA_32(m68k, ea, m68k->mmu_tt0);
// logerror("PMMU: pc=%x PMOVE from mmu_tt0=%08x\n", m68k->ppc, m68k->mmu_tt0); // printf("PMMU: pc=%x PMOVE from mmu_tt0=%08x\n", m68k->ppc, m68k->mmu_tt0);
break; break;
case 0x03: // transparent translation register 1 case 0x03: // transparent translation register 1
WRITE_EA_32(m68k, ea, m68k->mmu_tt1); WRITE_EA_32(m68k, ea, m68k->mmu_tt1);
// logerror("PMMU: pc=%x PMOVE from mmu_tt1=%08x\n", m68k->ppc, m68k->mmu_tt1); // printf("PMMU: pc=%x PMOVE from mmu_tt1=%08x\n", m68k->ppc, m68k->mmu_tt1);
break; break;
case 0x10: // translation control register case 0x10: // translation control register
WRITE_EA_32(m68k, ea, m68k->mmu_tc); WRITE_EA_32(m68k, ea, m68k->mmu_tc);
// logerror("PMMU: pc=%x PMOVE from mmu_tc=%08x\n", m68k->ppc, m68k->mmu_tc); // printf("PMMU: pc=%x PMOVE from mmu_tc=%08x\n", m68k->ppc, m68k->mmu_tc);
break; break;
case 0x12: // supervisor root pointer case 0x12: // supervisor root pointer
WRITE_EA_64(m68k, ea, (UINT64)m68k->mmu_srp_limit<<32 | (UINT64)m68k->mmu_srp_aptr); WRITE_EA_64(m68k, ea, (UINT64)m68k->mmu_srp_limit<<32 | (UINT64)m68k->mmu_srp_aptr);
// logerror("PMMU: pc=%x PMOVE from SRP limit = %08x, aptr = %08x\n", REG_PPC(m68k), m68k->mmu_srp_limit, m68k->mmu_srp_aptr); // printf("PMMU: pc=%x PMOVE from SRP limit = %08x, aptr = %08x\n", REG_PPC(m68k), m68k->mmu_srp_limit, m68k->mmu_srp_aptr);
break; break;
case 0x13: // CPU root pointer case 0x13: // CPU root pointer
WRITE_EA_64(m68k, ea, (UINT64)m68k->mmu_crp_limit<<32 | (UINT64)m68k->mmu_crp_aptr); WRITE_EA_64(m68k, ea, (UINT64)m68k->mmu_crp_limit<<32 | (UINT64)m68k->mmu_crp_aptr);
// logerror("PMMU: pc=%x PMOVE from CRP limit = %08x, aptr = %08x\n", REG_PPC(m68k), m68k->mmu_crp_limit, m68k->mmu_crp_aptr); // printf("PMMU: pc=%x PMOVE from CRP limit = %08x, aptr = %08x\n", REG_PPC(m68k), m68k->mmu_crp_limit, m68k->mmu_crp_aptr);
break; break;
default: default:
logerror("680x0: PMOVE from unknown MMU register %x, PC %x\n", (modes>>10) & 7, m68k->pc); printf("680x0: PMOVE from unknown MMU register %x, PC %x\n", (modes>>10) & 7, m68k->pc);
break; break;
} }
@ -676,7 +675,7 @@ void m68881_mmu_ops(m68ki_cpu_core *m68k)
break; break;
case 1: case 1:
logerror("680x0: unknown PMOVE case 1, PC %x\n", m68k->pc); printf("680x0: unknown PMOVE case 1, PC %x\n", m68k->pc);
break; break;
case 2: case 2:
@ -684,17 +683,17 @@ void m68881_mmu_ops(m68ki_cpu_core *m68k)
{ {
case 0: // translation control register case 0: // translation control register
m68k->mmu_tc = READ_EA_32(m68k, ea); m68k->mmu_tc = READ_EA_32(m68k, ea);
// logerror("PMMU: TC = %08x\n", m68k->mmu_tc); // printf("PMMU: TC = %08x\n", m68k->mmu_tc);
if (m68k->mmu_tc & 0x80000000) if (m68k->mmu_tc & 0x80000000)
{ {
m68k->pmmu_enabled = 1; m68k->pmmu_enabled = 1;
// logerror("PMMU enabled\n"); // printf("PMMU enabled\n");
} }
else else
{ {
m68k->pmmu_enabled = 0; m68k->pmmu_enabled = 0;
// logerror("PMMU disabled\n"); // printf("PMMU disabled\n");
} }
if (!(modes & 0x100)) // flush ATC on moves to TC, SRP, CRP with FD bit clear if (!(modes & 0x100)) // flush ATC on moves to TC, SRP, CRP with FD bit clear
@ -707,7 +706,7 @@ void m68881_mmu_ops(m68ki_cpu_core *m68k)
temp64 = READ_EA_64(m68k, ea); temp64 = READ_EA_64(m68k, ea);
m68k->mmu_srp_limit = (temp64>>32) & 0xffffffff; m68k->mmu_srp_limit = (temp64>>32) & 0xffffffff;
m68k->mmu_srp_aptr = temp64 & 0xffffffff; m68k->mmu_srp_aptr = temp64 & 0xffffffff;
// logerror("PMMU: SRP limit = %08x aptr = %08x\n", m68k->mmu_srp_limit, m68k->mmu_srp_aptr); // printf("PMMU: SRP limit = %08x aptr = %08x\n", m68k->mmu_srp_limit, m68k->mmu_srp_aptr);
if (!(modes & 0x100)) if (!(modes & 0x100))
{ {
pmmu_atc_flush(m68k); pmmu_atc_flush(m68k);
@ -718,7 +717,7 @@ void m68881_mmu_ops(m68ki_cpu_core *m68k)
temp64 = READ_EA_64(m68k, ea); temp64 = READ_EA_64(m68k, ea);
m68k->mmu_crp_limit = (temp64>>32) & 0xffffffff; m68k->mmu_crp_limit = (temp64>>32) & 0xffffffff;
m68k->mmu_crp_aptr = temp64 & 0xffffffff; m68k->mmu_crp_aptr = temp64 & 0xffffffff;
// logerror("PMMU: CRP limit = %08x aptr = %08x\n", m68k->mmu_crp_limit, m68k->mmu_crp_aptr); // printf("PMMU: CRP limit = %08x aptr = %08x\n", m68k->mmu_crp_limit, m68k->mmu_crp_aptr);
if (!(modes & 0x100)) if (!(modes & 0x100))
{ {
pmmu_atc_flush(m68k); pmmu_atc_flush(m68k);
@ -726,7 +725,7 @@ void m68881_mmu_ops(m68ki_cpu_core *m68k)
break; break;
default: default:
logerror("680x0: PMOVE to unknown MMU register %x, PC %x\n", (modes>>10) & 7, m68k->pc); printf("680x0: PMOVE to unknown MMU register %x, PC %x\n", (modes>>10) & 7, m68k->pc);
break; break;
} }
break; break;
@ -734,7 +733,7 @@ void m68881_mmu_ops(m68ki_cpu_core *m68k)
case 3: // MMU status case 3: // MMU status
{ {
UINT32 temp = READ_EA_32(m68k, ea); UINT32 temp = READ_EA_32(m68k, ea);
logerror("680x0: unsupported PMOVE %x to MMU status, PC %x\n", temp, m68k->pc); printf("680x0: unsupported PMOVE %x to MMU status, PC %x\n", temp, m68k->pc);
} }
break; break;
} }
@ -753,7 +752,7 @@ void m68881_mmu_ops(m68ki_cpu_core *m68k)
break; break;
default: default:
logerror("680x0: unknown PMOVE mode %x (modes %04x) (PC %x)\n", (modes>>13) & 0x7, modes, m68k->pc); printf("680x0: unknown PMOVE mode %x (modes %04x) (PC %x)\n", (modes>>13) & 0x7, modes, m68k->pc);
break; break;
} }
@ -761,7 +760,7 @@ void m68881_mmu_ops(m68ki_cpu_core *m68k)
break; break;
default: default:
logerror("680x0: unknown PMMU instruction group %d\n", (m68k->ir>>9) & 0x7); printf("680x0: unknown PMMU instruction group %d\n", (m68k->ir>>9) & 0x7);
break; break;
} }
} }

14
src/mame/drivers/seta2.c
View File

@ -2204,7 +2204,7 @@ static MACHINE_RESET( funcube )
static MACHINE_CONFIG_START( funcube, seta2_state ) static MACHINE_CONFIG_START( funcube, seta2_state )
MCFG_CPU_ADD("maincpu", M68040, XTAL_25_447MHz) // !! XCF5206 actually !! MCFG_CPU_ADD("maincpu", MCF5206E, XTAL_25_447MHz)
MCFG_CPU_PROGRAM_MAP(funcube_map) MCFG_CPU_PROGRAM_MAP(funcube_map)
MCFG_CPU_VBLANK_INT_HACK(funcube_interrupt,2) MCFG_CPU_VBLANK_INT_HACK(funcube_interrupt,2)
@ -2406,12 +2406,7 @@ static DRIVER_INIT( funcube2 )
UINT32 *main_cpu = (UINT32 *) machine.region("maincpu")->base(); UINT32 *main_cpu = (UINT32 *) machine.region("maincpu")->base();
UINT16 *sub_cpu = (UINT16 *) machine.region("sub")->base(); UINT16 *sub_cpu = (UINT16 *) machine.region("sub")->base();
main_cpu[0x810/4] = 0xe0214e71; main_cpu[0xa5c/4] = 0x4e713e3c; // PIC protection?
main_cpu[0x814/4] = 0x4e71203c;
main_cpu[0x81c/4] = 0x4e714e71;
main_cpu[0xa5c/4] = 0x4e713e3c;
main_cpu[0xa74/4] = 0x4e713e3c; main_cpu[0xa74/4] = 0x4e713e3c;
main_cpu[0xa8c/4] = 0x4e7141f9; main_cpu[0xa8c/4] = 0x4e7141f9;
@ -2432,11 +2427,6 @@ static DRIVER_INIT( funcube3 )
UINT32 *main_cpu = (UINT32 *) machine.region("maincpu")->base(); UINT32 *main_cpu = (UINT32 *) machine.region("maincpu")->base();
UINT16 *sub_cpu = (UINT16 *) machine.region("sub")->base(); UINT16 *sub_cpu = (UINT16 *) machine.region("sub")->base();
main_cpu[0x450/4] = 0xe0214e71;
main_cpu[0x454/4] = 0x4e71203c;
main_cpu[0x45c/4] = 0x4e714e71;
main_cpu[0x008bc/4] = 0x4a804e71; main_cpu[0x008bc/4] = 0x4a804e71;
main_cpu[0x19f0c/4] = 0x4e714e71; main_cpu[0x19f0c/4] = 0x4e714e71;
main_cpu[0x19fb8/4] = 0x4e714e71; main_cpu[0x19fb8/4] = 0x4e714e71;