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drcbex64: some more micro-optimization (nw)
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392ceebfad
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@ -4725,22 +4725,24 @@ void drcbe_x64::op_muls(x86code *&dst, const instruction &inst)
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// 32-bit destination with memory/immediate or register/immediate
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if (!compute_hi && !src1p.is_immediate() && src2p.is_immediate())
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{
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int dstreg = dstp.is_int_register() ? dstp.ireg() : REG_EAX;
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if (src1p.is_memory())
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emit_imul_r32_m32_imm(dst, REG_EAX, MABS(src1p.memory()), src2p.immediate()); // imul eax,[src1p],src2p
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emit_imul_r32_m32_imm(dst, dstreg, MABS(src1p.memory()), src2p.immediate()); // imul dstreg,[src1p],src2p
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else if (src1p.is_int_register())
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emit_imul_r32_r32_imm(dst, REG_EAX, src1p.ireg(), src2p.immediate()); // imul eax,src1p,src2p
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emit_mov_p32_r32(dst, dstp, REG_EAX); // mov dstp,eax
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emit_imul_r32_r32_imm(dst, dstreg, src1p.ireg(), src2p.immediate()); // imul dstreg,src1p,src2p
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emit_mov_p32_r32(dst, dstp, dstreg); // mov dstp,eax
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}
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// 32-bit destination, general case
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else if (!compute_hi)
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{
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emit_mov_r32_p32(dst, REG_EAX, src1p); // mov eax,src1p
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int dstreg = dstp.is_int_register() ? dstp.ireg() : REG_EAX;
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emit_mov_r32_p32(dst, dstreg, src1p); // mov dstreg,src1p
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if (src2p.is_memory())
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emit_imul_r32_m32(dst, REG_EAX, MABS(src2p.memory())); // imul eax,[src2p]
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emit_imul_r32_m32(dst, dstreg, MABS(src2p.memory())); // imul dstreg,[src2p]
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else if (src2p.is_int_register())
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emit_imul_r32_r32(dst, REG_EAX, src2p.ireg()); // imul eax,src2p
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emit_mov_p32_r32(dst, dstp, REG_EAX); // mov dstp,eax
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emit_imul_r32_r32(dst, dstreg, src2p.ireg()); // imul dstreg,src2p
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emit_mov_p32_r32(dst, dstp, dstreg); // mov dstp,dstreg
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}
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// 64-bit destination, general case
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@ -4803,22 +4805,24 @@ void drcbe_x64::op_muls(x86code *&dst, const instruction &inst)
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// 64-bit destination with memory/immediate or register/immediate
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if (!compute_hi && !src1p.is_immediate() && src2p.is_immediate() && short_immediate(src2p.immediate()))
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{
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int dstreg = dstp.is_int_register() ? dstp.ireg() : REG_RAX;
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if (src1p.is_memory())
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emit_imul_r64_m64_imm(dst, REG_RAX, MABS(src1p.memory()), src2p.immediate());// imul rax,[src1p],src2p
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emit_imul_r64_m64_imm(dst, dstreg, MABS(src1p.memory()), src2p.immediate());// imul dstreg,[src1p],src2p
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else if (src1p.is_int_register())
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emit_imul_r64_r64_imm(dst, REG_RAX, src1p.ireg(), src2p.immediate()); // imul rax,src1p,src2p
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emit_mov_p64_r64(dst, dstp, REG_RAX); // mov dstp,rax
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emit_imul_r64_r64_imm(dst, dstreg, src1p.ireg(), src2p.immediate()); // imul rax,src1p,src2p
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emit_mov_p64_r64(dst, dstp, dstreg); // mov dstp,rax
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}
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// 64-bit destination, general case
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else if (!compute_hi)
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{
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emit_mov_r64_p64(dst, REG_RAX, src1p); // mov rax,src1p
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int dstreg = dstp.is_int_register() ? dstp.ireg() : REG_RAX;
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emit_mov_r64_p64(dst, dstreg, src1p); // mov dstreg,src1p
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if (src2p.is_memory())
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emit_imul_r64_m64(dst, REG_RAX, MABS(src2p.memory())); // imul rax,[src2p]
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emit_imul_r64_m64(dst, dstreg, MABS(src2p.memory())); // imul dstreg,[src2p]
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else if (src2p.is_int_register())
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emit_imul_r64_r64(dst, REG_RAX, src2p.ireg()); // imul rax,src2p
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emit_mov_p64_r64(dst, dstp, REG_RAX); // mov dstp,rax
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emit_imul_r64_r64(dst, dstreg, src2p.ireg()); // imul dstreg,src2p
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emit_mov_p64_r64(dst, dstp, dstreg); // mov dstp,dstreg
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}
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// 128-bit destination, general case
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@ -5259,6 +5263,10 @@ void drcbe_x64::op_xor(x86code *&dst, const instruction &inst)
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else if (dstp.is_memory() && dstp == src2p)
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emit_xor_m32_p32(dst, MABS(dstp.memory()), src1p, inst); // xor [dstp],src1p
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// dstp == src1p register
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else if (dstp.is_int_register() && dstp == src1p)
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emit_xor_r32_p32(dst, dstp.ireg(), src2p, inst); // xor dstp,src2p
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// general case
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else
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{
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@ -5279,6 +5287,10 @@ void drcbe_x64::op_xor(x86code *&dst, const instruction &inst)
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else if (dstp.is_memory() && dstp == src2p)
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emit_xor_m64_p64(dst, MABS(dstp.memory()), src1p, inst); // xor [dstp],src1p
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// dstp == src1p register
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else if (dstp.is_int_register() && dstp == src1p)
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emit_xor_r64_p64(dst, dstp.ireg(), src2p, inst); // xor dstp,src2p
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// general case
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else
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{
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