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https://github.com/holub/mame
synced 2025-04-19 15:11:37 +03:00
Create stub MSM66573 device so Challenge Gear driver can have a CPU type
This commit is contained in:
AJR
parent
9a57e389bf
commit
c6a47e34df
@ -4086,9 +4086,17 @@ if opt_tool(CPUS, "PALM") then
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end
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--------------------------------------------------
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-- Oki OLMS-66K/nX-8 series, disassembler only
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-- Oki OLMS-66K/nX-8 series
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--@src/devices/cpu/olms66k/msm665xx.h,CPUS["OLMS66K"] = true
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--------------------------------------------------
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if CPUS["OLMS66K"] then
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files {
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MAME_DIR .. "src/devices/cpu/olms66k/msm665xx.cpp",
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MAME_DIR .. "src/devices/cpu/olms66k/msm665xx.h",
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}
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end
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if opt_tool(CPUS, "OLMS66K") then
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table.insert(disasm_files , MAME_DIR .. "src/devices/cpu/olms66k/nx8dasm.cpp")
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table.insert(disasm_files , MAME_DIR .. "src/devices/cpu/olms66k/nx8dasm.h")
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233
src/devices/cpu/olms66k/msm665xx.cpp
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233
src/devices/cpu/olms66k/msm665xx.cpp
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@ -0,0 +1,233 @@
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// license:BSD-3-Clause
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// copyright-holders:AJR
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/****************************************************************************
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Oki MSM665xx 16-bit microcontroller family (nX-8/500S core)
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Currently this is just one stub device with no actual execution core.
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****************************************************************************/
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#include "emu.h"
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#include "msm665xx.h"
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#include "nx8dasm.h"
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// device type definition
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DEFINE_DEVICE_TYPE(MSM66573, msm66573_device, "msm66573", "Oki MSM66573")
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msm665xx_device::msm665xx_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock, address_map_constructor mem_map, address_map_constructor data_map)
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: cpu_device(mconfig, type, tag, owner, clock)
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, m_program_config("program", ENDIANNESS_LITTLE, 8, 20, 0, mem_map)
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, m_data_config("iram", ENDIANNESS_LITTLE, 16, 20, 0, data_map)
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, m_acc(0)
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, m_pc(0)
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, m_ppc(0)
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, m_psw(0)
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, m_lrb(0)
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, m_ssp(0)
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, m_csr(0)
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, m_dsr(0)
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, m_tsr(0)
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, m_romwin(0x30)
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, m_icount(0)
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{
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}
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device_memory_interface::space_config_vector msm665xx_device::memory_space_config() const
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{
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return space_config_vector {
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std::make_pair(AS_PROGRAM, &m_program_config),
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std::make_pair(AS_DATA, &m_data_config)
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};
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}
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std::unique_ptr<util::disasm_interface> msm665xx_device::create_disassembler()
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{
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return std::make_unique<nx8_500s_disassembler>(m_psw);
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}
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msm66573_device::msm66573_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock)
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: msm665xx_device(mconfig, MSM66573, tag, owner, clock,
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address_map_constructor(), // TODO: 64KB internal ROM (optional)
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address_map_constructor(FUNC(msm66573_device::data_map), this))
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{
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}
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void msm66573_device::data_map(address_map &map)
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{
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map(0x00000, 0x00001).rw(FUNC(msm66573_device::ssp_r), FUNC(msm66573_device::ssp_w));
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map(0x00002, 0x00003).rw(FUNC(msm66573_device::lrb_r), FUNC(msm66573_device::lrb_w));
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map(0x00004, 0x00005).rw(FUNC(msm66573_device::psw_r), FUNC(msm66573_device::psw_w));
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map(0x00006, 0x00007).rw(FUNC(msm66573_device::acc_r), FUNC(msm66573_device::acc_w));
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map(0x00008, 0x00008).rw(FUNC(msm66573_device::tsr_r), FUNC(msm66573_device::tsr_w));
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map(0x00009, 0x00009).rw(FUNC(msm66573_device::dsr_r), FUNC(msm66573_device::dsr_w));
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map(0x0000b, 0x0000b).rw(FUNC(msm66573_device::romwin_r), FUNC(msm66573_device::romwin_w));
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// TODO: many, many other SFRs
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map(0x00200, 0x011ff).ram().share("internal");
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}
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void msm665xx_device::device_start()
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{
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// get address spaces and access caches
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space(AS_PROGRAM).specific(m_program_space);
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space(AS_PROGRAM).cache(m_program_cache);
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space(AS_DATA).specific(m_data_space);
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space(AS_DATA).cache(m_data_cache);
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set_icountptr(m_icount);
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// debug state
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state_add(MSM665XX_ACC, "ACC", m_acc);
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state_add(MSM665XX_PC, "PC", m_pc);
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state_add<u32>(STATE_GENPC, "GENPC",
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[this]() { return u32(m_csr) << 16 | m_pc; },
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[this](u32 data) { m_csr = (data >> 16) & 0x0f; m_pc = data & 0xffff; m_ppc = data & 0xfffff; }
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).mask(0xfffff).noshow();
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state_add<u32>(STATE_GENPCBASE, "GENPCBASE", m_ppc,
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[this](u32 data) { m_csr = (data >> 16) & 0x0f; m_pc = data & 0xffff; m_ppc = data & 0xfffff; }
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).mask(0xfffff).noshow();
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state_add(MSM665XX_PSW, "PSW", m_psw);
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//state_add(STATE_GENFLAGS, "FLAGS", m_psw).formatstr("%9s").noshow(); // TODO
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state_add(MSM665XX_LRB, "LRB", m_lrb);
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state_add(MSM665XX_SSP, "SSP", m_ssp);
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u16 *fixed = static_cast<u16 *>(memshare("internal")->ptr());
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for (int n = 0; n < 4; n++)
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state_add<u16>(MSM665XX_PR0 + n, std::array<const char *, 4>{{"X1", "X2", "DP", "USP"}}[n],
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[this, fixed, n]() { return fixed[(m_psw & 0x07) << 2 | n]; },
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[this, fixed, n](u16 data) { fixed[(m_psw & 0x07) << 2 | n] = data; }
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);
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for (int n = 0; n < 4; n++)
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state_add<u16>(MSM665XX_ER0 + n, util::string_format("R%d", n).c_str(),
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[this, fixed, n]() { return fixed[(m_lrb & 0x00ff) << 2 | n]; },
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[this, fixed, n](u16 data) { fixed[(m_lrb & 0x00ff) << 2 | n] = data; }
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);
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for (int n = 0; n < 8; n++)
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state_add<u8>(MSM665XX_R0 + n, util::string_format("R%d", n).c_str(),
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[this, fixed, n]() { return util::little_endian_cast<const u8>(fixed)[(m_lrb & 0x00ff) << 3 | n]; },
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[this, fixed, n](u8 data) { util::little_endian_cast<u8>(fixed)[(m_lrb & 0x00ff) << 3 | n] = data; }
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).noshow();
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state_add(MSM665XX_CSR, "CSR", m_csr).mask(0x0f);
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state_add(MSM665XX_DSR, "DSR", m_dsr).mask(0x0f);
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state_add(MSM665XX_TSR, "TSR", m_tsr).mask(0x0f);
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state_add(MSM665XX_ROMWIN, "ROMWIN", m_romwin);
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// save state
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save_item(NAME(m_acc));
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save_item(NAME(m_pc));
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save_item(NAME(m_ppc));
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save_item(NAME(m_psw));
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save_item(NAME(m_lrb));
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save_item(NAME(m_ssp));
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save_item(NAME(m_csr));
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save_item(NAME(m_dsr));
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save_item(NAME(m_tsr));
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save_item(NAME(m_romwin));
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}
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void msm665xx_device::device_reset()
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{
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// PC will be initialized from vector following reset; LRB and ROMWIN are undefined at reset
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m_acc = 0;
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m_psw = 0;
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m_ssp = 0xffff;
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m_csr = 0;
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m_dsr = 0;
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m_tsr = 0;
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}
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u16 msm665xx_device::ssp_r()
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{
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return m_ssp;
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}
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void msm665xx_device::ssp_w(u16 data)
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{
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m_ssp = data;
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}
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u16 msm665xx_device::lrb_r()
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{
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return m_lrb;
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}
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void msm665xx_device::lrb_w(offs_t offset, u16 data, u16 mem_mask)
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{
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m_lrb = (m_lrb & ~mem_mask) | (data & mem_mask);
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}
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u16 msm665xx_device::psw_r()
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{
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return m_psw;
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}
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void msm665xx_device::psw_w(offs_t offset, u16 data, u16 mem_mask)
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{
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m_psw = (m_psw & ~mem_mask) | (data & mem_mask);
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}
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u16 msm665xx_device::acc_r()
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{
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return m_acc;
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}
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void msm665xx_device::acc_w(offs_t offset, u16 data, u16 mem_mask)
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{
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m_acc = (m_acc & ~mem_mask) | (data & mem_mask);
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}
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u8 msm665xx_device::dsr_r()
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{
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return m_dsr;
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}
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void msm665xx_device::dsr_w(u8 data)
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{
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m_dsr = data & 0x0f;
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}
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u8 msm665xx_device::tsr_r()
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{
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return m_tsr;
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}
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void msm665xx_device::tsr_w(u8 data)
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{
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m_tsr = data & 0x0f;
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}
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u8 msm665xx_device::romwin_r()
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{
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return m_romwin;
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}
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void msm665xx_device::romwin_w(u8 data)
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{
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// ROMWIN is only supposed to be written once after reset
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m_romwin = data | 0x30;
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}
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void msm665xx_device::execute_run()
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{
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m_pc = m_program_cache.read_word(0);
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m_ppc = m_pc;
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debugger_instruction_hook(m_pc);
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// TODO
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m_icount = 0;
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}
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void msm665xx_device::state_string_export(const device_state_entry &entry, std::string &str) const
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{
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switch (entry.index())
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{
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case STATE_GENFLAGS:
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// TODO
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break;
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}
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}
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98
src/devices/cpu/olms66k/msm665xx.h
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98
src/devices/cpu/olms66k/msm665xx.h
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@ -0,0 +1,98 @@
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// license:BSD-3-Clause
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// copyright-holders:AJR
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/**********************************************************************
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Oki MSM665xx 16-bit microcontroller family (nX-8/500S core)
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**********************************************************************/
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#ifndef MAME_CPU_OLMS66K_MSM665XX_H
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#define MAME_CPU_OLMS66K_MSM665XX_H
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#pragma once
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class msm665xx_device : public cpu_device
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{
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public:
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enum {
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MSM665XX_ACC, MSM665XX_PC, MSM665XX_PSW, MSM665XX_LRB, MSM665XX_SSP,
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MSM665XX_PR0, MSM665XX_X1 = MSM665XX_PR0,
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MSM665XX_PR1, MSM665XX_X2 = MSM665XX_PR1,
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MSM665XX_PR2, MSM665XX_DP = MSM665XX_PR2,
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MSM665XX_PR3, MSM665XX_USP = MSM665XX_PR3,
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MSM665XX_ER0, MSM665XX_ER1, MSM665XX_ER2, MSM665XX_ER3,
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MSM665XX_R0, MSM665XX_R1, MSM665XX_R2, MSM665XX_R3,
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MSM665XX_R4, MSM665XX_R5, MSM665XX_R6, MSM665XX_R7,
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MSM665XX_CSR, MSM665XX_DSR, MSM665XX_TSR,
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MSM665XX_ROMWIN
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};
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// TODO: port callbacks
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protected:
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msm665xx_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock, address_map_constructor mem_map, address_map_constructor data_map);
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virtual void device_start() override;
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virtual void device_reset() override;
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virtual std::unique_ptr<util::disasm_interface> create_disassembler() override;
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virtual void execute_run() override;
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virtual space_config_vector memory_space_config() const override;
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virtual void state_string_export(const device_state_entry &entry, std::string &str) const override;
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u16 ssp_r();
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void ssp_w(u16 data);
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u16 lrb_r();
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void lrb_w(offs_t offset, u16 data, u16 mem_mask);
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u16 psw_r();
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void psw_w(offs_t offset, u16 data, u16 mem_mask);
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u16 acc_r();
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void acc_w(offs_t offset, u16 data, u16 mem_mask);
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u8 dsr_r();
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void dsr_w(u8 data);
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u8 tsr_r();
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void tsr_w(u8 data);
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u8 romwin_r();
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void romwin_w(u8 data);
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private:
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address_space_config m_program_config;
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address_space_config m_data_config;
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memory_access<20, 0, 0, ENDIANNESS_LITTLE>::cache m_program_cache;
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memory_access<20, 0, 0, ENDIANNESS_LITTLE>::specific m_program_space;
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memory_access<20, 1, 0, ENDIANNESS_LITTLE>::cache m_data_cache;
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memory_access<20, 1, 0, ENDIANNESS_LITTLE>::specific m_data_space;
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u16 m_acc;
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u16 m_pc;
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u32 m_ppc;
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u16 m_psw;
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u16 m_lrb;
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u16 m_ssp;
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u8 m_csr;
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u8 m_dsr;
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u8 m_tsr;
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u8 m_romwin;
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s32 m_icount;
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};
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class msm66573_device : public msm665xx_device
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{
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public:
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// device type constructor
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msm66573_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock);
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private:
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void data_map(address_map &map);
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};
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// device type declaration
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DECLARE_DEVICE_TYPE(MSM66573, msm66573_device)
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#endif // MAME_CPU_OLMS66K_MSM665XX_H
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