mirror of
https://github.com/holub/mame
synced 2025-06-15 00:47:03 +03:00
Merge branch 'master' of https://github.com/mamedev/mame
This commit is contained in:
Robbbert
commit
c7d667d41a
@ -1197,7 +1197,7 @@ void namcos22_state::syscon_mcucontrol(offs_t offset, u8 data)
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m_mcu->set_input_line(INPUT_LINE_RESET, data ? CLEAR_LINE : ASSERT_LINE);
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}
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READ8_MEMBER(namcos22_state::syscon_r)
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u8 namcos22_state::syscon_r(offs_t offset)
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{
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return m_syscontrol[offset];
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}
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@ -1242,7 +1242,7 @@ READ8_MEMBER(namcos22_state::syscon_r)
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0x1c: dsp control
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*/
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WRITE8_MEMBER(namcos22_state::ss22_syscon_w)
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void namcos22_state::ss22_syscon_w(offs_t offset, u8 data)
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{
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switch (offset)
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{
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@ -1345,7 +1345,7 @@ INTERRUPT_GEN_MEMBER(namcos22s_state::namcos22s_interrupt)
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0x1a: 0 or 1 or 0xff -> DSP control
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0x1b: ?
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*/
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WRITE8_MEMBER(namcos22_state::s22_syscon_w)
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void namcos22_state::s22_syscon_w(offs_t offset, u8 data)
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{
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switch (offset)
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{
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@ -1463,23 +1463,23 @@ INTERRUPT_GEN_MEMBER(namcos22_state::namcos22_interrupt)
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}
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READ16_MEMBER(namcos22_state::namcos22_shared_r)
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u16 namcos22_state::namcos22_shared_r(offs_t offset)
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{
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return m_shareram[offset];
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}
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WRITE16_MEMBER(namcos22_state::namcos22_shared_w)
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void namcos22_state::namcos22_shared_w(offs_t offset, u16 data, u16 mem_mask)
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{
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COMBINE_DATA(&m_shareram[offset]);
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}
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READ32_MEMBER(namcos22_state::namcos22_dspram_r)
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u32 namcos22_state::namcos22_dspram_r(offs_t offset)
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{
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return m_polygonram[offset] | 0xff000000; // only d0-23 are connected
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}
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WRITE32_MEMBER(namcos22_state::namcos22_dspram_w)
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void namcos22_state::namcos22_dspram_w(offs_t offset, u32 data, u32 mem_mask)
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{
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if (ACCESSING_BITS_16_23)
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{
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@ -1491,7 +1491,7 @@ WRITE32_MEMBER(namcos22_state::namcos22_dspram_w)
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}
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READ16_MEMBER(namcos22_state::namcos22_keycus_r)
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u16 namcos22_state::namcos22_keycus_r(offs_t offset)
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{
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// Like other Namco hardware, this chip is used for protection as well as
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// reading random values in some games.
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@ -1556,7 +1556,7 @@ READ16_MEMBER(namcos22_state::namcos22_keycus_r)
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return m_keycus_rng;
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}
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WRITE16_MEMBER(namcos22_state::namcos22_keycus_w)
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void namcos22_state::namcos22_keycus_w(offs_t offset, u16 data, u16 mem_mask)
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{
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// for obfuscating keycus and/or random seed?
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}
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@ -1583,18 +1583,14 @@ WRITE16_MEMBER(namcos22_state::namcos22_portbit_w)
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m_portbits[offset] = m_custom[offset].read_safe(0xffff);
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}
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READ16_MEMBER(namcos22_state::namcos22_dipswitch_r)
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{
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return m_dsw->read();
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}
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WRITE16_MEMBER(namcos22_state::namcos22_cpuleds_w)
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void namcos22_state::namcos22_cpuleds_w(offs_t offset, u32 data, u32 mem_mask)
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{
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// 8 leds on cpu board, 0=on 1=off
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// on System22: two rows of 4 red leds
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// on SS22: GYRGYRGY green/yellow/red
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COMBINE_DATA(&m_cpuled_data);
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for (int i = 0; i < 8; i++)
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m_cpuled[i] = (~data << i & 0x80) ? 0 : 1;
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m_cpuled_out[i] = (~data << i & 0x800000) ? 0 : 1;
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}
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WRITE32_MEMBER(namcos22s_state::namcos22s_chipselect_w)
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@ -1704,7 +1700,7 @@ void namcos22_state::namcos22_am(address_map &map)
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* 0x50000000 - DIPSW3
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* 0x50000001 - DIPSW2
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*/
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map(0x50000000, 0x50000003).rw(FUNC(namcos22_state::namcos22_dipswitch_r), FUNC(namcos22_state::namcos22_cpuleds_w)).umask32(0xffff0000);
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map(0x50000000, 0x50000003).portr("DSW").w(FUNC(namcos22_state::namcos22_cpuleds_w));
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map(0x50000008, 0x5000000b).rw(FUNC(namcos22_state::namcos22_portbit_r), FUNC(namcos22_state::namcos22_portbit_w));
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/**
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@ -1825,8 +1821,8 @@ void namcos22s_state::namcos22s_am(address_map &map)
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map(0x400000, 0x40001f).rw(FUNC(namcos22s_state::namcos22_keycus_r), FUNC(namcos22s_state::namcos22_keycus_w));
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map(0x410000, 0x413fff).ram(); // C139 SCI buffer
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map(0x420000, 0x42000f).rw(FUNC(namcos22s_state::namcos22_sci_r), FUNC(namcos22s_state::namcos22_sci_w)); // C139 SCI registers
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map(0x430000, 0x430003).w(FUNC(namcos22s_state::namcos22_cpuleds_w)).umask32(0xffff0000);
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map(0x440000, 0x440003).r(FUNC(namcos22s_state::namcos22_dipswitch_r)).umask32(0xffff0000);
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map(0x430000, 0x430003).w(FUNC(namcos22s_state::namcos22_cpuleds_w));
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map(0x440000, 0x440003).portr("DSW");
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map(0x450008, 0x45000b).rw(FUNC(namcos22s_state::namcos22_portbit_r), FUNC(namcos22s_state::namcos22_portbit_w));
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map(0x460000, 0x463fff).rw(m_eeprom, FUNC(eeprom_parallel_28xx_device::read), FUNC(eeprom_parallel_28xx_device::write)).umask32(0xff00ff00);
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map(0x700000, 0x70001f).rw(FUNC(namcos22s_state::syscon_r), FUNC(namcos22s_state::ss22_syscon_w));
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@ -1938,7 +1934,7 @@ void namcos22_state::slave_enable(bool enable)
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}
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READ16_MEMBER(namcos22_state::namcos22_dspram16_r)
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u16 namcos22_state::namcos22_dspram16_r(offs_t offset)
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{
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u32 value = m_polygonram[offset];
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@ -1966,7 +1962,7 @@ READ16_MEMBER(namcos22_state::namcos22_dspram16_r)
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return value;
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}
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WRITE16_MEMBER(namcos22_state::namcos22_dspram16_w)
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void namcos22_state::namcos22_dspram16_w(offs_t offset, u16 data, u16 mem_mask)
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{
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u32 value = m_polygonram[offset];
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u16 lo = value & 0xffff;
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@ -1994,7 +1990,7 @@ WRITE16_MEMBER(namcos22_state::namcos22_dspram16_w)
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m_polygonram[offset] = (hi << 16) | lo;
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}
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WRITE16_MEMBER(namcos22_state::namcos22_dspram16_bank_w)
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void namcos22_state::namcos22_dspram16_bank_w(offs_t offset, u16 data, u16 mem_mask)
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{
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COMBINE_DATA(&m_dspram_bank);
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}
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@ -2034,29 +2030,29 @@ s32 namcos22_state::pointram_read(offs_t offs) // called from point_read
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}
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WRITE16_MEMBER(namcos22_state::point_address_w)
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void namcos22_state::point_address_w(u16 data)
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{
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m_point_address <<= 16;
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m_point_address |= data;
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}
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WRITE16_MEMBER(namcos22_state::point_loword_iw)
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void namcos22_state::point_loword_iw(u16 data)
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{
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m_point_data |= data;
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point_write(m_point_address++, m_point_data);
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}
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WRITE16_MEMBER(namcos22_state::point_hiword_w)
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void namcos22_state::point_hiword_w(u16 data)
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{
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m_point_data = data << 16;
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}
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READ16_MEMBER(namcos22_state::point_loword_r)
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u16 namcos22_state::point_loword_r()
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{
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return point_read(m_point_address) & 0xffff;
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}
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READ16_MEMBER(namcos22_state::point_hiword_ir)
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u16 namcos22_state::point_hiword_ir()
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{
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// high bit is unknown busy signal (ridgerac, ridgera2, raveracw, cybrcomm)
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return 0x8000 | (point_read(m_point_address++) >> 16 & 0x00ff);
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@ -2068,7 +2064,7 @@ u16 namcos22_state::pdp_status_r()
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return m_dsp_master_bioz;
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}
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READ16_MEMBER(namcos22_state::pdp_begin_r)
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u16 namcos22_state::pdp_begin_r()
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{
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if (machine().side_effects_disabled())
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return 0;
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@ -2675,14 +2671,14 @@ void namcos22s_state::mcu_port4_w(u8 data)
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if (~m_mcu_iocontrol & data & 0x20)
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{
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for (int i = 0; i < 8; i++)
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m_mcuout[i] = BIT(m_mcu_outdata, i);
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m_mcu_out[i] = BIT(m_mcu_outdata, i);
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machine().bookkeeping().coin_counter_w(0, m_mcu_outdata & 1);
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}
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if (~m_mcu_iocontrol & data & 0x40)
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{
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for (int i = 0; i < 8; i++)
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m_mcuout[8+i] = BIT(m_mcu_outdata, i);
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m_mcu_out[8+i] = BIT(m_mcu_outdata, i);
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}
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m_mcu_iocontrol = data;
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@ -2980,24 +2976,25 @@ static INPUT_PORTS_START( ridgera )
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PORT_BIT( 0xff, 0x00, IPT_PEDAL2 ) PORT_MINMAX(0x00, 0xc0) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_NAME("Brake Pedal")
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PORT_START("DSW")
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PORT_DIPNAME( 0x0001, 0x0001, "Test Mode" ) PORT_DIPLOCATION("SW2:1")
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PORT_DIPSETTING( 0x0001, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
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PORT_DIPUNKNOWN_DIPLOC( 0x0002, 0x0002, "SW2:2" )
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PORT_DIPUNKNOWN_DIPLOC( 0x0004, 0x0004, "SW2:3" )
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PORT_DIPUNKNOWN_DIPLOC( 0x0008, 0x0008, "SW2:4" )
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PORT_DIPUNKNOWN_DIPLOC( 0x0010, 0x0010, "SW2:5" )
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PORT_DIPUNKNOWN_DIPLOC( 0x0020, 0x0020, "SW2:6" )
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PORT_DIPUNKNOWN_DIPLOC( 0x0040, 0x0040, "SW2:7" )
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PORT_DIPUNKNOWN_DIPLOC( 0x0080, 0x0080, "SW2:8" )
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PORT_DIPUNKNOWN_DIPLOC( 0x0100, 0x0100, "SW3:1" )
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PORT_DIPUNKNOWN_DIPLOC( 0x0200, 0x0200, "SW3:2" )
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PORT_DIPUNKNOWN_DIPLOC( 0x0400, 0x0400, "SW3:3" )
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PORT_DIPUNKNOWN_DIPLOC( 0x0800, 0x0800, "SW3:4" )
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PORT_DIPUNKNOWN_DIPLOC( 0x1000, 0x1000, "SW3:5" )
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PORT_DIPUNKNOWN_DIPLOC( 0x2000, 0x2000, "SW3:6" )
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PORT_DIPUNKNOWN_DIPLOC( 0x4000, 0x4000, "SW3:7" )
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PORT_DIPUNKNOWN_DIPLOC( 0x8000, 0x8000, "SW3:8" )
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PORT_DIPNAME( 0x00010000, 0x00010000, "Test Mode" ) PORT_DIPLOCATION("SW2:1")
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PORT_DIPSETTING( 0x00010000, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
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PORT_DIPUNKNOWN_DIPLOC( 0x00020000, 0x00020000, "SW2:2" )
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PORT_DIPUNKNOWN_DIPLOC( 0x00040000, 0x00040000, "SW2:3" )
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PORT_DIPUNKNOWN_DIPLOC( 0x00080000, 0x00080000, "SW2:4" )
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PORT_DIPUNKNOWN_DIPLOC( 0x00100000, 0x00100000, "SW2:5" )
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PORT_DIPUNKNOWN_DIPLOC( 0x00200000, 0x00200000, "SW2:6" )
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PORT_DIPUNKNOWN_DIPLOC( 0x00400000, 0x00400000, "SW2:7" )
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PORT_DIPUNKNOWN_DIPLOC( 0x00800000, 0x00800000, "SW2:8" )
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PORT_DIPUNKNOWN_DIPLOC( 0x01000000, 0x01000000, "SW3:1" )
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PORT_DIPUNKNOWN_DIPLOC( 0x02000000, 0x02000000, "SW3:2" )
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PORT_DIPUNKNOWN_DIPLOC( 0x04000000, 0x04000000, "SW3:3" )
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PORT_DIPUNKNOWN_DIPLOC( 0x08000000, 0x08000000, "SW3:4" )
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PORT_DIPUNKNOWN_DIPLOC( 0x10000000, 0x10000000, "SW3:5" )
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PORT_DIPUNKNOWN_DIPLOC( 0x20000000, 0x20000000, "SW3:6" )
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PORT_DIPUNKNOWN_DIPLOC( 0x40000000, 0x40000000, "SW3:7" )
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PORT_DIPUNKNOWN_DIPLOC( 0x80000000, 0x80000000, "SW3:8" )
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PORT_BIT( 0x0000ffff, IP_ACTIVE_LOW, IPT_UNUSED )
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INPUT_PORTS_END
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static INPUT_PORTS_START( ridgeracf )
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@ -3012,13 +3009,13 @@ static INPUT_PORTS_START( ridgeracf )
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// DIP3-1 to DIP3-3 are for setting up the viewing angle (game used one board per screen?)
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// Some of the other dipswitches are for debugging, like with Ridge Racer 2.
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PORT_MODIFY("DSW")
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PORT_DIPUNKNOWN_DIPLOC( 0x0001, 0x0001, "SW2:1" )
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PORT_DIPNAME( 0x0002, 0x0000, "Unknown" ) PORT_DIPLOCATION("SW2:2") // always on?
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PORT_DIPSETTING( 0x0002, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
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PORT_DIPNAME( 0x8000, 0x8000, "Test Mode 2" ) PORT_DIPLOCATION("SW3:8")
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PORT_DIPSETTING( 0x8000, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
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PORT_DIPUNKNOWN_DIPLOC( 0x00010000, 0x00010000, "SW2:1" )
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PORT_DIPNAME( 0x00020000, 0x00000000, "Unknown" ) PORT_DIPLOCATION("SW2:2") // always on?
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PORT_DIPSETTING( 0x00020000, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
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PORT_DIPNAME( 0x80000000, 0x80000000, "Test Mode 2" ) PORT_DIPLOCATION("SW3:8")
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PORT_DIPSETTING( 0x80000000, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
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INPUT_PORTS_END
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static INPUT_PORTS_START( ridgera2 )
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@ -3039,9 +3036,9 @@ static INPUT_PORTS_START( ridgera2 )
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3-7 : debug polygons
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*/
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PORT_MODIFY("DSW")
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PORT_DIPNAME( 0x8000, 0x8000, "Test Mode 2" ) PORT_DIPLOCATION("SW3:8")
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PORT_DIPSETTING( 0x8000, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
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PORT_DIPNAME( 0x80000000, 0x80000000, "Test Mode 2" ) PORT_DIPLOCATION("SW3:8")
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PORT_DIPSETTING( 0x80000000, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
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INPUT_PORTS_END
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static INPUT_PORTS_START( raveracw )
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@ -3092,22 +3089,23 @@ static INPUT_PORTS_START( cybrcomm )
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PORT_BIT( 0xff, 0x7f, IPT_AD_STICK_X ) PORT_MINMAX(0x47, 0xb7) PORT_CODE_DEC(KEYCODE_S) PORT_CODE_INC(KEYCODE_F) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_PLAYER(1)
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PORT_START("DSW")
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PORT_DIPUNKNOWN_DIPLOC( 0x0001, 0x0001, "SW2:1" )
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PORT_DIPUNKNOWN_DIPLOC( 0x0002, 0x0002, "SW2:2" )
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PORT_DIPUNKNOWN_DIPLOC( 0x0004, 0x0004, "SW2:3" )
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PORT_DIPUNKNOWN_DIPLOC( 0x0008, 0x0008, "SW2:4" )
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PORT_DIPUNKNOWN_DIPLOC( 0x0010, 0x0010, "SW2:5" )
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PORT_DIPUNKNOWN_DIPLOC( 0x0020, 0x0020, "SW2:6" )
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PORT_DIPUNKNOWN_DIPLOC( 0x0040, 0x0040, "SW2:7" )
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PORT_DIPUNKNOWN_DIPLOC( 0x0080, 0x0080, "SW2:8" )
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PORT_DIPUNKNOWN_DIPLOC( 0x0100, 0x0100, "SW3:1" )
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PORT_DIPUNKNOWN_DIPLOC( 0x0200, 0x0200, "SW3:2" )
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PORT_DIPUNKNOWN_DIPLOC( 0x0400, 0x0400, "SW3:3" )
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PORT_DIPUNKNOWN_DIPLOC( 0x0800, 0x0800, "SW3:4" )
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PORT_DIPUNKNOWN_DIPLOC( 0x1000, 0x1000, "SW3:5" )
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PORT_DIPUNKNOWN_DIPLOC( 0x2000, 0x2000, "SW3:6" )
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PORT_DIPUNKNOWN_DIPLOC( 0x4000, 0x4000, "SW3:7" )
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PORT_DIPUNKNOWN_DIPLOC( 0x8000, 0x8000, "SW3:8" )
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PORT_DIPUNKNOWN_DIPLOC( 0x00010000, 0x00010000, "SW2:1" )
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PORT_DIPUNKNOWN_DIPLOC( 0x00020000, 0x00020000, "SW2:2" )
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PORT_DIPUNKNOWN_DIPLOC( 0x00040000, 0x00040000, "SW2:3" )
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PORT_DIPUNKNOWN_DIPLOC( 0x00080000, 0x00080000, "SW2:4" )
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PORT_DIPUNKNOWN_DIPLOC( 0x00100000, 0x00100000, "SW2:5" )
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PORT_DIPUNKNOWN_DIPLOC( 0x00200000, 0x00200000, "SW2:6" )
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PORT_DIPUNKNOWN_DIPLOC( 0x00400000, 0x00400000, "SW2:7" )
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PORT_DIPUNKNOWN_DIPLOC( 0x00800000, 0x00800000, "SW2:8" )
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PORT_DIPUNKNOWN_DIPLOC( 0x01000000, 0x01000000, "SW3:1" )
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PORT_DIPUNKNOWN_DIPLOC( 0x02000000, 0x02000000, "SW3:2" )
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PORT_DIPUNKNOWN_DIPLOC( 0x04000000, 0x04000000, "SW3:3" )
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PORT_DIPUNKNOWN_DIPLOC( 0x08000000, 0x08000000, "SW3:4" )
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PORT_DIPUNKNOWN_DIPLOC( 0x10000000, 0x10000000, "SW3:5" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x20000000, 0x20000000, "SW3:6" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x40000000, 0x40000000, "SW3:7" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x80000000, 0x80000000, "SW3:8" )
|
||||
PORT_BIT( 0x0000ffff, IP_ACTIVE_LOW, IPT_UNUSED )
|
||||
INPUT_PORTS_END
|
||||
|
||||
static INPUT_PORTS_START( acedrvr )
|
||||
@ -3139,26 +3137,27 @@ static INPUT_PORTS_START( acedrvr )
|
||||
PORT_BIT( 0xff, 0x00, IPT_PEDAL2 ) PORT_MINMAX(0x00, 0x48) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_NAME("Brake Pedal")
|
||||
|
||||
PORT_START("DSW")
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x0001, 0x0001, "SW2:1" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x0002, 0x0002, "SW2:2" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x0004, 0x0004, "SW2:3" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x0008, 0x0008, "SW2:4" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x0010, 0x0010, "SW2:5" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x0020, 0x0020, "SW2:6" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x0040, 0x0040, "SW2:7" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x0080, 0x0080, "SW2:8" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x0100, 0x0100, "SW3:1" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x0200, 0x0200, "SW3:2" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x0400, 0x0400, "SW3:3" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x0800, 0x0800, "SW3:4" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x1000, 0x1000, "SW3:5" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x2000, 0x2000, "SW3:6" )
|
||||
PORT_DIPNAME( 0x4000, 0x4000, "Test Mode?" ) PORT_DIPLOCATION("SW3:7")
|
||||
PORT_DIPSETTING( 0x4000, DEF_STR( Off ) )
|
||||
PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
|
||||
PORT_DIPNAME( 0x8000, 0x8000, "Test Mode?" ) PORT_DIPLOCATION("SW3:8") // enter test mode if SW3:7 is on
|
||||
PORT_DIPSETTING( 0x8000, DEF_STR( Off ) )
|
||||
PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x00010000, 0x00010000, "SW2:1" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x00020000, 0x00020000, "SW2:2" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x00040000, 0x00040000, "SW2:3" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x00080000, 0x00080000, "SW2:4" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x00100000, 0x00100000, "SW2:5" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x00200000, 0x00200000, "SW2:6" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x00400000, 0x00400000, "SW2:7" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x00800000, 0x00800000, "SW2:8" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x01000000, 0x01000000, "SW3:1" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x02000000, 0x02000000, "SW3:2" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x04000000, 0x04000000, "SW3:3" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x08000000, 0x08000000, "SW3:4" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x10000000, 0x10000000, "SW3:5" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x20000000, 0x20000000, "SW3:6" )
|
||||
PORT_DIPNAME( 0x40000000, 0x40000000, "Test Mode?" ) PORT_DIPLOCATION("SW3:7")
|
||||
PORT_DIPSETTING( 0x40000000, DEF_STR( Off ) )
|
||||
PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
|
||||
PORT_DIPNAME( 0x80000000, 0x80000000, "Test Mode?" ) PORT_DIPLOCATION("SW3:8") // enter test mode if SW3:7 is on
|
||||
PORT_DIPSETTING( 0x80000000, DEF_STR( Off ) )
|
||||
PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
|
||||
PORT_BIT( 0x0000ffff, IP_ACTIVE_LOW, IPT_UNUSED )
|
||||
|
||||
PORT_START("DEV")
|
||||
PORT_CONFNAME( 0x01, 0x00, "Enable Dev Inputs" )
|
||||
@ -3224,15 +3223,15 @@ static INPUT_PORTS_START( alpiner )
|
||||
PORT_BIT( 0x3ff, 0x200, IPT_AD_STICK_X ) PORT_MINMAX(0x080, 0x380) PORT_SENSITIVITY(100) PORT_KEYDELTA(16) PORT_PLAYER(2) PORT_NAME("Steps Edge")
|
||||
|
||||
PORT_START("DSW")
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x0001, 0x0001, "SW4:1" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x0002, 0x0002, "SW4:2" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x0004, 0x0004, "SW4:3" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x0008, 0x0008, "SW4:4" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x0010, 0x0010, "SW4:5" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x0020, 0x0020, "SW4:6" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x0040, 0x0040, "SW4:7" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x0080, 0x0080, "SW4:8" )
|
||||
PORT_BIT( 0xff00, IP_ACTIVE_LOW, IPT_UNUSED )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x00010000, 0x00010000, "SW4:1" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x00020000, 0x00020000, "SW4:2" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x00040000, 0x00040000, "SW4:3" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x00080000, 0x00080000, "SW4:4" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x00100000, 0x00100000, "SW4:5" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x00200000, 0x00200000, "SW4:6" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x00400000, 0x00400000, "SW4:7" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x00800000, 0x00800000, "SW4:8" )
|
||||
PORT_BIT( 0xff00ffff, IP_ACTIVE_LOW, IPT_UNUSED )
|
||||
INPUT_PORTS_END
|
||||
|
||||
static INPUT_PORTS_START( airco22 )
|
||||
@ -3257,15 +3256,15 @@ static INPUT_PORTS_START( airco22 )
|
||||
PORT_BIT( 0x3ff, 0x200, IPT_AD_STICK_Z ) PORT_MINMAX(0x100, 0x300) PORT_SENSITIVITY(100) PORT_KEYDELTA(12) PORT_NAME("Throttle Stick")
|
||||
|
||||
PORT_START("DSW")
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x0001, 0x0001, "SW4:1" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x0002, 0x0002, "SW4:2" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x0004, 0x0004, "SW4:3" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x0008, 0x0008, "SW4:4" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x0010, 0x0010, "SW4:5" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x0020, 0x0020, "SW4:6" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x0040, 0x0040, "SW4:7" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x0080, 0x0080, "SW4:8" )
|
||||
PORT_BIT( 0xff00, IP_ACTIVE_LOW, IPT_UNUSED )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x00010000, 0x00010000, "SW4:1" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x00020000, 0x00020000, "SW4:2" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x00040000, 0x00040000, "SW4:3" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x00080000, 0x00080000, "SW4:4" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x00100000, 0x00100000, "SW4:5" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x00200000, 0x00200000, "SW4:6" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x00400000, 0x00400000, "SW4:7" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x00800000, 0x00800000, "SW4:8" )
|
||||
PORT_BIT( 0xff00ffff, IP_ACTIVE_LOW, IPT_UNUSED )
|
||||
INPUT_PORTS_END
|
||||
|
||||
static INPUT_PORTS_START( cybrcycc )
|
||||
@ -3290,17 +3289,17 @@ static INPUT_PORTS_START( cybrcycc )
|
||||
PORT_BIT( 0x3ff, 0x000, IPT_PEDAL2 ) PORT_MINMAX(0x000, 0x100) PORT_SENSITIVITY(100) PORT_KEYDELTA(40) PORT_NAME("Brake Pedal")
|
||||
|
||||
PORT_START("DSW")
|
||||
PORT_DIPNAME( 0x0001, 0x0001, "Test Mode" ) PORT_DIPLOCATION("SW4:1")
|
||||
PORT_DIPSETTING( 0x0001, DEF_STR( Off ) )
|
||||
PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x0002, 0x0002, "SW4:2" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x0004, 0x0004, "SW4:3" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x0008, 0x0008, "SW4:4" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x0010, 0x0010, "SW4:5" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x0020, 0x0020, "SW4:6" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x0040, 0x0040, "SW4:7" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x0080, 0x0080, "SW4:8" )
|
||||
PORT_BIT( 0xff00, IP_ACTIVE_LOW, IPT_UNUSED )
|
||||
PORT_DIPNAME( 0x00010000, 0x00010000, "Test Mode" ) PORT_DIPLOCATION("SW4:1")
|
||||
PORT_DIPSETTING( 0x00010000, DEF_STR( Off ) )
|
||||
PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x00020000, 0x00020000, "SW4:2" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x00040000, 0x00040000, "SW4:3" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x00080000, 0x00080000, "SW4:4" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x00100000, 0x00100000, "SW4:5" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x00200000, 0x00200000, "SW4:6" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x00400000, 0x00400000, "SW4:7" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x00800000, 0x00800000, "SW4:8" )
|
||||
PORT_BIT( 0xff00ffff, IP_ACTIVE_LOW, IPT_UNUSED )
|
||||
INPUT_PORTS_END
|
||||
|
||||
static INPUT_PORTS_START( dirtdash )
|
||||
@ -3329,15 +3328,15 @@ static INPUT_PORTS_START( dirtdash )
|
||||
PORT_BIT( 0x3ff, 0x000, IPT_PEDAL2 ) PORT_MINMAX(0x000, 0x100) PORT_SENSITIVITY(100) PORT_KEYDELTA(40) PORT_NAME("Brake Pedal")
|
||||
|
||||
PORT_START("DSW")
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x0001, 0x0001, "SW4:1" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x0002, 0x0002, "SW4:2" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x0004, 0x0004, "SW4:3" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x0008, 0x0008, "SW4:4" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x0010, 0x0010, "SW4:5" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x0020, 0x0020, "SW4:6" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x0040, 0x0040, "SW4:7" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x0080, 0x0080, "SW4:8" )
|
||||
PORT_BIT( 0xff00, IP_ACTIVE_LOW, IPT_UNUSED )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x00010000, 0x00010000, "SW4:1" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x00020000, 0x00020000, "SW4:2" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x00040000, 0x00040000, "SW4:3" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x00080000, 0x00080000, "SW4:4" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x00100000, 0x00100000, "SW4:5" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x00200000, 0x00200000, "SW4:6" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x00400000, 0x00400000, "SW4:7" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x00800000, 0x00800000, "SW4:8" )
|
||||
PORT_BIT( 0xff00ffff, IP_ACTIVE_LOW, IPT_UNUSED )
|
||||
INPUT_PORTS_END
|
||||
|
||||
static INPUT_PORTS_START( tokyowar )
|
||||
@ -3364,17 +3363,17 @@ static INPUT_PORTS_START( tokyowar )
|
||||
PORT_BIT( 0x3ff, 0x000, IPT_PEDAL2 ) PORT_MINMAX(0x000, 0x100) PORT_SENSITIVITY(100) PORT_KEYDELTA(20) PORT_NAME("Brake Pedal")
|
||||
|
||||
PORT_START("DSW")
|
||||
PORT_DIPNAME( 0x0001, 0x0001, "Test Mode" ) PORT_DIPLOCATION("SW4:1")
|
||||
PORT_DIPSETTING( 0x0001, DEF_STR( Off ) )
|
||||
PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x0002, 0x0002, "SW4:2" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x0004, 0x0004, "SW4:3" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x0008, 0x0008, "SW4:4" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x0010, 0x0010, "SW4:5" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x0020, 0x0020, "SW4:6" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x0040, 0x0040, "SW4:7" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x0080, 0x0080, "SW4:8" )
|
||||
PORT_BIT( 0xff00, IP_ACTIVE_LOW, IPT_UNUSED )
|
||||
PORT_DIPNAME( 0x00010000, 0x00010000, "Test Mode" ) PORT_DIPLOCATION("SW4:1")
|
||||
PORT_DIPSETTING( 0x00010000, DEF_STR( Off ) )
|
||||
PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x00020000, 0x00020000, "SW4:2" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x00040000, 0x00040000, "SW4:3" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x00080000, 0x00080000, "SW4:4" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x00100000, 0x00100000, "SW4:5" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x00200000, 0x00200000, "SW4:6" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x00400000, 0x00400000, "SW4:7" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x00800000, 0x00800000, "SW4:8" )
|
||||
PORT_BIT( 0xff00ffff, IP_ACTIVE_LOW, IPT_UNUSED )
|
||||
INPUT_PORTS_END
|
||||
|
||||
static INPUT_PORTS_START( aquajet )
|
||||
@ -3399,17 +3398,17 @@ static INPUT_PORTS_START( aquajet )
|
||||
PORT_BIT( 0x3ff, 0x1fc, IPT_AD_STICK_Y ) PORT_MINMAX(0x000, 0x3f8) PORT_SENSITIVITY(100) PORT_KEYDELTA(40) PORT_REVERSE
|
||||
|
||||
PORT_START("DSW")
|
||||
PORT_DIPNAME( 0x0001, 0x0001, "Test Mode" ) PORT_DIPLOCATION("SW4:1")
|
||||
PORT_DIPSETTING( 0x0001, DEF_STR( Off ) )
|
||||
PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x0002, 0x0002, "SW4:2" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x0004, 0x0004, "SW4:3" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x0008, 0x0008, "SW4:4" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x0010, 0x0010, "SW4:5" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x0020, 0x0020, "SW4:6" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x0040, 0x0040, "SW4:7" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x0080, 0x0080, "SW4:8" )
|
||||
PORT_BIT( 0xff00, IP_ACTIVE_LOW, IPT_UNUSED )
|
||||
PORT_DIPNAME( 0x00010000, 0x00010000, "Test Mode" ) PORT_DIPLOCATION("SW4:1")
|
||||
PORT_DIPSETTING( 0x00010000, DEF_STR( Off ) )
|
||||
PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x00020000, 0x00020000, "SW4:2" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x00040000, 0x00040000, "SW4:3" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x00080000, 0x00080000, "SW4:4" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x00100000, 0x00100000, "SW4:5" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x00200000, 0x00200000, "SW4:6" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x00400000, 0x00400000, "SW4:7" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x00800000, 0x00800000, "SW4:8" )
|
||||
PORT_BIT( 0xff00ffff, IP_ACTIVE_LOW, IPT_UNUSED )
|
||||
INPUT_PORTS_END
|
||||
|
||||
static INPUT_PORTS_START( adillor )
|
||||
@ -3432,17 +3431,17 @@ static INPUT_PORTS_START( adillor )
|
||||
PORT_BIT( 0xff, 0x80, IPT_AD_STICK_Y ) PORT_MINMAX(0x01, 0xff) PORT_SENSITIVITY(100) PORT_KEYDELTA(8) PORT_NAME("Trackball Y") PORT_REVERSE
|
||||
|
||||
PORT_START("DSW")
|
||||
PORT_DIPNAME( 0x0001, 0x0001, "Test Mode" ) PORT_DIPLOCATION("SW4:1")
|
||||
PORT_DIPSETTING( 0x0001, DEF_STR( Off ) )
|
||||
PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x0002, 0x0002, "SW4:2" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x0004, 0x0004, "SW4:3" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x0008, 0x0008, "SW4:4" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x0010, 0x0010, "SW4:5" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x0020, 0x0020, "SW4:6" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x0040, 0x0040, "SW4:7" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x0080, 0x0080, "SW4:8" )
|
||||
PORT_BIT( 0xff00, IP_ACTIVE_LOW, IPT_UNUSED )
|
||||
PORT_DIPNAME( 0x00010000, 0x00010000, "Test Mode" ) PORT_DIPLOCATION("SW4:1")
|
||||
PORT_DIPSETTING( 0x00010000, DEF_STR( Off ) )
|
||||
PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x00020000, 0x00020000, "SW4:2" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x00040000, 0x00040000, "SW4:3" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x00080000, 0x00080000, "SW4:4" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x00100000, 0x00100000, "SW4:5" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x00200000, 0x00200000, "SW4:6" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x00400000, 0x00400000, "SW4:7" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x00800000, 0x00800000, "SW4:8" )
|
||||
PORT_BIT( 0xff00ffff, IP_ACTIVE_LOW, IPT_UNUSED )
|
||||
|
||||
PORT_START("DEV")
|
||||
PORT_CONFNAME( 0x01, 0x00, "Enable Dev Inputs" )
|
||||
@ -3483,15 +3482,15 @@ static INPUT_PORTS_START( propcycl )
|
||||
PORT_BIT( 0xff, 0x80, IPT_AD_STICK_Z ) PORT_MINMAX(0x01, 0xff) PORT_SENSITIVITY(100) PORT_KEYDELTA(10) PORT_NAME("Cycle Pedal")
|
||||
|
||||
PORT_START("DSW")
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x0001, 0x0001, "SW4:1" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x0002, 0x0002, "SW4:2" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x0004, 0x0004, "SW4:3" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x0008, 0x0008, "SW4:4" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x0010, 0x0010, "SW4:5" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x0020, 0x0020, "SW4:6" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x0040, 0x0040, "SW4:7" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x0080, 0x0080, "SW4:8" )
|
||||
PORT_BIT( 0xff00, IP_ACTIVE_LOW, IPT_UNUSED )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x00010000, 0x00010000, "SW4:1" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x00020000, 0x00020000, "SW4:2" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x00040000, 0x00040000, "SW4:3" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x00080000, 0x00080000, "SW4:4" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x00100000, 0x00100000, "SW4:5" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x00200000, 0x00200000, "SW4:6" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x00400000, 0x00400000, "SW4:7" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x00800000, 0x00800000, "SW4:8" )
|
||||
PORT_BIT( 0xff00ffff, IP_ACTIVE_LOW, IPT_UNUSED )
|
||||
INPUT_PORTS_END
|
||||
|
||||
static INPUT_PORTS_START( timecris )
|
||||
@ -3513,17 +3512,17 @@ static INPUT_PORTS_START( timecris )
|
||||
PORT_BIT( 0xffff, 43+241/2, IPT_LIGHTGUN_Y ) PORT_CROSSHAIR(Y, 1.0, 0.0, 0) PORT_MINMAX(43, 43+241) PORT_SENSITIVITY(64) PORT_KEYDELTA(4)
|
||||
|
||||
PORT_START("DSW")
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x0001, 0x0001, "SW4:1" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x0002, 0x0002, "SW4:2" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x0004, 0x0004, "SW4:3" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x0008, 0x0008, "SW4:4" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x0010, 0x0010, "SW4:5" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x0020, 0x0020, "SW4:6" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x0040, 0x0040, "SW4:7" )
|
||||
PORT_DIPNAME( 0x0080, 0x0080, "Test Mode" ) PORT_DIPLOCATION("SW4:8")
|
||||
PORT_DIPSETTING( 0x0080, DEF_STR( Off ) )
|
||||
PORT_DIPSETTING( 0x0000, DEF_STR( On ) )
|
||||
PORT_BIT( 0xff00, IP_ACTIVE_LOW, IPT_UNUSED )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x00010000, 0x00010000, "SW4:1" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x00020000, 0x00020000, "SW4:2" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x00040000, 0x00040000, "SW4:3" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x00080000, 0x00080000, "SW4:4" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x00100000, 0x00100000, "SW4:5" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x00200000, 0x00200000, "SW4:6" )
|
||||
PORT_DIPUNKNOWN_DIPLOC( 0x00400000, 0x00400000, "SW4:7" )
|
||||
PORT_DIPNAME( 0x00800000, 0x00800000, "Test Mode" ) PORT_DIPLOCATION("SW4:8")
|
||||
PORT_DIPSETTING( 0x00800000, DEF_STR( Off ) )
|
||||
PORT_DIPSETTING( 0x00000000, DEF_STR( On ) )
|
||||
PORT_BIT( 0xff00ffff, IP_ACTIVE_LOW, IPT_UNUSED )
|
||||
INPUT_PORTS_END
|
||||
|
||||
|
||||
@ -3620,11 +3619,12 @@ ALLOW_SAVE_TYPE(namcos22_dsp_upload_state);
|
||||
|
||||
void namcos22_state::machine_start()
|
||||
{
|
||||
m_mcuout.resolve();
|
||||
m_cpuled.resolve();
|
||||
m_mcu_out.resolve();
|
||||
m_cpuled_out.resolve();
|
||||
m_portbits[0] = 0xffff;
|
||||
m_portbits[1] = 0xffff;
|
||||
|
||||
m_cpuled_data = 0;
|
||||
m_keycus_rng = 0;
|
||||
m_su_82 = 0;
|
||||
m_irq_state = 0;
|
||||
@ -3665,6 +3665,7 @@ void namcos22_state::machine_start()
|
||||
save_item(NAME(m_irq_enabled));
|
||||
save_item(NAME(m_dsp_upload_state));
|
||||
save_item(NAME(m_UploadDestIdx));
|
||||
save_item(NAME(m_cpuled_data));
|
||||
save_item(NAME(m_su_82));
|
||||
save_item(NAME(m_keycus_id));
|
||||
save_item(NAME(m_keycus_rng));
|
||||
|
||||
@ -213,12 +213,11 @@ public:
|
||||
m_vics_control(*this, "vics_control"),
|
||||
m_screen(*this, "screen"),
|
||||
m_adc_ports(*this, "ADC.%u", 0),
|
||||
m_dsw(*this, "DSW"),
|
||||
m_inputs(*this, "INPUTS"),
|
||||
m_custom(*this, "CUSTOM.%u", 0),
|
||||
m_opt(*this, "OPT.%u", 0),
|
||||
m_mcuout(*this, "mcuout%u", 0U),
|
||||
m_cpuled(*this, "cpuled%u", 0U)
|
||||
m_mcu_out(*this, "mcuout%u", 0U),
|
||||
m_cpuled_out(*this, "cpuled%u", 0U)
|
||||
{ }
|
||||
|
||||
void cybrcomm(machine_config &config);
|
||||
@ -268,27 +267,26 @@ protected:
|
||||
virtual void video_start() override;
|
||||
virtual void device_post_load() override;
|
||||
|
||||
//private:
|
||||
DECLARE_WRITE32_MEMBER(namcos22_textram_w);
|
||||
DECLARE_READ16_MEMBER(namcos22_tilemapattr_r);
|
||||
DECLARE_WRITE16_MEMBER(namcos22_tilemapattr_w);
|
||||
DECLARE_READ32_MEMBER(namcos22_dspram_r);
|
||||
DECLARE_WRITE32_MEMBER(namcos22_dspram_w);
|
||||
DECLARE_WRITE32_MEMBER(namcos22_cgram_w);
|
||||
DECLARE_WRITE32_MEMBER(namcos22_paletteram_w);
|
||||
DECLARE_WRITE16_MEMBER(namcos22_dspram16_bank_w);
|
||||
DECLARE_READ16_MEMBER(namcos22_dspram16_r);
|
||||
DECLARE_WRITE16_MEMBER(namcos22_dspram16_w);
|
||||
void namcos22_textram_w(offs_t offset, u32 data, u32 mem_mask);
|
||||
u16 namcos22_tilemapattr_r(offs_t offset);
|
||||
void namcos22_tilemapattr_w(offs_t offset, u16 data, u16 mem_mask);
|
||||
u32 namcos22_dspram_r(offs_t offset);
|
||||
void namcos22_dspram_w(offs_t offset, u32 data, u32 mem_mask);
|
||||
void namcos22_cgram_w(offs_t offset, u32 data, u32 mem_mask);
|
||||
void namcos22_paletteram_w(offs_t offset, u32 data, u32 mem_mask);
|
||||
void namcos22_dspram16_bank_w(offs_t offset, u16 data, u16 mem_mask);
|
||||
u16 namcos22_dspram16_r(offs_t offset);
|
||||
void namcos22_dspram16_w(offs_t offset, u16 data, u16 mem_mask);
|
||||
u16 pdp_status_r();
|
||||
DECLARE_READ16_MEMBER(pdp_begin_r);
|
||||
u16 pdp_begin_r();
|
||||
u16 dsp_hold_signal_r();
|
||||
void dsp_hold_ack_w(u16 data);
|
||||
void dsp_xf_output_w(u16 data);
|
||||
DECLARE_WRITE16_MEMBER(point_address_w);
|
||||
DECLARE_WRITE16_MEMBER(point_loword_iw);
|
||||
DECLARE_WRITE16_MEMBER(point_hiword_w);
|
||||
DECLARE_READ16_MEMBER(point_loword_r);
|
||||
DECLARE_READ16_MEMBER(point_hiword_ir);
|
||||
void point_address_w(u16 data);
|
||||
void point_loword_iw(u16 data);
|
||||
void point_hiword_w(u16 data);
|
||||
u16 point_loword_r();
|
||||
u16 point_hiword_ir();
|
||||
DECLARE_WRITE16_MEMBER(dsp_unk2_w);
|
||||
DECLARE_READ16_MEMBER(dsp_unk_port3_r);
|
||||
DECLARE_WRITE16_MEMBER(upload_code_to_slave_dsp_w);
|
||||
@ -312,14 +310,13 @@ protected:
|
||||
DECLARE_WRITE16_MEMBER(dsp_slave_portb_w);
|
||||
DECLARE_READ32_MEMBER(namcos22_sci_r);
|
||||
DECLARE_WRITE32_MEMBER(namcos22_sci_w);
|
||||
DECLARE_READ16_MEMBER(namcos22_shared_r);
|
||||
DECLARE_WRITE16_MEMBER(namcos22_shared_w);
|
||||
DECLARE_READ16_MEMBER(namcos22_keycus_r);
|
||||
DECLARE_WRITE16_MEMBER(namcos22_keycus_w);
|
||||
u16 namcos22_shared_r(offs_t offset);
|
||||
void namcos22_shared_w(offs_t offset, u16 data, u16 mem_mask);
|
||||
u16 namcos22_keycus_r(offs_t offset);
|
||||
void namcos22_keycus_w(offs_t offset, u16 data, u16 mem_mask);
|
||||
DECLARE_READ16_MEMBER(namcos22_portbit_r);
|
||||
DECLARE_WRITE16_MEMBER(namcos22_portbit_w);
|
||||
DECLARE_READ16_MEMBER(namcos22_dipswitch_r);
|
||||
DECLARE_WRITE16_MEMBER(namcos22_cpuleds_w);
|
||||
void namcos22_cpuleds_w(offs_t offset, u32 data, u32 mem_mask);
|
||||
u8 mcu_port4_s22_r();
|
||||
u8 iomcu_port4_s22_r();
|
||||
DECLARE_READ16_MEMBER(mcuc74_speedup_r);
|
||||
@ -350,9 +347,9 @@ protected:
|
||||
void syscon_irqack(offs_t offset, u8 data);
|
||||
void syscon_dspcontrol(offs_t offset, u8 data);
|
||||
void syscon_mcucontrol(offs_t offset, u8 data);
|
||||
DECLARE_READ8_MEMBER(syscon_r);
|
||||
DECLARE_WRITE8_MEMBER(ss22_syscon_w);
|
||||
DECLARE_WRITE8_MEMBER(s22_syscon_w);
|
||||
u8 syscon_r(offs_t offset);
|
||||
void ss22_syscon_w(offs_t offset, u8 data);
|
||||
void s22_syscon_w(offs_t offset, u8 data);
|
||||
|
||||
void posirq_update();
|
||||
emu_timer *m_posirq_timer;
|
||||
@ -424,12 +421,11 @@ protected:
|
||||
optional_shared_ptr<u32> m_vics_control;
|
||||
required_device<screen_device> m_screen;
|
||||
optional_ioport_array<8> m_adc_ports;
|
||||
required_ioport m_dsw;
|
||||
required_ioport m_inputs;
|
||||
optional_ioport_array<2> m_custom;
|
||||
optional_ioport_array<2> m_opt;
|
||||
output_finder<16> m_mcuout;
|
||||
output_finder<8> m_cpuled;
|
||||
output_finder<16> m_mcu_out;
|
||||
output_finder<8> m_cpuled_out;
|
||||
|
||||
u8 m_syscontrol[0x20];
|
||||
bool m_dsp_irq_enabled;
|
||||
@ -450,6 +446,7 @@ protected:
|
||||
int m_irq_enabled;
|
||||
namcos22_dsp_upload_state m_dsp_upload_state;
|
||||
int m_UploadDestIdx;
|
||||
u32 m_cpuled_data;
|
||||
u16 m_su_82;
|
||||
u16 m_keycus_id;
|
||||
u16 m_keycus_rng;
|
||||
@ -553,8 +550,8 @@ private:
|
||||
|
||||
DECLARE_WRITE16_MEMBER(namcos22s_czattr_w);
|
||||
DECLARE_READ16_MEMBER(namcos22s_czattr_r);
|
||||
DECLARE_WRITE32_MEMBER(namcos22s_czram_w);
|
||||
DECLARE_READ32_MEMBER(namcos22s_czram_r);
|
||||
void namcos22s_czram_w(offs_t offset, u32 data, u32 mem_mask);
|
||||
u32 namcos22s_czram_r(offs_t offset);
|
||||
DECLARE_READ32_MEMBER(namcos22s_vics_control_r);
|
||||
DECLARE_WRITE32_MEMBER(namcos22s_vics_control_w);
|
||||
DECLARE_READ16_MEMBER(spotram_r);
|
||||
|
||||
@ -1754,7 +1754,7 @@ TILE_GET_INFO_MEMBER(namcos22_state::get_text_tile_info)
|
||||
tileinfo.set(0, data & 0x03ff, data >> 12, TILE_FLIPYX((data & 0x0c00) >> 10));
|
||||
}
|
||||
|
||||
WRITE32_MEMBER(namcos22_state::namcos22_textram_w)
|
||||
void namcos22_state::namcos22_textram_w(offs_t offset, u32 data, u32 mem_mask)
|
||||
{
|
||||
u32 prev = m_textram[offset];
|
||||
COMBINE_DATA(&m_textram[offset]);
|
||||
@ -1765,7 +1765,7 @@ WRITE32_MEMBER(namcos22_state::namcos22_textram_w)
|
||||
}
|
||||
}
|
||||
|
||||
WRITE32_MEMBER(namcos22_state::namcos22_cgram_w)
|
||||
void namcos22_state::namcos22_cgram_w(offs_t offset, u32 data, u32 mem_mask)
|
||||
{
|
||||
u32 prev = m_cgram[offset];
|
||||
COMBINE_DATA(&m_cgram[offset]);
|
||||
@ -1805,7 +1805,7 @@ TIMER_CALLBACK_MEMBER(namcos22_state::posirq_callback)
|
||||
posirq_update();
|
||||
}
|
||||
|
||||
WRITE16_MEMBER(namcos22_state::namcos22_tilemapattr_w)
|
||||
void namcos22_state::namcos22_tilemapattr_w(offs_t offset, u16 data, u16 mem_mask)
|
||||
{
|
||||
/*
|
||||
0: R/W - x offset
|
||||
@ -1830,7 +1830,7 @@ WRITE16_MEMBER(namcos22_state::namcos22_tilemapattr_w)
|
||||
}
|
||||
}
|
||||
|
||||
READ16_MEMBER(namcos22_state::namcos22_tilemapattr_r)
|
||||
u16 namcos22_state::namcos22_tilemapattr_r(offs_t offset)
|
||||
{
|
||||
switch (offset)
|
||||
{
|
||||
@ -2092,7 +2092,7 @@ void namcos22s_state::draw_text_layer(screen_device &screen, bitmap_rgb32 &bitma
|
||||
|
||||
/*********************************************************************************************/
|
||||
|
||||
WRITE32_MEMBER(namcos22_state::namcos22_paletteram_w)
|
||||
void namcos22_state::namcos22_paletteram_w(offs_t offset, u32 data, u32 mem_mask)
|
||||
{
|
||||
u32 prev = m_paletteram[offset];
|
||||
COMBINE_DATA(&m_paletteram[offset]);
|
||||
@ -2154,7 +2154,7 @@ READ16_MEMBER(namcos22s_state::namcos22s_czattr_r)
|
||||
return m_czattr[offset];
|
||||
}
|
||||
|
||||
WRITE32_MEMBER(namcos22s_state::namcos22s_czram_w)
|
||||
void namcos22s_state::namcos22s_czram_w(offs_t offset, u32 data, u32 mem_mask)
|
||||
{
|
||||
/*
|
||||
czram contents, it's basically a big cz compare table
|
||||
@ -2181,7 +2181,7 @@ WRITE32_MEMBER(namcos22s_state::namcos22s_czram_w)
|
||||
}
|
||||
}
|
||||
|
||||
READ32_MEMBER(namcos22s_state::namcos22s_czram_r)
|
||||
u32 namcos22s_state::namcos22s_czram_r(offs_t offset)
|
||||
{
|
||||
int bank = m_czattr[5] & 3;
|
||||
return (m_banked_czram[bank][offset * 2] << 16) | m_banked_czram[bank][offset * 2 + 1];
|
||||
|
||||
Loading…
Reference in New Issue
Block a user