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Code cleanup

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This commit is contained in:
U-demo\test 2015-04-12 15:03:30 -06:00
parent 566ecdc0ea
commit c81f94ab51
4 changed files with 27 additions and 28 deletions
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8
src/emu/video/voodoo_pci.c
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@ -31,12 +31,12 @@ voodoo_pci_device::voodoo_pci_device(const machine_config &mconfig, const char *
void voodoo_pci_device::set_cpu_tag(const char *_cpu_tag)
{
cpu_tag = _cpu_tag;
m_cpu_tag = _cpu_tag;
}
void voodoo_pci_device::device_start()
{
voodoo_device::static_set_cpu_tag(m_voodoo, cpu_tag);
voodoo_device::static_set_cpu_tag(m_voodoo, m_cpu_tag);
pci_device::device_start();
add_map(32*1024*1024, M_MEM, FUNC(voodoo_pci_device::reg_map));
add_map(32*1024*1024, M_MEM, FUNC(voodoo_pci_device::lfb_map));
@ -51,7 +51,7 @@ void voodoo_pci_device::device_reset()
void voodoo_pci_device::map_extra(UINT64 memory_window_start, UINT64 memory_window_end, UINT64 memory_offset, address_space *memory_space,
UINT64 io_window_start, UINT64 io_window_end, UINT64 io_offset, address_space *io_space)
{
logerror("%s: map_extra\n", tag());
logerror("%s: map_extra\n", this->tag());
// Really awkward way of getting vga address space mapped
// Should really be dependent on voodoo VGAINIT0 bit 8 and IO base + 0xc3 bit 0
if (1) {
@ -75,7 +75,7 @@ void voodoo_pci_device::map_extra(UINT64 memory_window_start, UINT64 memory_wind
start = (start & 0xFFFF0000) + 0x300;
UINT64 end = (start & 0xFFFF0000) + 0x3ef;
space->install_device_delegate(start, end, *this, bi.map);
logerror("%s: map %s at %0*x-%0*x\n", tag(), bi.map.name(), bi.flags & M_IO ? 4 : 8, UINT32(start), bi.flags & M_IO ? 4 : 8, UINT32(end));
logerror("%s: map %s at %0*x-%0*x\n", this->tag(), bi.map.name(), bi.flags & M_IO ? 4 : 8, UINT32(start), bi.flags & M_IO ? 4 : 8, UINT32(end));
}
}

2
src/emu/video/voodoo_pci.h
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@ -27,7 +27,7 @@ protected:
private:
required_device<voodoo_banshee_device> m_voodoo;
const char *cpu_tag;
const char *m_cpu_tag;
DECLARE_ADDRESS_MAP(reg_map, 32);
DECLARE_ADDRESS_MAP(lfb_map, 32);

1
src/mame/drivers/iteagle.c
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@ -152,7 +152,6 @@ static MACHINE_CONFIG_START( gtfore, iteagle_state )
MCFG_SCREEN_VIDEO_ATTRIBUTES(VIDEO_UPDATE_BEFORE_VBLANK)
MCFG_SCREEN_REFRESH_RATE(59)
MCFG_SCREEN_SIZE(512, 384)
MCFG_SCREEN_VISIBLE_AREA(0, 511, 0, 383)
MCFG_SCREEN_UPDATE_DEVICE(":pci:09.0", voodoo_pci_device, screen_update)

44
src/mame/machine/iteagle_fpga.c
View File

@ -47,21 +47,21 @@ void iteagle_fpga_device::device_reset()
//m_rtc_regs[0] = 0x11223344;
switch ((machine().root_device().ioport("VERSION")->read()>>4)&0xF) {
case 3:
m_seq = 0x0a0b0a; // gt02o
break;
m_seq = 0x0a0b0a; // gt02
break;
case 4:
m_seq = 0x0a020b; // gt04
break;
m_seq = 0x0a020b; // gt04
break;
case 5:
m_seq = 0x0b0a0c; // gt05
break;
m_seq = 0x0b0a0c; // gt05
break;
default:
m_seq = 0x0c0b0d; // gt02
break;
}
m_seq = 0x0c0b0d; // gt06
break;
}
m_seq_rem1 = 0;
m_seq_rem2 = 0;
m_seq_rem1 = 0;
m_seq_rem2 = 0;
// 0x00&0x2 == 1 for boot
//m_fpga_regs[0x00/4] = 0xC1110002; // 0xCF000002;// byte 3 is voltage sensor? high = 0x40 good = 0xC0 0xF0 0xFF; //0x80 0x30 0x00FF = voltage low
@ -97,21 +97,21 @@ void iteagle_fpga_device::update_sequence(UINT32 data)
UINT32 val1, feed;
feed = ((m_seq<<4) ^ m_seq)>>7;
if (data & 0x1) {
val1 = ((m_seq & 0x2)<<1) | ((m_seq & 0x4)>>1) | ((m_seq & 0x8)>>3);
m_seq_rem1 = ((m_seq & 0x10)) | ((m_seq & 0x20)>>2) | ((m_seq & 0x40)>>4);
m_seq_rem2 = ((m_seq & 0x80)>>1) | ((m_seq & 0x100)>>3) | ((m_seq & 0x200)>>5);
m_seq = (m_seq>>9) | ((feed&0x1ff)<<15);
m_fpga_regs[offset] = (m_fpga_regs[offset]&0xFFFFFF00) | ((val1 + m_seq_rem1 + m_seq_rem2)&0xFF);
val1 = ((m_seq & 0x2)<<1) | ((m_seq & 0x4)>>1) | ((m_seq & 0x8)>>3);
m_seq_rem1 = ((m_seq & 0x10)) | ((m_seq & 0x20)>>2) | ((m_seq & 0x40)>>4);
m_seq_rem2 = ((m_seq & 0x80)>>1) | ((m_seq & 0x100)>>3) | ((m_seq & 0x200)>>5);
m_seq = (m_seq>>9) | ((feed&0x1ff)<<15);
m_fpga_regs[offset] = (m_fpga_regs[offset]&0xFFFFFF00) | ((val1 + m_seq_rem1 + m_seq_rem2)&0xFF);
} else if (data & 0x2) {
val1 = ((m_seq & 0x2)<<1) | ((m_seq & 0x4)>>1) | ((m_seq & 0x8)>>3);
m_seq_rem1 = ((m_seq & 0x10)) | ((m_seq & 0x20)>>2) | ((m_seq & 0x40)>>4);
m_seq = (m_seq>>6) | ((feed&0x3f)<<18);
m_fpga_regs[offset] = (m_fpga_regs[offset]&0xFFFFFF00) | ((val1 + m_seq_rem1 + m_seq_rem2)&0xFF);
val1 = ((m_seq & 0x2)<<1) | ((m_seq & 0x4)>>1) | ((m_seq & 0x8)>>3);
m_seq_rem1 = ((m_seq & 0x10)) | ((m_seq & 0x20)>>2) | ((m_seq & 0x40)>>4);
m_seq = (m_seq>>6) | ((feed&0x3f)<<18);
m_fpga_regs[offset] = (m_fpga_regs[offset]&0xFFFFFF00) | ((val1 + m_seq_rem1 + m_seq_rem2)&0xFF);
} else {
val1 = ((m_seq & 0x2)<<6) | ((m_seq & 0x4)<<4) | ((m_seq & 0x8)<<2) | ((m_seq & 0x10)<<0)
| ((m_seq & 0x20)>>2) | ((m_seq & 0x40)>>4) | ((m_seq & 0x80)>>6) | ((m_seq & 0x100)>>8);
m_seq = (m_seq>>8) | ((feed&0xff)<<16);
m_fpga_regs[offset] = (m_fpga_regs[offset]&0xFFFFFF00) | ((val1 + m_seq_rem1 + m_seq_rem2) & 0xff);
m_seq = (m_seq>>8) | ((feed&0xff)<<16);
m_fpga_regs[offset] = (m_fpga_regs[offset]&0xFFFFFF00) | ((val1 + m_seq_rem1 + m_seq_rem2) & 0xff);
}
if (0 && LOG_FPGA)
logerror("%s:fpga update_sequence In: %02X Seq: %06X Out: %02X\n", machine().describe_context(), data, m_seq, m_fpga_regs[offset]&0xff);