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pci-ide: Allow for address size resolving even in legacy mode. (nw)

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This commit is contained in:
Ted Green 2017-05-14 13:21:12 -06:00
parent e99238e88b
commit c84d7f1806
3 changed files with 31 additions and 21 deletions
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47
src/devices/machine/pci-ide.cpp
View File

@ -17,7 +17,7 @@ ide_pci_device::ide_pci_device(const machine_config &mconfig, const char *tag, d
DEVICE_ADDRESS_MAP_START(config_map, 32, ide_pci_device)
AM_RANGE(0x08, 0x0b) AM_WRITE8(prog_if_w, 0x0000ff00)
AM_RANGE(0x10, 0x1f) AM_WRITE(address_base_w)
AM_RANGE(0x10, 0x1f) AM_READWRITE(address_base_r, address_base_w)
AM_RANGE(0x40, 0x5f) AM_READWRITE(pcictrl_r, pcictrl_w)
AM_RANGE(0x70, 0x77) AM_DEVREADWRITE("ide", bus_master_ide_controller_device, bmdma_r, bmdma_w) // PCI646
AM_RANGE(0x78, 0x7f) AM_DEVREADWRITE("ide2", bus_master_ide_controller_device, bmdma_r, bmdma_w) // PCI646
@ -214,26 +214,35 @@ WRITE32_MEMBER(ide_pci_device::pcictrl_w)
}
}
READ32_MEMBER(ide_pci_device::address_base_r)
{
if (bank_reg_infos[offset].bank == -1)
return 0;
int bid = bank_reg_infos[offset].bank;
if (bank_reg_infos[offset].hi)
return bank_infos[bid].adr >> 32;
int flags = bank_infos[bid].flags;
return (pci_bar[offset] & ~(bank_infos[bid].size - 1)) | (flags & M_IO ? 1 : 0) | (flags & M_64A ? 4 : 0) | (flags & M_PREF ? 8 : 0);
}
WRITE32_MEMBER(ide_pci_device::address_base_w)
{
// data==0xffffffff is used to identify required memory space
if (data != 0xffffffff) {
// Save local copy of BAR
pci_bar[offset] = data;
// Bits 0 (primary) and 2 (secondary) control if the mapping is legacy or BAR
switch (offset) {
case 0: case 1:
if (pclass & 0x1)
pci_device::address_base_w(space, offset, data);
break;
case 2: case 3:
if (pclass & 0x4)
pci_device::address_base_w(space, offset, data);
break;
default:
// Only the first 4 bars are controlled by pif
// Save local copy of BAR
pci_bar[offset] = data;
// Bits 0 (primary) and 2 (secondary) control if the mapping is legacy or BAR
switch (offset) {
case 0: case 1:
if (pclass & 0x1)
pci_device::address_base_w(space, offset, data);
}
logerror("Mapping bar[%i] = %08x\n", offset, data);
break;
case 2: case 3:
if (pclass & 0x4)
pci_device::address_base_w(space, offset, data);
break;
default:
// Only the first 4 bars are controlled by pif
pci_device::address_base_w(space, offset, data);
}
logerror("Mapping bar[%i] = %08x\n", offset, data);
}

1
src/devices/machine/pci-ide.h
View File

@ -73,6 +73,7 @@ private:
DECLARE_WRITE8_MEMBER(prog_if_w);
DECLARE_READ32_MEMBER(pcictrl_r);
DECLARE_WRITE32_MEMBER(pcictrl_w);
DECLARE_READ32_MEMBER(address_base_r);
DECLARE_WRITE32_MEMBER(address_base_w);
};

4
src/devices/machine/vrc5074.cpp
View File

@ -388,7 +388,7 @@ void vrc5074_device::setup_pci_space()
m_pci_mask[index] = (1 << (36 - mask)) - 1;
m_pci_laddr[index] = m_cpu_regs[NREG_PCIINIT0 + index * 2] & (~m_pci_mask[index]);
m_pci_type[index] = m_cpu_regs[NREG_PCIINIT0 + index * 2] & 0xe;
if (0 && LOG_NILE)
if (1 && LOG_NILE)
logerror("setup_pci_space: mask_sel=%x pci_type=%x pci_mask[%d]=%08X pci_laddr[%d]=%08X\n",
mask, m_pci_type[index], index, m_pci_mask[index], index, m_pci_laddr[index]);
}
@ -873,7 +873,7 @@ WRITE32_MEMBER(vrc5074_device::cpu_reg_w)
break;
case NREG_PCIW0:
case NREG_PCIW1:
setup_pci_space();
map_cpu_space();
break;
case NREG_CPUSTAT + 0: /* CPU status */
case NREG_CPUSTAT + 1: /* CPU status */