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Cleanups for 0.125u3.

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This commit is contained in:
Aaron Giles 2008-05-29 09:25:51 +00:00
parent 7247ecbce2
commit c852c42952
24 changed files with 446 additions and 446 deletions
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122
src/emu/cheat.c
View File

@ -120,7 +120,7 @@ enum
DEFINE_BITFIELD_ENUM(RegionFlag, 7, 7), // 0 = cpu, 1 = non-cpu DEFINE_BITFIELD_ENUM(RegionFlag, 7, 7), // 0 = cpu, 1 = non-cpu
/* old code */ /* old code */
// DEFINE_BITFIELD_ENUM(OneShot, 0, 0), // DEFINE_BITFIELD_ENUM(OneShot, 0, 0),
DEFINE_BITFIELD_ENUM(Type, 1, 2), DEFINE_BITFIELD_ENUM(Type, 1, 2),
DEFINE_BITFIELD_ENUM(Operation, 3, 4), DEFINE_BITFIELD_ENUM(Operation, 3, 4),
DEFINE_BITFIELD_ENUM(TypeParameter, 5, 7), DEFINE_BITFIELD_ENUM(TypeParameter, 5, 7),
@ -393,7 +393,7 @@ enum // entry flags
kCheatFlag_HasWrongCode = 1 << 12, kCheatFlag_HasWrongCode = 1 << 12,
/* true if the cheat has been edited or is a new cheat /* true if the cheat has been edited or is a new cheat
checked at auto-save then save the code if true */ checked at auto-save then save the code if true */
kCheatFlag_Dirty = 1 << 13, kCheatFlag_Dirty = 1 << 13,
/* masks */ /* masks */
@ -1039,16 +1039,16 @@ static const UINT32 kIncrementDecTable[] =
static const char *const kRegionNames[] = { static const char *const kRegionNames[] = {
"INVALID", "INVALID",
"CPU1", "CPU2", "CPU3", "CPU4", "CPU5", "CPU6", "CPU7", "CPU8", // 01-08 [01-08] : CPU "CPU1", "CPU2", "CPU3", "CPU4", "CPU5", "CPU6", "CPU7", "CPU8", // 01-08 [01-08] : CPU
"GFX1", "GFX2", "GFX3", "GFX4", "GFX5", "GFX6", "GFX7", "GFX8", // 09-16 [08-10] : GFX "GFX1", "GFX2", "GFX3", "GFX4", "GFX5", "GFX6", "GFX7", "GFX8", // 09-16 [08-10] : GFX
"PROMS", // 17 [11] : PROMS "PROMS", // 17 [11] : PROMS
"SOUND1", "SOUND2", "SOUND3", "SOUND4", "SOUND5", "SOUND6", "SOUND7", "SOUND8", // 18-25 [12-19] : SOUND "SOUND1", "SOUND2", "SOUND3", "SOUND4", "SOUND5", "SOUND6", "SOUND7", "SOUND8", // 18-25 [12-19] : SOUND
"USER1", "USER2", "USER3", "USER4", "USER5", "USER6", "USER7", "USER8", // 26-45 [1A-2D] : USER "USER1", "USER2", "USER3", "USER4", "USER5", "USER6", "USER7", "USER8", // 26-45 [1A-2D] : USER
/* USER9 - PLDS are undefined in old format */ /* USER9 - PLDS are undefined in old format */
"USER9", "USER10", "USER11", "USER12", "USER13", "USER14", "USER15", "USER16", "USER9", "USER10", "USER11", "USER12", "USER13", "USER14", "USER15", "USER16",
"USER17", "USER18", "USER19", "USER20", "USER17", "USER18", "USER19", "USER20",
"DISKS", // 46 [2E] : DISKS "DISKS", // 46 [2E] : DISKS
"PLDS" }; // 47 [2F] : PLDS "PLDS" }; // 47 [2F] : PLDS
static const char *const kNumbersTable[] = { static const char *const kNumbersTable[] = {
"0", "1", "2", "3", "4", "5", "6", "7", "0", "1", "2", "3", "4", "5", "6", "7",
@ -1437,12 +1437,12 @@ static int ShiftKeyPressed(void)
{ {
return (input_code_pressed(KEYCODE_LSHIFT) || input_code_pressed(KEYCODE_RSHIFT)); return (input_code_pressed(KEYCODE_LSHIFT) || input_code_pressed(KEYCODE_RSHIFT));
} }
static int ControlKeyPressed(void) static int ControlKeyPressed(void)
{ {
return (input_code_pressed(KEYCODE_LCONTROL) || input_code_pressed(KEYCODE_RCONTROL)); return (input_code_pressed(KEYCODE_LCONTROL) || input_code_pressed(KEYCODE_RCONTROL));
} }
static int AltKeyPressed(void) static int AltKeyPressed(void)
{ {
return (input_code_pressed(KEYCODE_LALT) || input_code_pressed(KEYCODE_RALT)); return (input_code_pressed(KEYCODE_LALT) || input_code_pressed(KEYCODE_RALT));
@ -4736,31 +4736,31 @@ static int edit_cheat_menu(running_machine *machine, cheat_menu_stack *menu)
switch(info->fieldType) switch(info->fieldType)
{ {
/* case kType_ActivationKey1: /* case kType_ActivationKey1:
case kType_ActivationKey2: case kType_ActivationKey2:
if(info->fieldType == kType_ActivationKey1) if(info->fieldType == kType_ActivationKey1)
{ {
entry->activationKey1--; entry->activationKey1--;
if(entry->activationKey1 < 0) if(entry->activationKey1 < 0)
entry->activationKey1 = __code_max - 1; entry->activationKey1 = __code_max - 1;
if(entry->activationKey1 >= __code_max) if(entry->activationKey1 >= __code_max)
entry->activationKey1 = 0; entry->activationKey1 = 0;
entry->flags |= kCheatFlag_HasActivationKey1; entry->flags |= kCheatFlag_HasActivationKey1;
} }
else else
{ {
entry->activationKey2--; entry->activationKey2--;
if(entry->activationKey2 < 0) if(entry->activationKey2 < 0)
entry->activationKey2 = __code_max - 1; entry->activationKey2 = __code_max - 1;
if(entry->activationKey2 >= __code_max) if(entry->activationKey2 >= __code_max)
entry->activationKey2 = 0; entry->activationKey2 = 0;
entry->flags |= kCheatFlag_HasActivationKey2; entry->flags |= kCheatFlag_HasActivationKey2;
} }
break; break;
*/ */
case kType_Link: case kType_Link:
TOGGLE_MASK_FIELD(action->type, LinkEnable); TOGGLE_MASK_FIELD(action->type, LinkEnable);
@ -5036,31 +5036,31 @@ static int edit_cheat_menu(running_machine *machine, cheat_menu_stack *menu)
switch(info->fieldType) switch(info->fieldType)
{ {
/* case kType_ActivationKey1: /* case kType_ActivationKey1:
case kType_ActivationKey2: case kType_ActivationKey2:
if(info->fieldType == kType_ActivationKey1) if(info->fieldType == kType_ActivationKey1)
{ {
entry->activationKey1++; entry->activationKey1++;
if(entry->activationKey1 < 0) if(entry->activationKey1 < 0)
entry->activationKey1 = __code_max - 1; entry->activationKey1 = __code_max - 1;
if(entry->activationKey1 >= __code_max) if(entry->activationKey1 >= __code_max)
entry->activationKey1 = 0; entry->activationKey1 = 0;
entry->flags |= kCheatFlag_HasActivationKey1; entry->flags |= kCheatFlag_HasActivationKey1;
} }
else else
{ {
entry->activationKey2++; entry->activationKey2++;
if(entry->activationKey2 < 0) if(entry->activationKey2 < 0)
entry->activationKey2 = __code_max - 1; entry->activationKey2 = __code_max - 1;
if(entry->activationKey2 >= __code_max) if(entry->activationKey2 >= __code_max)
entry->activationKey2 = 0; entry->activationKey2 = 0;
entry->flags |= kCheatFlag_HasActivationKey2; entry->flags |= kCheatFlag_HasActivationKey2;
} }
break; break;
*/ */
case kType_Link: case kType_Link:
TOGGLE_MASK_FIELD(action->type, LinkEnable); TOGGLE_MASK_FIELD(action->type, LinkEnable);
@ -6224,8 +6224,8 @@ static int search_minimum_menu(running_machine *machine, cheat_menu_stack *menu)
const char * menuSubItem[kMenu_Max + 1] = { 0 }; const char * menuSubItem[kMenu_Max + 1] = { 0 };
char flagBuf[kMenu_Max + 1] = { 0 }; char flagBuf[kMenu_Max + 1] = { 0 };
char cpuBuf[4]; char cpuBuf[4];
char valueBuf[32]; // "FFFFFFF[F] (4294967295)" 23 chars char valueBuf[32]; // "FFFFFFF[F] (4294967295)" 23 chars
char timerBuf[32]; // "-FFFFFFF[F] (4294967295)" 24 chars char timerBuf[32]; // "-FFFFFFF[F] (4294967295)" 24 chars
char numResultsBuf[16]; char numResultsBuf[16];
char * stringsBuf; char * stringsBuf;
search_info *search = get_current_search(); search_info *search = get_current_search();
@ -7824,7 +7824,7 @@ static int select_search_region_menu(running_machine *machine, cheat_menu_stack
} }
else else
{ {
/* in case of no SearchRegion */ /* in case of no SearchRegion */
menuItem[total] = "No Search Region"; menuItem[total] = "No Search Region";
menuSubItem[total++] = NULL; menuSubItem[total++] = NULL;
} }
@ -7903,7 +7903,7 @@ static int select_search_region_menu(running_machine *machine, cheat_menu_stack
{ {
/* SHIFT + CHEAT DELETE = invalidate selected region */ /* SHIFT + CHEAT DELETE = invalidate selected region */
invalidate_entire_region(search, region); invalidate_entire_region(search, region);
// ui_popup_time(1, "region invalidated - %d results remain", search->num_results); // ui_popup_time(1, "region invalidated - %d results remain", search->num_results);
} }
} }
else if(input_ui_pressed(machine, IPT_UI_RELOAD_CHEAT)) else if(input_ui_pressed(machine, IPT_UI_RELOAD_CHEAT))
@ -8328,7 +8328,7 @@ static int choose_watch_menu(running_machine *machine, cheat_menu_stack *menu)
UINT8 total = 0; UINT8 total = 0;
const char ** menuItem; const char ** menuItem;
char ** buf; char ** buf;
char * stringsBuf; // "USER20 FFFFFFFF (99:32 Bit)" 27 chars char * stringsBuf; // "USER20 FFFFFFFF (99:32 Bit)" 27 chars
WatchInfo * watch; WatchInfo * watch;
/* first setting : NONE */ /* first setting : NONE */
@ -10476,7 +10476,7 @@ static void ResizeCheatActionListNoDispose(CheatEntry * entry, UINT32 newLength)
/*---------------------------------------------------------------- /*----------------------------------------------------------------
AddActionBefore - Insert empty Action AddActionBefore - Insert empty Action
This function is only called in EditCheat() This function is only called in EditCheat()
----------------------------------------------------------------*/ ----------------------------------------------------------------*/
static void AddActionBefore(CheatEntry * entry, UINT32 idx) static void AddActionBefore(CheatEntry * entry, UINT32 idx)
@ -11025,7 +11025,7 @@ static UINT32 read_region_data(search_region *region, UINT32 offset, UINT8 size,
UINT8 * buf = (UINT8 *)region->cached_pointer; UINT8 * buf = (UINT8 *)region->cached_pointer;
if(buf) if(buf)
/* return DoMemoryRead(region->cached_pointer, address, size, swap, &raw_cpu_info); */ /* return DoMemoryRead(region->cached_pointer, address, size, swap, &raw_cpu_info); */
return DoMemoryRead(buf, address, size, cpu_needs_swap(region->target_idx) ^ swap, get_cpu_info(region->target_idx)); return DoMemoryRead(buf, address, size, cpu_needs_swap(region->target_idx) ^ swap, get_cpu_info(region->target_idx));
else else
return 0; return 0;
@ -15011,7 +15011,7 @@ static void BuildLabelIndexTable(CheatEntry *entry)
//logerror("Cheat - Finish building index table for %s (length = %x)\n", entry->name, entry->labelIndexLength); //logerror("Cheat - Finish building index table for %s (length = %x)\n", entry->name, entry->labelIndexLength);
//for(i = 0; i < entry->labelIndexLength; i++) //for(i = 0; i < entry->labelIndexLength; i++)
// logerror("IndexTable[%x] = %x\n",i,entry->labelIndex[i]); // logerror("IndexTable[%x] = %x\n",i,entry->labelIndex[i]);
} }

28
src/emu/cpu/cop400/410ops.c
View File

@ -60,11 +60,11 @@ static TIMER_CALLBACK(cop410_serial_tick)
{ {
/* /*
SIO is an asynchronous binary counter decrementing its value by one upon each low-going pulse ("1" to "0") occurring on the SI input. SIO is an asynchronous binary counter decrementing its value by one upon each low-going pulse ("1" to "0") occurring on the SI input.
Each pulse must remain at each logic level at least two instruction cycles. SK outputs the value of the C upon the execution of an XAS Each pulse must remain at each logic level at least two instruction cycles. SK outputs the value of the C upon the execution of an XAS
and remains latched until the execution of another XAS instruction. The SO output is equal to the value of EN3. and remains latched until the execution of another XAS instruction. The SO output is equal to the value of EN3.
*/ */
// serial output // serial output
@ -87,17 +87,17 @@ static TIMER_CALLBACK(cop410_serial_tick)
} }
else else
{ {
/* /*
SIO is a serial shift register, shifting continuously left each instruction cycle time. The data present at SI goes into the least
significant bit of SIO: SO can be enabled to output the most significant bit of SIO each cycle time. SK output becomes a logic-
controlled clock, providing a SYNC signal each instruction time. It will start outputting a SYNC pulse upon the execution of an XAS
instruction with C = "1," stopping upon the execution of a subsequent XAS with C = "0".
If EN0 is changed from "1" to "0" ("0" to "1") the SK output will change from "1" to SYNC (SYNC to "1") without the execution of SIO is a serial shift register, shifting continuously left each instruction cycle time. The data present at SI goes into the least
an XAS instruction. significant bit of SIO: SO can be enabled to output the most significant bit of SIO each cycle time. SK output becomes a logic-
controlled clock, providing a SYNC signal each instruction time. It will start outputting a SYNC pulse upon the execution of an XAS
instruction with C = "1," stopping upon the execution of a subsequent XAS with C = "0".
*/ If EN0 is changed from "1" to "0" ("0" to "1") the SK output will change from "1" to SYNC (SYNC to "1") without the execution of
an XAS instruction.
*/
// serial output // serial output

2
src/emu/cpu/cop400/cop410.c
View File

@ -14,7 +14,7 @@
TODO: TODO:
- remove LBIops - remove LBIops
- run all test suites - run all test suites
*/ */

4
src/emu/cpu/cop400/cop420.c
View File

@ -13,8 +13,8 @@
TODO: TODO:
- run interrupt test suite - run interrupt test suite
- run production test suite - run production test suite
- remove LBIops - remove LBIops
*/ */

6
src/emu/cpu/drcbex64.c
View File

@ -4845,14 +4845,14 @@ static x86code *op_setc(drcbe_state *drcbe, x86code *dst, const drcuml_instructi
emit_clc(&dst); emit_clc(&dst);
return dst; return dst;
} }
/* load non-immediate bit numbers into a register */ /* load non-immediate bit numbers into a register */
if (bitp.type != DRCUML_PTYPE_IMMEDIATE) if (bitp.type != DRCUML_PTYPE_IMMEDIATE)
{ {
emit_mov_r32_p32(drcbe, &dst, REG_ECX, &bitp); emit_mov_r32_p32(drcbe, &dst, REG_ECX, &bitp);
emit_and_r32_imm(&dst, REG_ECX, inst->size * 8 - 1); emit_and_r32_imm(&dst, REG_ECX, inst->size * 8 - 1);
} }
/* 32-bit form */ /* 32-bit form */
if (inst->size == 4) if (inst->size == 4)
{ {
@ -4871,7 +4871,7 @@ static x86code *op_setc(drcbe_state *drcbe, x86code *dst, const drcuml_instructi
emit_bt_r32_r32(&dst, srcp.value, REG_ECX); // bt srcp,ecx emit_bt_r32_r32(&dst, srcp.value, REG_ECX); // bt srcp,ecx
} }
} }
/* 64-bit form */ /* 64-bit form */
else else
{ {

6
src/emu/cpu/drcbex86.c
View File

@ -4906,14 +4906,14 @@ static x86code *op_setc(drcbe_state *drcbe, x86code *dst, const drcuml_instructi
emit_clc(&dst); emit_clc(&dst);
return dst; return dst;
} }
/* load non-immediate bit numbers into a register */ /* load non-immediate bit numbers into a register */
if (bitp.type != DRCUML_PTYPE_IMMEDIATE) if (bitp.type != DRCUML_PTYPE_IMMEDIATE)
{ {
emit_mov_r32_p32(drcbe, &dst, REG_ECX, &bitp); emit_mov_r32_p32(drcbe, &dst, REG_ECX, &bitp);
emit_and_r32_imm(&dst, REG_ECX, inst->size * 8 - 1); emit_and_r32_imm(&dst, REG_ECX, inst->size * 8 - 1);
} }
/* 32-bit form */ /* 32-bit form */
if (inst->size == 4) if (inst->size == 4)
{ {
@ -4932,7 +4932,7 @@ static x86code *op_setc(drcbe_state *drcbe, x86code *dst, const drcuml_instructi
emit_bt_r32_r32(&dst, srcp.value, REG_ECX); // bt [srcp],ecx emit_bt_r32_r32(&dst, srcp.value, REG_ECX); // bt [srcp],ecx
} }
} }
/* 64-bit form */ /* 64-bit form */
else else
{ {

14
src/emu/cpu/drcfe.c
View File

@ -12,14 +12,14 @@
Future improvements/changes: Future improvements/changes:
* change from detecting live to detecting unnecessary * change from detecting live to detecting unnecessary
- at the end of sequence: mustupdate.all = TRUE; - at the end of sequence: mustupdate.all = TRUE;
- scan backwards: - scan backwards:
inst.mustupdate = inst.update & mustupdate; inst.mustupdate = inst.update & mustupdate;
if (inst.modified.reg) mustupdate.reg = FALSE; if (inst.modified.reg) mustupdate.reg = FALSE;
if (inst.used.reg) mustupdate.reg = TRUE; if (inst.used.reg) mustupdate.reg = TRUE;
* rename UINT64 gpr, fpr to UINT32 reg[4] * rename UINT64 gpr, fpr to UINT32 reg[4]
***************************************************************************/ ***************************************************************************/

12
src/emu/cpu/drcuml.c
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@ -17,16 +17,16 @@
- checks behavior of all opcodes - checks behavior of all opcodes
* Extend registers to 16? Depends on if PPC can use them * Extend registers to 16? Depends on if PPC can use them
* Support for FPU exceptions * Support for FPU exceptions
* New instructions? * New instructions?
- FDRNDS dst,src - FDRNDS dst,src
round to single-precision round to single-precision
- FCOPYI, ICOPYF
copy raw between float and integer registers
- FCOPYI, ICOPYF
copy raw between float and integer registers
- VALID opcode_desc,handle,param - VALID opcode_desc,handle,param
checksum/compare code referenced by opcode_desc; if not checksum/compare code referenced by opcode_desc; if not
matching, generate exception with handle,param matching, generate exception with handle,param

2
src/emu/cpu/mips/mips3com.h
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@ -209,7 +209,7 @@ struct _mips3_state
/* MMU */ /* MMU */
mips3_tlb_entry tlb[MIPS3_TLB_ENTRIES]; mips3_tlb_entry tlb[MIPS3_TLB_ENTRIES];
UINT32 * tlb_table; UINT32 * tlb_table;
/* for use by specific implementations */ /* for use by specific implementations */
mips3imp_state *impstate; mips3imp_state *impstate;
}; };

36
src/emu/cpu/mips/mips3drc.c
View File

@ -11,7 +11,7 @@
**************************************************************************** ****************************************************************************
Future improvements/changes: Future improvements/changes:
* Add DRC option to flush PC before calling memory handlers * Add DRC option to flush PC before calling memory handlers
* Constant tracking? (hasn't bought us much in the past) * Constant tracking? (hasn't bought us much in the past)
@ -926,7 +926,7 @@ static void mips3_set_info(UINT32 state, cpuinfo *info)
/*------------------------------------------------- /*-------------------------------------------------
mips3_get_info - return information about a mips3_get_info - return information about a
given CPU instance given CPU instance
-------------------------------------------------*/ -------------------------------------------------*/
@ -1110,7 +1110,7 @@ static void code_compile_block(drcuml_state *drcuml, UINT8 mode, offs_t pc)
UML_HASHJMP(block, MEM(&mips3->impstate->mode), IMM(nextpc), mips3->impstate->nocode); UML_HASHJMP(block, MEM(&mips3->impstate->mode), IMM(nextpc), mips3->impstate->nocode);
// hashjmp <mode>,nextpc,nocode // hashjmp <mode>,nextpc,nocode
else if (seqlast->next == NULL || seqlast->next->pc != nextpc) else if (seqlast->next == NULL || seqlast->next->pc != nextpc)
UML_HASHJMP(block, IMM(mips3->impstate->mode), IMM(nextpc), mips3->impstate->nocode); UML_HASHJMP(block, IMM(mips3->impstate->mode), IMM(nextpc), mips3->impstate->nocode);
// hashjmp <mode>,nextpc,nocode // hashjmp <mode>,nextpc,nocode
} }
@ -1964,7 +1964,7 @@ static void generate_delay_slot_and_branch(drcuml_block *block, compiler_state *
{ {
generate_update_cycles(block, &compiler_temp, R32(RSREG), TRUE); generate_update_cycles(block, &compiler_temp, R32(RSREG), TRUE);
// <subtract cycles> // <subtract cycles>
UML_HASHJMP(block, IMM(mips3->impstate->mode), R32(RSREG), mips3->impstate->nocode); UML_HASHJMP(block, IMM(mips3->impstate->mode), R32(RSREG), mips3->impstate->nocode);
// hashjmp <mode>,<rsreg>,nocode // hashjmp <mode>,<rsreg>,nocode
} }
@ -2061,7 +2061,7 @@ static int generate_opcode(drcuml_block *block, compiler_state *compiler, const
if (mips3->impstate->drcoptions & MIPS3DRC_CHECK_OVERFLOWS) if (mips3->impstate->drcoptions & MIPS3DRC_CHECK_OVERFLOWS)
{ {
UML_ADDf(block, IREG(0), R32(RSREG), IMM(SIMMVAL), FLAGS_V); // add i0,<rsreg>,SIMMVAL,V UML_ADDf(block, IREG(0), R32(RSREG), IMM(SIMMVAL), FLAGS_V); // add i0,<rsreg>,SIMMVAL,V
UML_EXHc(block, IF_V, mips3->impstate->exception[EXCEPTION_OVERFLOW], IMM(0)); UML_EXHc(block, IF_V, mips3->impstate->exception[EXCEPTION_OVERFLOW], IMM(0));
// exh overflow,0 // exh overflow,0
} }
else else
@ -2082,7 +2082,7 @@ static int generate_opcode(drcuml_block *block, compiler_state *compiler, const
if (mips3->impstate->drcoptions & MIPS3DRC_CHECK_OVERFLOWS) if (mips3->impstate->drcoptions & MIPS3DRC_CHECK_OVERFLOWS)
{ {
UML_DADDf(block, IREG(0), R64(RSREG), IMM(SIMMVAL), FLAGS_V); // dadd i0,<rsreg>,SIMMVAL,V UML_DADDf(block, IREG(0), R64(RSREG), IMM(SIMMVAL), FLAGS_V); // dadd i0,<rsreg>,SIMMVAL,V
UML_EXHc(block, IF_V, mips3->impstate->exception[EXCEPTION_OVERFLOW], IMM(0)); UML_EXHc(block, IF_V, mips3->impstate->exception[EXCEPTION_OVERFLOW], IMM(0));
// exh overflow,0 // exh overflow,0
} }
else else
@ -2115,7 +2115,7 @@ static int generate_opcode(drcuml_block *block, compiler_state *compiler, const
if (RTREG != 0) if (RTREG != 0)
{ {
UML_DCMP(block, R64(RSREG), IMM(SIMMVAL)); // dcmp <rsreg>,SIMMVAL UML_DCMP(block, R64(RSREG), IMM(SIMMVAL)); // dcmp <rsreg>,SIMMVAL
UML_DFLAGS(block, R64(RTREG), (UINT64)~0, mips3->impstate->slt_table); UML_DFLAGS(block, R64(RTREG), (UINT64)~0, mips3->impstate->slt_table);
// dflags <rtreg>,~0,slt_table // dflags <rtreg>,~0,slt_table
} }
return TRUE; return TRUE;
@ -2220,7 +2220,7 @@ static int generate_opcode(drcuml_block *block, compiler_state *compiler, const
if (mips3->bigendian) if (mips3->bigendian)
UML_XOR(block, IREG(1), IREG(1), IMM(0x18)); // xor i1,i1,0x18 UML_XOR(block, IREG(1), IREG(1), IMM(0x18)); // xor i1,i1,0x18
UML_SHL(block, IREG(2), IMM(~0), IREG(1)); // shl i2,~0,i1 UML_SHL(block, IREG(2), IMM(~0), IREG(1)); // shl i2,~0,i1
UML_CALLH(block, mips3->impstate->read32mask[mips3->impstate->mode >> 1]); UML_CALLH(block, mips3->impstate->read32mask[mips3->impstate->mode >> 1]);
// callh read32mask // callh read32mask
if (RTREG != 0) if (RTREG != 0)
{ {
@ -2240,7 +2240,7 @@ static int generate_opcode(drcuml_block *block, compiler_state *compiler, const
if (!mips3->bigendian) if (!mips3->bigendian)
UML_XOR(block, IREG(1), IREG(1), IMM(0x38)); // xor i1,i1,0x38 UML_XOR(block, IREG(1), IREG(1), IMM(0x38)); // xor i1,i1,0x38
UML_DSHR(block, IREG(2), IMM((UINT64)~0), IREG(1)); // dshr i2,~0,i1 UML_DSHR(block, IREG(2), IMM((UINT64)~0), IREG(1)); // dshr i2,~0,i1
UML_CALLH(block, mips3->impstate->read64mask[mips3->impstate->mode >> 1]); UML_CALLH(block, mips3->impstate->read64mask[mips3->impstate->mode >> 1]);
// callh read64mask // callh read64mask
if (RTREG != 0) if (RTREG != 0)
{ {
@ -2257,7 +2257,7 @@ static int generate_opcode(drcuml_block *block, compiler_state *compiler, const
if (mips3->bigendian) if (mips3->bigendian)
UML_XOR(block, IREG(1), IREG(1), IMM(0x38)); // xor i1,i1,0x38 UML_XOR(block, IREG(1), IREG(1), IMM(0x38)); // xor i1,i1,0x38
UML_DSHL(block, IREG(2), IMM((UINT64)~0), IREG(1)); // dshl i2,~0,i1 UML_DSHL(block, IREG(2), IMM((UINT64)~0), IREG(1)); // dshl i2,~0,i1
UML_CALLH(block, mips3->impstate->read64mask[mips3->impstate->mode >> 1]); UML_CALLH(block, mips3->impstate->read64mask[mips3->impstate->mode >> 1]);
// callh read64mask // callh read64mask
if (RTREG != 0) if (RTREG != 0)
{ {
@ -2344,7 +2344,7 @@ static int generate_opcode(drcuml_block *block, compiler_state *compiler, const
UML_XOR(block, IREG(3), IREG(3), IMM(0x18)); // xor i3,i3,0x18 UML_XOR(block, IREG(3), IREG(3), IMM(0x18)); // xor i3,i3,0x18
UML_SHR(block, IREG(2), IMM(~0), IREG(3)); // shr i2,~0,i3 UML_SHR(block, IREG(2), IMM(~0), IREG(3)); // shr i2,~0,i3
UML_SHR(block, IREG(1), IREG(1), IREG(3)); // shr i1,i1,i3 UML_SHR(block, IREG(1), IREG(1), IREG(3)); // shr i1,i1,i3
UML_CALLH(block, mips3->impstate->write32mask[mips3->impstate->mode >> 1]); UML_CALLH(block, mips3->impstate->write32mask[mips3->impstate->mode >> 1]);
// callh write32mask // callh write32mask
if (!in_delay_slot) if (!in_delay_slot)
generate_update_cycles(block, compiler, IMM(desc->pc + 4), TRUE); generate_update_cycles(block, compiler, IMM(desc->pc + 4), TRUE);
@ -2358,7 +2358,7 @@ static int generate_opcode(drcuml_block *block, compiler_state *compiler, const
UML_XOR(block, IREG(3), IREG(3), IMM(0x18)); // xor i3,i3,0x18 UML_XOR(block, IREG(3), IREG(3), IMM(0x18)); // xor i3,i3,0x18
UML_SHL(block, IREG(2), IMM(~0), IREG(3)); // shl i2,~0,i3 UML_SHL(block, IREG(2), IMM(~0), IREG(3)); // shl i2,~0,i3
UML_SHL(block, IREG(1), IREG(1), IREG(3)); // shl i1,i1,i3 UML_SHL(block, IREG(1), IREG(1), IREG(3)); // shl i1,i1,i3
UML_CALLH(block, mips3->impstate->write32mask[mips3->impstate->mode >> 1]); UML_CALLH(block, mips3->impstate->write32mask[mips3->impstate->mode >> 1]);
// callh write32mask // callh write32mask
if (!in_delay_slot) if (!in_delay_slot)
generate_update_cycles(block, compiler, IMM(desc->pc + 4), TRUE); generate_update_cycles(block, compiler, IMM(desc->pc + 4), TRUE);
@ -2372,7 +2372,7 @@ static int generate_opcode(drcuml_block *block, compiler_state *compiler, const
UML_XOR(block, IREG(3), IREG(3), IMM(0x38)); // xor i3,i3,0x38 UML_XOR(block, IREG(3), IREG(3), IMM(0x38)); // xor i3,i3,0x38
UML_DSHR(block, IREG(2), IMM((UINT64)~0), IREG(3)); // dshr i2,~0,i3 UML_DSHR(block, IREG(2), IMM((UINT64)~0), IREG(3)); // dshr i2,~0,i3
UML_DSHR(block, IREG(1), IREG(1), IREG(3)); // dshr i1,i1,i3 UML_DSHR(block, IREG(1), IREG(1), IREG(3)); // dshr i1,i1,i3
UML_CALLH(block, mips3->impstate->write64mask[mips3->impstate->mode >> 1]); UML_CALLH(block, mips3->impstate->write64mask[mips3->impstate->mode >> 1]);
// callh write64mask // callh write64mask
if (!in_delay_slot) if (!in_delay_slot)
generate_update_cycles(block, compiler, IMM(desc->pc + 4), TRUE); generate_update_cycles(block, compiler, IMM(desc->pc + 4), TRUE);
@ -2386,7 +2386,7 @@ static int generate_opcode(drcuml_block *block, compiler_state *compiler, const
UML_XOR(block, IREG(3), IREG(3), IMM(0x38)); // xor i3,i3,0x38 UML_XOR(block, IREG(3), IREG(3), IMM(0x38)); // xor i3,i3,0x38
UML_DSHL(block, IREG(2), IMM((UINT64)~0), IREG(3)); // dshl i2,~0,i3 UML_DSHL(block, IREG(2), IMM((UINT64)~0), IREG(3)); // dshl i2,~0,i3
UML_DSHL(block, IREG(1), IREG(1), IREG(3)); // dshl i1,i1,i3 UML_DSHL(block, IREG(1), IREG(1), IREG(3)); // dshl i1,i1,i3
UML_CALLH(block, mips3->impstate->write64mask[mips3->impstate->mode >> 1]); UML_CALLH(block, mips3->impstate->write64mask[mips3->impstate->mode >> 1]);
// callh write64mask // callh write64mask
if (!in_delay_slot) if (!in_delay_slot)
generate_update_cycles(block, compiler, IMM(desc->pc + 4), TRUE); generate_update_cycles(block, compiler, IMM(desc->pc + 4), TRUE);
@ -2575,7 +2575,7 @@ static int generate_special(drcuml_block *block, compiler_state *compiler, const
if (mips3->impstate->drcoptions & MIPS3DRC_CHECK_OVERFLOWS) if (mips3->impstate->drcoptions & MIPS3DRC_CHECK_OVERFLOWS)
{ {
UML_ADDf(block, IREG(0), R32(RSREG), R32(RTREG), FLAGS_V); // add i0,<rsreg>,<rtreg>,V UML_ADDf(block, IREG(0), R32(RSREG), R32(RTREG), FLAGS_V); // add i0,<rsreg>,<rtreg>,V
UML_EXHc(block, IF_V, mips3->impstate->exception[EXCEPTION_OVERFLOW], IMM(0)); UML_EXHc(block, IF_V, mips3->impstate->exception[EXCEPTION_OVERFLOW], IMM(0));
// exh overflow,0,V // exh overflow,0,V
if (RDREG != 0) if (RDREG != 0)
UML_DSEXT4(block, R64(RDREG), IREG(0)); // dsext4 <rdreg>,i0 UML_DSEXT4(block, R64(RDREG), IREG(0)); // dsext4 <rdreg>,i0
@ -2599,7 +2599,7 @@ static int generate_special(drcuml_block *block, compiler_state *compiler, const
if (mips3->impstate->drcoptions & MIPS3DRC_CHECK_OVERFLOWS) if (mips3->impstate->drcoptions & MIPS3DRC_CHECK_OVERFLOWS)
{ {
UML_DADDf(block, IREG(0), R64(RSREG), R64(RTREG), FLAGS_V); // dadd i0,<rsreg>,<rtreg>,V UML_DADDf(block, IREG(0), R64(RSREG), R64(RTREG), FLAGS_V); // dadd i0,<rsreg>,<rtreg>,V
UML_EXHc(block, IF_V, mips3->impstate->exception[EXCEPTION_OVERFLOW], IMM(0)); UML_EXHc(block, IF_V, mips3->impstate->exception[EXCEPTION_OVERFLOW], IMM(0));
// exh overflow,0,V // exh overflow,0,V
if (RDREG != 0) if (RDREG != 0)
UML_DMOV(block, R64(RDREG), IREG(0)); // dmov <rdreg>,i0 UML_DMOV(block, R64(RDREG), IREG(0)); // dmov <rdreg>,i0
@ -2617,7 +2617,7 @@ static int generate_special(drcuml_block *block, compiler_state *compiler, const
if (mips3->impstate->drcoptions & MIPS3DRC_CHECK_OVERFLOWS) if (mips3->impstate->drcoptions & MIPS3DRC_CHECK_OVERFLOWS)
{ {
UML_SUBf(block, IREG(0), R32(RSREG), R32(RTREG), FLAGS_V); // sub i0,<rsreg>,<rtreg>,V UML_SUBf(block, IREG(0), R32(RSREG), R32(RTREG), FLAGS_V); // sub i0,<rsreg>,<rtreg>,V
UML_EXHc(block, IF_V, mips3->impstate->exception[EXCEPTION_OVERFLOW], IMM(0)); UML_EXHc(block, IF_V, mips3->impstate->exception[EXCEPTION_OVERFLOW], IMM(0));
// exh overflow,0,V // exh overflow,0,V
if (RDREG != 0) if (RDREG != 0)
UML_DSEXT4(block, R64(RDREG), IREG(0)); // dsext4 <rdreg>,i0 UML_DSEXT4(block, R64(RDREG), IREG(0)); // dsext4 <rdreg>,i0
@ -2641,7 +2641,7 @@ static int generate_special(drcuml_block *block, compiler_state *compiler, const
if (mips3->impstate->drcoptions & MIPS3DRC_CHECK_OVERFLOWS) if (mips3->impstate->drcoptions & MIPS3DRC_CHECK_OVERFLOWS)
{ {
UML_DSUBf(block, IREG(0), R64(RSREG), R64(RTREG), FLAGS_V); // dsub i0,<rsreg>,<rtreg>,V UML_DSUBf(block, IREG(0), R64(RSREG), R64(RTREG), FLAGS_V); // dsub i0,<rsreg>,<rtreg>,V
UML_EXHc(block, IF_V, mips3->impstate->exception[EXCEPTION_OVERFLOW], IMM(0)); UML_EXHc(block, IF_V, mips3->impstate->exception[EXCEPTION_OVERFLOW], IMM(0));
// exh overflow,0,V // exh overflow,0,V
if (RDREG != 0) if (RDREG != 0)
UML_DMOV(block, R64(RDREG), IREG(0)); // dmov <rdreg>,i0 UML_DMOV(block, R64(RDREG), IREG(0)); // dmov <rdreg>,i0

22
src/emu/inptport.c
View File

@ -613,7 +613,7 @@ INLINE const char *get_port_tag(const input_port_config *port, char *tempbuffer)
for (curport = port->machine->portconfig; curport != NULL; curport = curport->next) for (curport = port->machine->portconfig; curport != NULL; curport = curport->next)
{ {
if (curport == port) if (curport == port)
break; break;
index++; index++;
} }
sprintf(tempbuffer, "(PORT#%d)", index); sprintf(tempbuffer, "(PORT#%d)", index);
@ -636,7 +636,7 @@ INLINE void *error_buf_append(char *errorbuf, int errorbuflen, const char *forma
if (strlen(format) + 25 < bytesleft) if (strlen(format) + 25 < bytesleft)
vsprintf(&errorbuf[curlen], format, va); vsprintf(&errorbuf[curlen], format, va);
va_end(va); va_end(va);
return NULL; return NULL;
} }
@ -904,8 +904,8 @@ void input_field_set_user_settings(const input_field_config *field, const input_
/*------------------------------------------------- /*-------------------------------------------------
input_field_select_previous_setting - select input_field_select_previous_setting - select
the previous item for a DIP switch or the previous item for a DIP switch or
configuration field configuration field
-------------------------------------------------*/ -------------------------------------------------*/
@ -913,7 +913,7 @@ void input_field_select_previous_setting(const input_field_config *field)
{ {
const input_setting_config *setting, *prevsetting; const input_setting_config *setting, *prevsetting;
int found_match = FALSE; int found_match = FALSE;
/* only makes sense if we have settings */ /* only makes sense if we have settings */
assert(field->settinglist != NULL); assert(field->settinglist != NULL);
@ -947,7 +947,7 @@ void input_field_select_previous_setting(const input_field_config *field)
/*------------------------------------------------- /*-------------------------------------------------
input_field_select_next_setting - select the input_field_select_next_setting - select the
next item for a DIP switch or next item for a DIP switch or
configuration field configuration field
-------------------------------------------------*/ -------------------------------------------------*/
@ -2945,7 +2945,7 @@ static input_port_config *port_config_detokenize(input_port_config *listhead, co
break; break;
} }
} }
/* insert any pending fields */ /* insert any pending fields */
if (curfield != NULL) if (curfield != NULL)
field_config_insert(curfield, &maskbits, errorbuf, errorbuflen); field_config_insert(curfield, &maskbits, errorbuf, errorbuflen);
@ -3026,7 +3026,7 @@ static input_field_config *field_config_alloc(input_port_config *port, int type,
{ {
input_field_config *config; input_field_config *config;
int seqtype; int seqtype;
/* allocate memory */ /* allocate memory */
config = malloc_or_die(sizeof(*config)); config = malloc_or_die(sizeof(*config));
memset(config, 0, sizeof(*config)); memset(config, 0, sizeof(*config));
@ -3046,8 +3046,8 @@ static input_field_config *field_config_alloc(input_port_config *port, int type,
/*------------------------------------------------- /*-------------------------------------------------
field_config_insert - insert an allocated field_config_insert - insert an allocated
input port field config, replacing any input port field config, replacing any
intersecting fields already present and intersecting fields already present and
inserting at the correct sorted location inserting at the correct sorted location
-------------------------------------------------*/ -------------------------------------------------*/
@ -3741,7 +3741,7 @@ static void save_game_inputs(running_machine *machine, xml_data_node *parentnode
if (portnode != NULL) if (portnode != NULL)
{ {
char tempbuffer[20]; char tempbuffer[20];
/* add the identifying information and attributes */ /* add the identifying information and attributes */
xml_set_attribute(portnode, "tag", get_port_tag(port, tempbuffer)); xml_set_attribute(portnode, "tag", get_port_tag(port, tempbuffer));
xml_set_attribute(portnode, "type", input_field_type_to_token(machine, field->type, field->player)); xml_set_attribute(portnode, "type", input_field_type_to_token(machine, field->type, field->player));

16
src/emu/machine/8257dma.c
View File

@ -5,10 +5,10 @@
For datasheet http://www.threedee.com/jcm/library/index.html For datasheet http://www.threedee.com/jcm/library/index.html
2008/05 Miodrag Milanovic 2008/05 Miodrag Milanovic
- added support for autoload mode - added support for autoload mode
- fixed bug in calculating count - fixed bug in calculating count
2007/11 couriersud 2007/11 couriersud
- architecture copied from 8237 DMA - architecture copied from 8237 DMA
@ -172,9 +172,9 @@ static int dma8257_do_operation(int which, int channel)
{ {
if ((channel==2) && DMA_MODE_AUTOLOAD(dma[which].mode)) { if ((channel==2) && DMA_MODE_AUTOLOAD(dma[which].mode)) {
/* in case of autoload at the end channel 3 info is */ /* in case of autoload at the end channel 3 info is */
/* copied to channel 2 info */ /* copied to channel 2 info */
dma[which].registers[4] = dma[which].registers[6]; dma[which].registers[4] = dma[which].registers[6];
dma[which].registers[5] = dma[which].registers[7]; dma[which].registers[5] = dma[which].registers[7];
} }
if (dma[which].intf->out_tc_func[channel]) if (dma[which].intf->out_tc_func[channel])
dma[which].intf->out_tc_func[channel](CLEAR_LINE); dma[which].intf->out_tc_func[channel](CLEAR_LINE);
@ -319,7 +319,7 @@ static void dma8257_write(int which, offs_t offset, UINT8 data)
if (DMA_MODE_AUTOLOAD(dma[which].mode)) { if (DMA_MODE_AUTOLOAD(dma[which].mode)) {
/* in case of autoload when inserting channel 2 info */ /* in case of autoload when inserting channel 2 info */
/* it is automaticaly copied to channel 3 info */ /* it is automaticaly copied to channel 3 info */
switch(offset) { switch(offset) {
case 4: case 4:
case 5: case 5:
@ -329,7 +329,7 @@ static void dma8257_write(int which, offs_t offset, UINT8 data)
dma[which].registers[offset+2] = data; dma[which].registers[offset+2] = data;
} }
} }
prepare_msb_flip(which); prepare_msb_flip(which);
break; break;

16
src/emu/video.c
View File

@ -2219,40 +2219,40 @@ static file_error mame_fopen_next(running_machine *machine, const char *pathopti
astring *fname = astring_alloc(); astring *fname = astring_alloc();
file_error filerr; file_error filerr;
int index; int index;
/* handle defaults */ /* handle defaults */
if (snapname == NULL || snapname[0] == 0) if (snapname == NULL || snapname[0] == 0)
snapname = "%g/%i"; snapname = "%g/%i";
astring_cpyc(snapstr, snapname); astring_cpyc(snapstr, snapname);
/* strip any extension in the provided name and add our own */ /* strip any extension in the provided name and add our own */
index = astring_rchr(snapstr, 0, '.'); index = astring_rchr(snapstr, 0, '.');
if (index != -1) if (index != -1)
astring_substr(snapstr, 0, index); astring_substr(snapstr, 0, index);
astring_catc(snapstr, "."); astring_catc(snapstr, ".");
astring_catc(snapstr, extension); astring_catc(snapstr, extension);
/* substitute path and gamename up front */ /* substitute path and gamename up front */
astring_replacec(snapstr, 0, "/", PATH_SEPARATOR); astring_replacec(snapstr, 0, "/", PATH_SEPARATOR);
astring_replacec(snapstr, 0, "%g", machine->basename); astring_replacec(snapstr, 0, "%g", machine->basename);
/* determine if the template has an index; if not, we always use the same name */ /* determine if the template has an index; if not, we always use the same name */
if (astring_findc(snapstr, 0, "%i") == -1) if (astring_findc(snapstr, 0, "%i") == -1)
astring_cpy(fname, snapstr); astring_cpy(fname, snapstr);
/* otherwise, we scan for the next available filename */ /* otherwise, we scan for the next available filename */
else else
{ {
int seq; int seq;
/* try until we succeed */ /* try until we succeed */
for (seq = 0; ; seq++) for (seq = 0; ; seq++)
{ {
char seqtext[10]; char seqtext[10];
/* make text for the sequence number */ /* make text for the sequence number */
sprintf(seqtext, "%04d", seq); sprintf(seqtext, "%04d", seq);
/* build up the filename */ /* build up the filename */
astring_cpy(fname, snapstr); astring_cpy(fname, snapstr);
astring_replacec(fname, 0, "%i", seqtext); astring_replacec(fname, 0, "%i", seqtext);

10
src/lib/util/astring.c
View File

@ -523,8 +523,8 @@ int astring_findc(const astring *str, int start, const char *search)
/*------------------------------------------------- /*-------------------------------------------------
astring_replace - search in an astring for astring_replace - search in an astring for
another astring, replacing all instances with another astring, replacing all instances with
a third and returning the number of matches a third and returning the number of matches
-------------------------------------------------*/ -------------------------------------------------*/
@ -535,8 +535,8 @@ int astring_replace(astring *str, int start, const astring *search, const astrin
/*------------------------------------------------- /*-------------------------------------------------
astring_replacec - search in an astring for a astring_replacec - search in an astring for a
C string, replacing all instances with another C string, replacing all instances with another
C string and returning the number of matches C string and returning the number of matches
-------------------------------------------------*/ -------------------------------------------------*/
@ -546,7 +546,7 @@ int astring_replacec(astring *str, int start, const char *search, const char *re
int replacelen = strlen(replace); int replacelen = strlen(replace);
int matches = 0; int matches = 0;
int curindex; int curindex;
for (curindex = astring_findc(str, start, search); curindex != -1; curindex = astring_findc(str, curindex + replacelen, search)) for (curindex = astring_findc(str, start, search); curindex != -1; curindex = astring_findc(str, curindex + replacelen, search))
{ {
matches++; matches++;

6
src/mame/drivers/ampoker2.c
View File

@ -229,7 +229,7 @@
Resistor Network Resistor Network
---------------- ----------------
The following diagram is related to taiwanese and argentine PCBs. The following diagram is related to taiwanese and argentine PCBs.
@ -532,11 +532,11 @@ static WRITE8_HANDLER( ampoker2_watchdog_reset_w )
if (((data >> 3) & 0x01) == 0) /* check for refresh value (0x08) */ if (((data >> 3) & 0x01) == 0) /* check for refresh value (0x08) */
{ {
watchdog_reset(machine); watchdog_reset(machine);
// popmessage("%02x", data); // popmessage("%02x", data);
} }
else else
{ {
// popmessage("%02x", data); // popmessage("%02x", data);
} }
} }

2
src/mame/drivers/astrof.c
View File

@ -149,7 +149,7 @@ static CUSTOM_INPUT( tomahawk_controls_r )
/* on a cocktail cabinet, two sets of controls are /* on a cocktail cabinet, two sets of controls are
multiplexed on a single set of inputs multiplexed on a single set of inputs
(not verified on pcb) */ (not verified on pcb) */
if (flipscreen) if (flipscreen)
ret = input_port_read(field->port->machine, "P2"); ret = input_port_read(field->port->machine, "P2");

2
src/mame/drivers/bking.c
View File

@ -264,7 +264,7 @@ static INPUT_PORTS_START( bking )
/* continue inputs are labelled in schematics. */ /* continue inputs are labelled in schematics. */
/* They are not connected though to any button */ /* They are not connected though to any button */
PORT_START /* IN1 */ PORT_START /* IN1 */
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_START1 ) PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_START1 )
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_START2 ) PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_START2 )

362
src/mame/drivers/hornet.c
View File

@ -2,19 +2,19 @@
Driver by Ville Linde Driver by Ville Linde
Konami 'Hornet' Hardware Konami 'Hornet' Hardware
Konami, 1997-1999 Konami, 1997-1999
Known games on this hardware include.... Known games on this hardware include....
Game (C) Year Game (C) Year
---------------------------------------------- ----------------------------------------------
Gradius 4 : Fukkatsu Konami 1999 Gradius 4 : Fukkatsu Konami 1999
NBA Play by Play Konami 1998 NBA Play by Play Konami 1998
Silent Scope Konami 1999 Silent Scope Konami 1999
Silent Scope 2 : Fatal Judgement Konami 2000 Silent Scope 2 : Fatal Judgement Konami 2000
Silent Scope 2 : Dark Silhouette Konami 2000 Silent Scope 2 : Dark Silhouette Konami 2000
Terraburst Konami 1998 Terraburst Konami 1998
Hardware overview: Hardware overview:
@ -42,185 +42,185 @@
3DFX 500-0010-01 (Voodoo 2) TMU with 4MB RAM 3DFX 500-0010-01 (Voodoo 2) TMU with 4MB RAM
Hardware configurations: Hardware configurations:
------------------------ ------------------------
Game KONAMI ID CPU PCB GFX Board(s) LAN PCB Game KONAMI ID CPU PCB GFX Board(s) LAN PCB
-------------------------------------------------------------- --------------------------------------------------------------
Gradius 4 GX837 GN715(A) GN715(B) Gradius 4 GX837 GN715(A) GN715(B)
NBA Play By Play GX778 GN715(A) GN715(B) NBA Play By Play GX778 GN715(A) GN715(B)
Silent Scope GQ830 GN715(A) 2x GN715(B) Silent Scope GQ830 GN715(A) 2x GN715(B)
Silent Scope 2 GQ931 GN715(A) 2x GQ871(B) GQ931(H) Silent Scope 2 GQ931 GN715(A) 2x GQ871(B) GQ931(H)
PCB Layouts PCB Layouts
----------- -----------
Top Board Top Board
GN715 PWB(A)A GN715 PWB(A)A
|--------------------------------------------------------------| |--------------------------------------------------------------|
| SP485CS CN10 CN11 CN9 JP8 JP9 JP10 JP11| | SP485CS CN10 CN11 CN9 JP8 JP9 JP10 JP11|
|CN19 PAL1 | |CN19 PAL1 |
|CN21 JP13 PAL2 68EC000 EPROM.7S | |CN21 JP13 PAL2 68EC000 EPROM.7S |
| NE5532 PAL3 CN12| | NE5532 PAL3 CN12|
| JP12 JP16 DRM1M4SJ8 CN13| | JP12 JP16 DRM1M4SJ8 CN13|
| NE5532 MASKROM.9P MASKROM.9T | | NE5532 MASKROM.9P MASKROM.9T |
| SM5877 JP15 RF5C400 | | SM5877 JP15 RF5C400 |
|CN18 MASKROM.12P MASKROM.12T| |CN18 MASKROM.12P MASKROM.12T|
| SM5877 16.9344MHz | | SM5877 16.9344MHz |
|CN14 SRAM256K MASKROM.14P MASKROM.14T| |CN14 SRAM256K MASKROM.14P MASKROM.14T|
| | | |
|CN16 SRAM256K MASKROM.16P MASKROM.16T| |CN16 SRAM256K MASKROM.16P MASKROM.16T|
| ADC12138 | | ADC12138 |
| 056800 JP5 | | 056800 JP5 |
| JP4 | | JP4 |
| MACH111 JP3 |---------| | | MACH111 JP3 |---------| |
| TEST_SW EPROM.22P | | | | TEST_SW EPROM.22P | | |
|CN1 DRAM16X16 |PPC403GA | | |CN1 DRAM16X16 |PPC403GA | |
| EPROM.25P | | | | EPROM.25P | | |
| | | | | | | |
| DRAM16X16 EPROM.27P |---------| | | DRAM16X16 EPROM.27P |---------| |
| 4AK16 JP6| | 4AK16 JP6|
| | | |
|CN3 | |CN3 |
| 0038323 PAL4 7.3728MHz| | 0038323 PAL4 7.3728MHz|
| E9825 058232 CN2 | | E9825 058232 CN2 |
| 50.000MHz| | 50.000MHz|
| RESET_SW CN5 JP1 JP2 | | RESET_SW CN5 JP1 JP2 |
|M48T58Y-70PC1 CN4 CN6 64.000MHz| |M48T58Y-70PC1 CN4 CN6 64.000MHz|
|--------------------------------------------------------------| |--------------------------------------------------------------|
Notes: Notes:
DRM1M4SJ8 - Fujitsu 81C4256 256Kx4 DRAM (SOJ24) DRM1M4SJ8 - Fujitsu 81C4256 256Kx4 DRAM (SOJ24)
SRAM256K - Cypress CY7C199 32kx8 SRAM (SOJ28) SRAM256K - Cypress CY7C199 32kx8 SRAM (SOJ28)
DRAM16X16 - Fujitsu 8118160A-60 16megx16 DRAM (SOJ42) DRAM16X16 - Fujitsu 8118160A-60 16megx16 DRAM (SOJ42)
0038323 E9825 - SOIC8 (Secured PIC?). I've seen a similar chip in the security cart of System573 0038323 E9825 - SOIC8 (Secured PIC?). I've seen a similar chip in the security cart of System573
M48T58Y-70PC1 - ST Timekeeper RAM M48T58Y-70PC1 - ST Timekeeper RAM
RF5C400 - Ricoh RF5C400 PCM 32Ch, 44.1 kHz Stereo, 3D Effect Spatializer, clock input 16.9344MHz RF5C400 - Ricoh RF5C400 PCM 32Ch, 44.1 kHz Stereo, 3D Effect Spatializer, clock input 16.9344MHz
056800 - Konami Custom (QFP80) 056800 - Konami Custom (QFP80)
058232 - Konami Custom Ceramic Package (SIL14) 058232 - Konami Custom Ceramic Package (SIL14)
ADC12138 - National Semiconductor ADC12138 A/D Converter, 12-bit + Serial I/O With MUX (SOP28) ADC12138 - National Semiconductor ADC12138 A/D Converter, 12-bit + Serial I/O With MUX (SOP28)
MACH111 - AMD MACH111 CPLD (Stamped 'N676A1', PLCC44) MACH111 - AMD MACH111 CPLD (Stamped 'N676A1', PLCC44)
68EC000 - Motorola MC68EC000, running at 16.0MHz (64/4) 68EC000 - Motorola MC68EC000, running at 16.0MHz (64/4)
PPC403GA - IBM PowerPC 403GA CPU, clock input 32.0MHz (QFP160) PPC403GA - IBM PowerPC 403GA CPU, clock input 32.0MHz (QFP160)
SM5877AM - Nippon Precision Circuits 3rd Order 2-Channel D/A Converter (SOIC24) SM5877AM - Nippon Precision Circuits 3rd Order 2-Channel D/A Converter (SOIC24)
4AK16 - Hitachi 4AK16 Silicon N-Channel Power MOS FET Array (SIL10) 4AK16 - Hitachi 4AK16 Silicon N-Channel Power MOS FET Array (SIL10)
NE5532AN - Philips, Dual Low-Noise High-Speed Audio OP Amp (DIP8) NE5532AN - Philips, Dual Low-Noise High-Speed Audio OP Amp (DIP8)
SP485CS - Sipex SP485CS Low Power Half Duplex RS485 Transceiver (DIP8) SP485CS - Sipex SP485CS Low Power Half Duplex RS485 Transceiver (DIP8)
PAL1 - AMD PALCE16V8 (stamped 'N676A4', DIP20) PAL1 - AMD PALCE16V8 (stamped 'N676A4', DIP20)
PAL2 - AMD PALCE16V8 (stamped 'N676A2', DIP20) PAL2 - AMD PALCE16V8 (stamped 'N676A2', DIP20)
PAL3 - AMD PALCE16V8 (stamped 'N676A3', DIP20) PAL3 - AMD PALCE16V8 (stamped 'N676A3', DIP20)
PAL4 - AMD PALCE16V8 (stamped 'N676A5', DIP20) PAL4 - AMD PALCE16V8 (stamped 'N676A5', DIP20)
JP1 - 25M O O-O 32M JP1 - 25M O O-O 32M
JP2 - 25M O O-O 32M JP2 - 25M O O-O 32M
JP3 - RW O O O RO JP3 - RW O O O RO
JP4 - PROG 32M O O-O 16M JP4 - PROG 32M O O-O 16M
JP5 - DATA 32M O-O O 16M JP5 - DATA 32M O-O O 16M
JP6 - BOOT 16 O-O O 32 JP6 - BOOT 16 O-O O 32
JP7 - SRC DOUT2 O O-O 0 JP7 - SRC DOUT2 O O-O 0
JP8 - 64M&32M O-O O 16M JP8 - 64M&32M O-O O 16M
JP9 - 64M O O-O 32M&16M JP9 - 64M O O-O 32M&16M
JP10 - 64M&32M O-O O 16M JP10 - 64M&32M O-O O 16M
JP11 - 64M O O-O 32M&16M JP11 - 64M O O-O 32M&16M
JP12 - THRU O-O O SP JP12 - THRU O-O O SP
JP13 - THRU O-O O SP JP13 - THRU O-O O SP
JP14 - WDT O O JP14 - WDT O O
JP15 - MONO O-O O SURR JP15 - MONO O-O O SURR
JP16 - HIGH O O O MID (N/C LOW) JP16 - HIGH O O O MID (N/C LOW)
CN1 THRU CN3 - Multi-pin Flat Cable Connector CN1 THRU CN3 - Multi-pin Flat Cable Connector
CN4 - Multi-pin Connector for Network PCB CN4 - Multi-pin Connector for Network PCB
CN5 - Multi-pin Flat Cable Connector CN5 - Multi-pin Flat Cable Connector
CN6 - 96-Pin To Lower PCB, Joining Connector CN6 - 96-Pin To Lower PCB, Joining Connector
CN7 THRU CN8 - Not used CN7 THRU CN8 - Not used
CN9 THRU CN11 - 6-Pin Power Connectors CN9 THRU CN11 - 6-Pin Power Connectors
CN19 - USB Connector CN19 - USB Connector
CN21 - 5-Pin Analog Controls Connector (Tied to USB Connector via the Filter Board) CN21 - 5-Pin Analog Controls Connector (Tied to USB Connector via the Filter Board)
CN18 - RCA Mono Audio OUT CN18 - RCA Mono Audio OUT
CN14 & CN16 - RCA Stereo Audio OUT CN14 & CN16 - RCA Stereo Audio OUT
ROM Usage ROM Usage
--------- ---------
|------------------------------- ROM Locations ----------------------------------| |------------------------------- ROM Locations ----------------------------------|
Game 27P 25P 22P 16P 14P 12P 9P 16T 14T 12T 9T 7S Game 27P 25P 22P 16P 14P 12P 9P 16T 14T 12T 9T 7S
----------------------------------------------------------------------------------------------- -----------------------------------------------------------------------------------------------
Gradius 4 837C01 - - 837A09 837A10 - 778A12 837A04 837A05 - - 837A08 Gradius 4 837C01 - - 837A09 837A10 - 778A12 837A04 837A05 - - 837A08
NBA P/Play 778A01 - - 778A09 778A10 778A11 778A12 778A04 778A05 - - 778A08 NBA P/Play 778A01 - - 778A09 778A10 778A11 778A12 778A04 778A05 - - 778A08
S/Scope 830B01 - - 830A09 830A10 - - - - - - 830A08 S/Scope 830B01 - - 830A09 830A10 - - - - - - 830A08
S/Scope 2 931D01 - - 931A09 931A10 931A11 - 931A04 - - - 931A08 S/Scope 2 931D01 - - 931A09 931A10 931A11 - 931A04 - - - 931A08
Terraburst Terraburst
Bottom Board Bottom Board
GN715 PWB(B)A GN715 PWB(B)A
|--------------------------------------------------------------| |--------------------------------------------------------------|
|CN4 CN2 CN8 CN6 CN5| |CN4 CN2 CN8 CN6 CN5|
|JP1 |---------| 4M_EDO 4M_EDO | |JP1 |---------| 4M_EDO 4M_EDO |
| | | |----------| | | | | |----------| |
| 4M_EDO 4M_EDO | TEXELFX | | | | | 4M_EDO 4M_EDO | TEXELFX | | | |
| | | | PIXELFX | 4M_EDO | | | | | PIXELFX | 4M_EDO |
| 4M_EDO 4M_EDO | | | | 4M_EDO | | 4M_EDO 4M_EDO | | | | 4M_EDO |
| |---------| | | |--------| | | |---------| | | |--------| |
| 4M_EDO 4M_EDO |----------| |KONAMI | | | 4M_EDO 4M_EDO |----------| |KONAMI | |
|CN3 50MHz JP7 |33906 | | |CN3 50MHz JP7 |33906 | |
| 4M_EDO 4M_EDO JP6 | | | | 4M_EDO 4M_EDO JP6 | | |
| 256KSRAM 256KSRAM |--------| | | 256KSRAM 256KSRAM |--------| |
|CN7 | |CN7 |
| AV9170 1MSRAM 1MSRAM | | AV9170 1MSRAM 1MSRAM |
| MC44200 | | MC44200 |
| 256KSRAM 256KSRAM | | 256KSRAM 256KSRAM |
| 1MSRAM 1MSRAM | | 1MSRAM 1MSRAM |
| |-------| MASKROM.24U | | |-------| MASKROM.24U |
| |KONAMI | MACH111 |-------------| MASKROM.24V| | |KONAMI | MACH111 |-------------| MASKROM.24V|
| |37122 | |ANALOG | 1MSRAM 1MSRAM | | |37122 | |ANALOG | 1MSRAM 1MSRAM |
| | | |DEVICES | | | | | |DEVICES | |
| |-------| JP5 |ADSP-21062 | 36.00MHz | | |-------| JP5 |ADSP-21062 | 36.00MHz |
|1MSRAM |SHARC | 1MSRAM 1MSRAM | |1MSRAM |SHARC | 1MSRAM 1MSRAM |
| | | | | | | |
|1MSRAM | | | |1MSRAM | | |
| 256KSRAM |-------------| MASKROM.32U | | 256KSRAM |-------------| MASKROM.32U |
|1MSRAM 256KSRAM MASKROM.32V| |1MSRAM 256KSRAM MASKROM.32V|
| 256KSRAM PAL1 PAL2 JP4 | | 256KSRAM PAL1 PAL2 JP4 |
|1MSRAM | |1MSRAM |
| JP2 CN1 JP3 | | JP2 CN1 JP3 |
|--------------------------------------------------------------| |--------------------------------------------------------------|
Notes: Notes:
4M_EDO - Silicon Magic SM81C256K16CJ-35 EDO DRAM 66MHz (SOJ40) 4M_EDO - Silicon Magic SM81C256K16CJ-35 EDO DRAM 66MHz (SOJ40)
1MSRAM - Cypress CY7C109-25VC 1Meg SRAM (SOJ32) 1MSRAM - Cypress CY7C109-25VC 1Meg SRAM (SOJ32)
256KSRAM - Winbond W24257AJ-15 256K SRAM (SOJ28) 256KSRAM - Winbond W24257AJ-15 256K SRAM (SOJ28)
TEXELFX - 3DFX 500-0004-02 BD0665.1 TMU (QFP208) TEXELFX - 3DFX 500-0004-02 BD0665.1 TMU (QFP208)
PIXELFX - 3DFX 500-0003-03 F001701.1 FBI (QFP240) PIXELFX - 3DFX 500-0003-03 F001701.1 FBI (QFP240)
0000037122 - Konami Custom (QFP208) 0000037122 - Konami Custom (QFP208)
MC44200FT - Motorola MC44200FT 3 Channel Video D/A Converter (QFP44) MC44200FT - Motorola MC44200FT 3 Channel Video D/A Converter (QFP44)
MACH111 - AMD MACH111 CPLD (Stamped 'N715B1', PLCC44) MACH111 - AMD MACH111 CPLD (Stamped 'N715B1', PLCC44)
AV9170 - Integrated Circuit Systems Inc. Clock Multiplier (SOIC8) AV9170 - Integrated Circuit Systems Inc. Clock Multiplier (SOIC8)
PAL1 - AMD PALCE16V8 (stamped 'N676B4', DIP20) PAL1 - AMD PALCE16V8 (stamped 'N676B4', DIP20)
PAL2 - AMD PALCE16V8 (stamped 'N676B5', DIP20) PAL2 - AMD PALCE16V8 (stamped 'N676B5', DIP20)
JP1 - SCR O O-O TWN JP1 - SCR O O-O TWN
JP2 - MASTER O-O O SLAVE JP2 - MASTER O-O O SLAVE
JP3 - 16M O O-O 32M JP3 - 16M O O-O 32M
JP4 - 32M O-O O 16M JP4 - 32M O-O O 16M
JP5 - ASYNC O O-O SYNC JP5 - ASYNC O O-O SYNC
JP6 - DSP O O-O ADCK JP6 - DSP O O-O ADCK
JP7 - MCK O-O O SCK JP7 - MCK O-O O SCK
CN1 - 96 Pin To Lower PCB, Joining Connector CN1 - 96 Pin To Lower PCB, Joining Connector
CN2 - 8-Pin RGB OUT CN2 - 8-Pin RGB OUT
CN3 - 15-Pin DSUB VGA Video MAIN OUT CN3 - 15-Pin DSUB VGA Video MAIN OUT
CN4 - 6-Pin Power Connector CN4 - 6-Pin Power Connector
CN5 - 4-Pin Power Connector CN5 - 4-Pin Power Connector
CN6 - 2-Pin Connector (Not Used) CN6 - 2-Pin Connector (Not Used)
CN7 - 15-Pin DSUB VGA Video MAIN OUT CN7 - 15-Pin DSUB VGA Video MAIN OUT
CN8 - 6-Pin Connector (Not Used) CN8 - 6-Pin Connector (Not Used)
ROM Usage ROM Usage
--------- ---------
|------ ROM Locations -------| |------ ROM Locations -------|
Game 24U 24V 32U 32V Game 24U 24V 32U 32V
------------------------------------------- -------------------------------------------
Gradius 4 837A13 837A15 837A14 837A16 Gradius 4 837A13 837A15 837A14 837A16
NBA P/Play 778A13 778A15 778A14 778A16 NBA P/Play 778A13 778A15 778A14 778A16
S/Scope - - - - (no ROMs, not used) S/Scope - - - - (no ROMs, not used)
S/Scope 2 - - - - (no ROMs, not used) S/Scope 2 - - - - (no ROMs, not used)
Terraburst Terraburst

6
src/mame/drivers/konamim2.c
View File

@ -10,11 +10,11 @@ This hardware is 3DO-based with two IBM Power PC CPUs.
There were only 5 known games on this hardware. They include.... There were only 5 known games on this hardware. They include....
Game Year CD Codes Konami Part# Game Year CD Codes Konami Part#
-------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------
Battle Tryst 1998 636JAC02 Battle Tryst 1998 636JAC02
Evil Night 1998 810UBA02 Evil Night 1998 810UBA02
Hell Night ((alt. Region title, same as Evil Night) 1998 810EAA02 Hell Night ((alt. Region title, same as Evil Night) 1998 810EAA02
Heat Of Eleven '98 1998 703EAA02 Heat Of Eleven '98 1998 703EAA02
Polystars 1997 623JAA02 003894 Polystars 1997 623JAA02 003894
Total Vice 1997 639AAB01 Total Vice 1997 639AAB01
@ -153,7 +153,7 @@ Notes:
This PCB is used on Total Vice only. This PCB is used on Total Vice only.
639JAA02.xx - 8MBit Sound data ROM (DIP42) 639JAA02.xx - 8MBit Sound data ROM (DIP42)
PAL - PAL16V8H stampd ' ' PAL - PAL16V8H stampd ' '
PWB0000047043 (C) 1998 KONAMI CO., LTD. PWB0000047043 (C) 1998 KONAMI CO., LTD.
|-----------------------------------------| |-----------------------------------------|

12
src/mame/drivers/magic10.c
View File

@ -466,9 +466,9 @@ ROM_END
/* /*
Super Pool Super Pool
ABM (Nazionale Elettronica Giochi S.A.S.), 1998. ABM (Nazionale Elettronica Giochi S.A.S.), 1998.
9743 Rev.01 9743 Rev.01
1x MC68HC000P10 1x MC68HC000P10
1x ACTEL A1020B-PL84C 1x ACTEL A1020B-PL84C
@ -478,13 +478,13 @@ ABM (Nazionale Elettronica Giochi S.A.S.), 1998.
1x TDA2003 (sound) 1x TDA2003 (sound)
1x oscillator 20.000MHz 1x oscillator 20.000MHz
1x oscillator 30.0000MHz 1x oscillator 30.0000MHz
1x blu resonator 1000J (close to sound) 1x blu resonator 1000J (close to sound)
1x M27C2001 (1) (Sound) 1x M27C2001 (1) (Sound)
2x TMS27C010A (2,3) (main) 2x TMS27C010A (2,3) (main)
4x TMS27C010A (4,5,6,7) (gfx) 4x TMS27C010A (4,5,6,7) (gfx)
1x PALCE22V10H (not dumped) 1x PALCE22V10H (not dumped)
1x PALCE16V8H (not dumped) 1x PALCE16V8H (not dumped)
1x 28x2 JAMMA edge connector 1x 28x2 JAMMA edge connector
1x 12 legs connector (J1) 1x 12 legs connector (J1)
@ -492,7 +492,7 @@ ABM (Nazionale Elettronica Giochi S.A.S.), 1998.
1x 8x2 switches dip 1x 8x2 switches dip
1x lithium battery 1x lithium battery
*/ */
ROM_START( suprpool ) ROM_START( suprpool )
ROM_REGION( 0x40000, REGION_CPU1, 0 ) /* 68000 Code */ ROM_REGION( 0x40000, REGION_CPU1, 0 ) /* 68000 Code */

52
src/mame/drivers/model2.c
View File

@ -3156,7 +3156,7 @@ RAM : M5M44170CJ (x2), HM514270CJ7 (x1), HM538254BJ-7 (x4), N341256SJ-15 (x10)
UM62256EM-70LL (x4), TC18128CFWL-80V (x12), TC55V328AJ-15 (x3) UM62256EM-70LL (x4), TC18128CFWL-80V (x12), TC55V328AJ-15 (x3)
CY7C185-25VC (x7), CY7C188-25VC (x2), dt71256 (x4), BR6265BF-10SL (x2) CY7C185-25VC (x7), CY7C188-25VC (x2), dt71256 (x4), BR6265BF-10SL (x2)
65256BLFP-10T (x2), LH521002AK-20 (x16) 65256BLFP-10T (x2), LH521002AK-20 (x16)
CUSTOM: SEGA 315-5687 (128 QFP) CUSTOM: SEGA 315-5687 (128 QFP)
FUJITSU MB86235 (x2, 208 QFP) FUJITSU MB86235 (x2, 208 QFP)
SEGA 315-5673 (240 QFP) SEGA 315-5673 (240 QFP)
@ -3174,32 +3174,32 @@ OTHER : D71051GU-10
Note: All epr* ROMs are 27C1024 Note: All epr* ROMs are 27C1024
All mpr* ROMs are 16M MASK All mpr* ROMs are 16M MASK
[JUMPERS] [JUMPERS]
JP1 2-3 JP1 2-3
JP2 1-2 JP2 1-2
JP3 2-3 JP3 2-3
JP4 1-2 JP4 1-2
JP5 1-2 JP5 1-2
JP6 1-2 JP6 1-2
JP7 1-2 JP7 1-2
JP8 2-3 JP8 2-3
JP9 2-3 JP9 2-3
JP10 1-2 JP10 1-2
JP11 1-2 JP11 1-2
JP12 1-2 JP12 1-2
JP13 1-2 JP13 1-2
JP14 1-2 JP14 1-2
JP15 2-3 JP15 2-3
JP16 1-2 JP16 1-2
JP17 1-2 JP17 1-2
JP18 1-2 JP18 1-2
JP19 1-2 JP19 1-2
JP20 2-3 JP20 2-3
JP21 2-3 JP21 2-3
JP22 2-3 JP22 2-3
JP23 2-3 JP23 2-3
JP24 2-3 JP24 2-3
*/ */
ROM_START( bel ) ROM_START( bel )
ROM_REGION( 0x200000, REGION_CPU1, 0 ) // i960 program ROM_REGION( 0x200000, REGION_CPU1, 0 ) // i960 program

150
src/mame/drivers/namcos22.c
View File

@ -142,12 +142,12 @@
* *
* RR1.GAM (for Ridge Racer 1/2, Rave Racer) * RR1.GAM (for Ridge Racer 1/2, Rave Racer)
********************************************************************************************************** **********************************************************************************************************
* *
* Namco Super System 22 Hardware Overview (last updated 22-01-2006 at 1:30am) * Namco Super System 22 Hardware Overview (last updated 22-01-2006 at 1:30am)
* --------------------------------------- * ---------------------------------------
* *
* Note! This document will be updated from time to time when more dumps are available. * Note! This document will be updated from time to time when more dumps are available.
* *
* This document covers all the known Namco Super System 22 games, including.... * This document covers all the known Namco Super System 22 games, including....
* Air Combat 22 (C) Namco, 1995 * Air Combat 22 (C) Namco, 1995
* Alpine Racer 1 (C) Namco, 1995 * Alpine Racer 1 (C) Namco, 1995
@ -160,15 +160,15 @@
* Prop Cycle (C) Namco, 1996 * Prop Cycle (C) Namco, 1996
* Time Crisis (C) Namco, 1995 * Time Crisis (C) Namco, 1995
* !Tokyo Wars (C) Namco, 1996 * !Tokyo Wars (C) Namco, 1996
* *
* ! - denotes secured but not dumped yet. * ! - denotes secured but not dumped yet.
* * - denotes not dumped yet. If you can help with the remaining undumped SS22 games, * * - denotes not dumped yet. If you can help with the remaining undumped SS22 games,
* please contact http://www.mameworld.net/gurudumps/ * please contact http://www.mameworld.net/gurudumps/
* *
* The Namco Super System 22 System comprises 4 PCB's plugged into a motherboard. The motherboard contains only * The Namco Super System 22 System comprises 4 PCB's plugged into a motherboard. The motherboard contains only
* some slots and connectors. The 4 PCB's are housed in a metal box with a large fan on the side. The fan mostly cools * some slots and connectors. The 4 PCB's are housed in a metal box with a large fan on the side. The fan mostly cools
* the video board as these are known to run hot and commonly fail, especially now the system is 10 years+ old. * the video board as these are known to run hot and commonly fail, especially now the system is 10 years+ old.
* *
* CPU PCB - There are three known revisions of this PCB. Two of them have an extra connector for an * CPU PCB - There are three known revisions of this PCB. Two of them have an extra connector for an
* auxillary PCB. One of the others doesnt have that connector but they are otherwise identical. * auxillary PCB. One of the others doesnt have that connector but they are otherwise identical.
* All PCBs can be swapped to any game and it will work. However, ALL required IC's must be swapped. * All PCBs can be swapped to any game and it will work. However, ALL required IC's must be swapped.
@ -187,7 +187,7 @@
* The differences are very minor, just the amount of connectors on the PCB. The Mother PCB is swappable to * The differences are very minor, just the amount of connectors on the PCB. The Mother PCB is swappable to
* any game as long as the required connectors for that game are present on the PCB. (all dumped games tested * any game as long as the required connectors for that game are present on the PCB. (all dumped games tested
* and worked fine) * and worked fine)
* *
* Each game has a 2 or 3 digit letter code assigned to it. Then a number 1 or 2, Then a Rev. A/B/C/D which denotes the * Each game has a 2 or 3 digit letter code assigned to it. Then a number 1 or 2, Then a Rev. A/B/C/D which denotes the
* software revision. * software revision.
* The 1 denotes a Japanese version. 2 denotes a World version. So far there are no other numbers used other than 1 or 2. * The 1 denotes a Japanese version. 2 denotes a World version. So far there are no other numbers used other than 1 or 2.
@ -195,15 +195,15 @@
* There is one exception so far. The World version of Alpine Racer 2, which uses a World version DATA ROM, and also one * There is one exception so far. The World version of Alpine Racer 2, which uses a World version DATA ROM, and also one
* of the WAVE ROMs is a World version, but one Japanese WAVE ROM is also used. * of the WAVE ROMs is a World version, but one Japanese WAVE ROM is also used.
* See the CPU PCB, Program ROM Daughterboard and MROM PCB texts below for more details on ROM usage. * See the CPU PCB, Program ROM Daughterboard and MROM PCB texts below for more details on ROM usage.
* *
* CPU PCB * CPU PCB
* ------- * -------
* 1st Revision * 1st Revision
* SYSTEM SUPER22 CPU PCB 8646960102 (8646970102) * SYSTEM SUPER22 CPU PCB 8646960102 (8646970102)
* *
* 2nd Revision * 2nd Revision
* SYSTEM SUPER22 CPU(B) PCB 8646962600 (8646972600) * SYSTEM SUPER22 CPU(B) PCB 8646962600 (8646972600)
* *
* 3rd Revision * 3rd Revision
* SYSTEM SUPER22 CPU(B) PCB 8646962600 (8646972601) <-- very minor? * SYSTEM SUPER22 CPU(B) PCB 8646962600 (8646972601) <-- very minor?
* |--------------------------------------------------------------| * |--------------------------------------------------------------|
@ -237,7 +237,7 @@
* | WAVEB.1L LC78815M LC78815M | * | WAVEB.1L LC78815M LC78815M |
* |--------------------------------------------------------------| * |--------------------------------------------------------------|
* (logic chips omitted from the PCB layout) * (logic chips omitted from the PCB layout)
* *
* Notes: * Notes:
* J6 : Custom Namco connector for plug-in program ROM PCB * J6 : Custom Namco connector for plug-in program ROM PCB
* J11 : Custom Namco connector for optional plug-in WAVE ROM PCB (holds some SOP44 MASKROMs) * J11 : Custom Namco connector for optional plug-in WAVE ROM PCB (holds some SOP44 MASKROMs)
@ -285,7 +285,7 @@
* Prop Cycle = C428 * Prop Cycle = C428
* Time Crisis = C419 * Time Crisis = C419
* Tokyo Wars = * Tokyo Wars =
* *
* *1 : Unpopulated position for PAL16V8 (PLCC20) * *1 : Unpopulated position for PAL16V8 (PLCC20)
* *2 : Unpopulated position for Fujitsu MB86601 (QFP100) * *2 : Unpopulated position for Fujitsu MB86601 (QFP100)
* *3 : Unpopulated position for 32MHz OSC * *3 : Unpopulated position for 32MHz OSC
@ -303,7 +303,7 @@
* Prop Cycle 'PR1 DATA' * Prop Cycle 'PR1 DATA'
* Time Crisis 'TS1 DATA' * Time Crisis 'TS1 DATA'
* Tokyo Wars * Tokyo Wars
* *
* WAVEA.2L \ * WAVEA.2L \
* WAVEB.1L / : 16M/32M WAVE MASKROMs. If 32MBit DIP42, they're programmed in BYTE mode (DIP42/SOP44) * WAVEB.1L / : 16M/32M WAVE MASKROMs. If 32MBit DIP42, they're programmed in BYTE mode (DIP42/SOP44)
* Game Wave A Wave B Type * Game Wave A Wave B Type
@ -319,9 +319,9 @@
* Prop Cycle 'PR1 WAVE A', 'PR1 WAVE B' , both DIP42 32M MASKROM * Prop Cycle 'PR1 WAVE A', 'PR1 WAVE B' , both DIP42 32M MASKROM
* Time Crisis 'TS1 WAVE A', 'TS1 WAVE B' , WAVE A DIP42 32M MASKROM, WAVE B DIP42 16M MASKROM * Time Crisis 'TS1 WAVE A', 'TS1 WAVE B' , WAVE A DIP42 32M MASKROM, WAVE B DIP42 16M MASKROM
* Tokyo Wars * Tokyo Wars
* *
* *
* *
* PROGRAM ROM Daughterboard PCB * PROGRAM ROM Daughterboard PCB
* ----------------------------- * -----------------------------
* This PCB holds the main program ROMs. There is a small sticker on each PCB stating the game code and software revision. * This PCB holds the main program ROMs. There is a small sticker on each PCB stating the game code and software revision.
@ -329,7 +329,7 @@
* There are 4 known types of program daughterboards used on SS22 games (so far). The most common is the first type. * There are 4 known types of program daughterboards used on SS22 games (so far). The most common is the first type.
* The PCB is very small (approx 2" x 3") containing one custom connector and some FlashROMs, and a PAL (in some cases). * The PCB is very small (approx 2" x 3") containing one custom connector and some FlashROMs, and a PAL (in some cases).
* The ones that contain a PAL are approx 3" x 3". * The ones that contain a PAL are approx 3" x 3".
* *
* Type 1 * Type 1
* SYSTEM SUPER22 MPM(F) PCB 8646961600 (8646971600) * SYSTEM SUPER22 MPM(F) PCB 8646961600 (8646971600)
* |-------------------------| * |-------------------------|
@ -343,7 +343,7 @@
* |-------------------------| * |-------------------------|
* Notes: * Notes:
* ROMx: Intel E28F008SA 8MBit FlashROM (x4, TSOP40) * ROMx: Intel E28F008SA 8MBit FlashROM (x4, TSOP40)
* *
* This PCB is used on: * This PCB is used on:
* Game Software revision * Game Software revision
* ------------------------------- * -------------------------------
@ -353,7 +353,7 @@
* Cyber Cycles 'CB2 Ver.C' * Cyber Cycles 'CB2 Ver.C'
* Prop Cycle 'PR2 Ver.A' * Prop Cycle 'PR2 Ver.A'
* Time Crisis 'TS2 Ver.B' * Time Crisis 'TS2 Ver.B'
* *
* Type 2 * Type 2
* SYSTEM SUPER22 MPM(F16) PCB 8646962500 (8646972500) * SYSTEM SUPER22 MPM(F16) PCB 8646962500 (8646972500)
* |-------------------------| * |-------------------------|
@ -368,12 +368,12 @@
* |-------------------------| * |-------------------------|
* Notes: * Notes:
* ROMx: Intel E28F016SA 16MBit FlashROMs (x2, TSOP56) * ROMx: Intel E28F016SA 16MBit FlashROMs (x2, TSOP56)
* *
* This PCB is used on: * This PCB is used on:
* Game Software revision * Game Software revision
* ------------------------------- * -------------------------------
* Time Crisis 'TS2 Ver.A' * Time Crisis 'TS2 Ver.A'
* *
* Type 3 * Type 3
* SYSTEM SUPER22 MPM(F16X4) PCB 8646962901 (8646972901) * SYSTEM SUPER22 MPM(F16X4) PCB 8646962901 (8646972901)
* |-------------------------| * |-------------------------|
@ -391,12 +391,12 @@
* Notes: * Notes:
* ICx* : Intel E28F016SA 16MBit FlashROMs (x4, TSOP56) * ICx* : Intel E28F016SA 16MBit FlashROMs (x4, TSOP56)
* SS22P1B: PALCE16V8H (PLCC20, labelled 'SS22P1B') * SS22P1B: PALCE16V8H (PLCC20, labelled 'SS22P1B')
* *
* This PCB is used on: * This PCB is used on:
* Game Software revision * Game Software revision
* ------------------------------- * -------------------------------
* Alpine Racer 2 'ARS2 Ver.B' * Alpine Racer 2 'ARS2 Ver.B'
* *
* Type 4 * Type 4
* SYSTEM SUPER22 MPM(F16X4F) PCB 8646963500 (8646973500) * SYSTEM SUPER22 MPM(F16X4F) PCB 8646963500 (8646973500)
* |-------------------------| * |-------------------------|
@ -421,15 +421,15 @@
* That pin traces to pin 6 (OUTPUT Y) of a 74F08 at 15F on the CPU board * That pin traces to pin 6 (OUTPUT Y) of a 74F08 at 15F on the CPU board
* Pins 4 (INPUT A) & 5 (INPUT B) of the 74F08 at 15F trace to Namco custom * Pins 4 (INPUT A) & 5 (INPUT B) of the 74F08 at 15F trace to Namco custom
* IC C383 pins 53 (A INPUT) & 52 (B INPUT) * IC C383 pins 53 (A INPUT) & 52 (B INPUT)
* *
* *
* This PCB is used on: * This PCB is used on:
* Game Software revision * Game Software revision
* ------------------------------- * -------------------------------
* Alpine Surfer 'AF2 Ver.A' * Alpine Surfer 'AF2 Ver.A'
* *
* *
* *
* Auxillary PCB (connector JC410 on the CPU PCB is used only on Time Crisis so far) * Auxillary PCB (connector JC410 on the CPU PCB is used only on Time Crisis so far)
* ------------- * -------------
* V159 GUN POINT PCB 244790102 (2447970102) * V159 GUN POINT PCB 244790102 (2447970102)
@ -456,9 +456,9 @@
* J1 : Connector joining Gun PCB to a connector on the metal box (which joins to the gun interface PCB in the * J1 : Connector joining Gun PCB to a connector on the metal box (which joins to the gun interface PCB in the
* cab which supplies 24V for the soleniod in the guns) * cab which supplies 24V for the soleniod in the guns)
* J2 : Connector joining to the CPU PCB (to JC410) * J2 : Connector joining to the CPU PCB (to JC410)
* *
* *
* *
* DSP PCB * DSP PCB
* ------- * -------
* SYSTEM SUPER22 DSP PCB 8646960302 (8646970302) * SYSTEM SUPER22 DSP PCB 8646960302 (8646970302)
@ -493,7 +493,7 @@
* | |-----| |---------| | * | |-----| |---------| |
* |--------------------------------------------------------------| * |--------------------------------------------------------------|
* (logic chips omitted from the PCB layout) * (logic chips omitted from the PCB layout)
* *
* Notes: * Notes:
* JD3 : Custom Namco connector joining this PCB to the MROM PCB with a special flat cable known as a * JD3 : Custom Namco connector joining this PCB to the MROM PCB with a special flat cable known as a
* 'DHD harness' * 'DHD harness'
@ -515,9 +515,9 @@
* SS22D4B : PALCE 16V8H (PLCC20, labelled 'SS22D4B') * SS22D4B : PALCE 16V8H (PLCC20, labelled 'SS22D4B')
* SS22D5 : PALCE 16V8H (PLCC20, labelled 'SS22D5') * SS22D5 : PALCE 16V8H (PLCC20, labelled 'SS22D5')
* LEDS : 8 red LEDs flash (in various pretty patterns) when the DSP PCB is active. * LEDS : 8 red LEDs flash (in various pretty patterns) when the DSP PCB is active.
* *
* *
* *
* ROM PCB * ROM PCB
* ------- * -------
* SYSTEM SUPER22 MROM PCB 8646960400 (8646970400) * SYSTEM SUPER22 MROM PCB 8646960400 (8646970400)
@ -552,11 +552,11 @@
* | SCG6.1L SCG6.1F | * | SCG6.1L SCG6.1F |
* |--------------------------------------------------------------| * |--------------------------------------------------------------|
* (logic chips omitted from the PCB layout) * (logic chips omitted from the PCB layout)
* *
* Notes: * Notes:
* Namco SS22 MROM PCBs have 2 identical sets of CG*, SCG* and CCR-L/CCR-H ROMs on the PCB. * Namco SS22 MROM PCBs have 2 identical sets of CG*, SCG* and CCR-L/CCR-H ROMs on the PCB.
* The Japanese region code '1' is appended to all game codes on all MROMs. * The Japanese region code '1' is appended to all game codes on all MROMs.
* *
* JR3, JR4 : Custom Namco connector joining this PCB to the VIDEO & DSP PCBs with a special flat cable known * JR3, JR4 : Custom Namco connector joining this PCB to the VIDEO & DSP PCBs with a special flat cable known
* as a 'DHD harness' * as a 'DHD harness'
* SS22M1 : PALCE 16V8H (PLCC20, labelled 'SS22M1') * SS22M1 : PALCE 16V8H (PLCC20, labelled 'SS22M1')
@ -568,7 +568,7 @@
* JP7, JP8, JP9: Jumpers to configure SCG* ROMs. Hardwired to '16M' on the PCB. Alt. setting '32M' * JP7, JP8, JP9: Jumpers to configure SCG* ROMs. Hardwired to '16M' on the PCB. Alt. setting '32M'
* JP10, JP11, JP12: Jumpers to configure SCG* ROMs. Hardwired to '16M' on the PCB. Alt. setting '32M' * JP10, JP11, JP12: Jumpers to configure SCG* ROMs. Hardwired to '16M' on the PCB. Alt. setting '32M'
* JP13 : Jumper to configure PTR* ROMs. Hardwired to '4M' on the PCB. Alt. setting '8M' * JP13 : Jumper to configure PTR* ROMs. Hardwired to '4M' on the PCB. Alt. setting '8M'
* *
* Game ROMs populated * Game ROMs populated
* --------------------------------------------------------- * ---------------------------------------------------------
* Air Combat 22 ACS1CCRH.5B, ACS1CCRH.1D 4M SOP32 * Air Combat 22 ACS1CCRH.5B, ACS1CCRH.1D 4M SOP32
@ -595,7 +595,7 @@
* ACS1PTRL1.16K " * ACS1PTRL1.16K "
* ACS1PTRL2.15K " * ACS1PTRL2.15K "
* ACS1PTRL3.14K " * ACS1PTRL3.14K "
* *
* Alpine Racer 1 AR1CCRH.5B, AR1CCRH.1D 4M SOP32 * Alpine Racer 1 AR1CCRH.5B, AR1CCRH.1D 4M SOP32
* AR1CCRL.7B, AR1CCRL.3D 16M SOP44 * AR1CCRL.7B, AR1CCRL.3D 16M SOP44
* AR1CG0.12B, AR1CG0.8D " * AR1CG0.12B, AR1CG0.8D "
@ -620,7 +620,7 @@
* AR1PTRL1.16K " * AR1PTRL1.16K "
* AR1PTRL2.15K " * AR1PTRL2.15K "
* AR1PTRL3.14K " * AR1PTRL3.14K "
* *
* Alpine Racer 2 ARS1CCRH.5B, ARS1CCRH.1D 4M SOP32 * Alpine Racer 2 ARS1CCRH.5B, ARS1CCRH.1D 4M SOP32
* ARS1CCRL.7B, ARS1CCRL.3D 16M SOP44 * ARS1CCRL.7B, ARS1CCRL.3D 16M SOP44
* ARS1CG0.12B, ARS1CG0.8D " * ARS1CG0.12B, ARS1CG0.8D "
@ -642,7 +642,7 @@
* ARS1PTRL1.16K " * ARS1PTRL1.16K "
* ARS1PTRL2.15K " * ARS1PTRL2.15K "
* ARS1PTRL3.14K " * ARS1PTRL3.14K "
* *
* Alpine Surfer AF1CCRH.5B, AF1CCRH.1D 4M SOP32 * Alpine Surfer AF1CCRH.5B, AF1CCRH.1D 4M SOP32
* AF1CCRL.7B, AF1CCRL.3D 16M SOP44 * AF1CCRL.7B, AF1CCRL.3D 16M SOP44
* AF1CG0.12B, AF1CG0.8D " * AF1CG0.12B, AF1CG0.8D "
@ -657,11 +657,11 @@
* AF1PTRM1.16J " * AF1PTRM1.16J "
* AF1PTRL0.18K " * AF1PTRL0.18K "
* AF1PTRL1.16K " * AF1PTRL1.16K "
* *
* Aqua Jet N/A * Aqua Jet N/A
* *
* Armidillo Racing N/A * Armidillo Racing N/A
* *
* Cyber Cycles CB1CCRH.5B, CB1CCRH.1D 4M SOP32 * Cyber Cycles CB1CCRH.5B, CB1CCRH.1D 4M SOP32
* CB1CCRL.7B, CB1CCRL.3D 16M SOP44 * CB1CCRL.7B, CB1CCRL.3D 16M SOP44
* CB1CG0.12B, CB1CG0.8D " * CB1CG0.12B, CB1CG0.8D "
@ -685,9 +685,9 @@
* CB1PTRL1.16K " * CB1PTRL1.16K "
* CB1PTRL2.15K " * CB1PTRL2.15K "
* CB1PTRL3.14K " * CB1PTRL3.14K "
* *
* Dirt Dash N/A * Dirt Dash N/A
* *
* Prop Cycle PR1CCRH.5B, PR1CCRH.1D 4M SOP32 * Prop Cycle PR1CCRH.5B, PR1CCRH.1D 4M SOP32
* PR1CCRL.7B, PR1CCRL.3D 16M SOP44 * PR1CCRL.7B, PR1CCRL.3D 16M SOP44
* PR1CG0.12B, PR1CG0.8D " * PR1CG0.12B, PR1CG0.8D "
@ -709,7 +709,7 @@
* PR1PTRL0.18K " * PR1PTRL0.18K "
* PR1PTRL1.16K " * PR1PTRL1.16K "
* PR1PTRL2.15K " * PR1PTRL2.15K "
* *
* Time Crisis TS1CCRH.5B, TS1CCRH.1D 4M SOP32 * Time Crisis TS1CCRH.5B, TS1CCRH.1D 4M SOP32
* TS1CCRL.7B, TS1CCRL.3D 16M SOP44 * TS1CCRL.7B, TS1CCRL.3D 16M SOP44
* TS1CG0.12B, TS1CG0.8D " * TS1CG0.12B, TS1CG0.8D "
@ -735,19 +735,19 @@
* TS1PTRL0.18K " * TS1PTRL0.18K "
* TS1PTRL1.16K " * TS1PTRL1.16K "
* TS1PTRL2.15K " * TS1PTRL2.15K "
* *
* Tokyo Wars N/A * Tokyo Wars N/A
* *
* *
* *
* VIDEO PCB * VIDEO PCB
* --------- * ---------
* 1st Revision * 1st Revision
* SYSTEM SUPER22 VIDEO 8646960204 (8646970204) * SYSTEM SUPER22 VIDEO 8646960204 (8646970204)
* *
* 2nd Revision * 2nd Revision
* SYSTEM SUPER22 VIDEO(B) 8646961200 (8646971200) * SYSTEM SUPER22 VIDEO(B) 8646961200 (8646971200)
* *
* 3rd Revision (PCB layout shown below) * 3rd Revision (PCB layout shown below)
* SYSTEM SUPER22 VIDEO(C) 8646962700 (8646972700) * SYSTEM SUPER22 VIDEO(C) 8646962700 (8646972700)
* |--------------------------------------------------------------| * |--------------------------------------------------------------|
@ -781,7 +781,7 @@
* | |---------| |---------| N341256 CXD1178Q | * | |---------| |---------| N341256 CXD1178Q |
* |--------------------------------------------------------------| * |--------------------------------------------------------------|
* (logic chips omitted from the PCB layout) * (logic chips omitted from the PCB layout)
* *
* Notes: * Notes:
* JV3 : Custom Namco connector joining this PCB to the MROM PCB with a special flat cable known * JV3 : Custom Namco connector joining this PCB to the MROM PCB with a special flat cable known
* as a 'DHD harness' * as a 'DHD harness'
@ -809,16 +809,16 @@
* video faults on Namco Super System 22 PCBs. * video faults on Namco Super System 22 PCBs.
* (Second reasons for video faults are most likely attributed * (Second reasons for video faults are most likely attributed
* to failure of RAM on this PCB) * to failure of RAM on this PCB)
* *
* *
* Motherboard PCB * Motherboard PCB
* --------------- * ---------------
* 1st Revision * 1st Revision
* SYSTEM SUPER22 MOTHER PCB 8646960602 (8646970602) * SYSTEM SUPER22 MOTHER PCB 8646960602 (8646970602)
* *
* 2nd Revision * 2nd Revision
* SYSTEM SUPER22 MOTHER(B) PCB (number not known) * SYSTEM SUPER22 MOTHER(B) PCB (number not known)
* *
* 3rd Revision * 3rd Revision
* SYSTEM SUPER22 MOTHER(C) PCB 8646960602 (8646970602) * SYSTEM SUPER22 MOTHER(C) PCB 8646960602 (8646970602)
* |------------------------------------------------------------------| * |------------------------------------------------------------------|
@ -841,12 +841,12 @@
* Notes: * Notes:
* IC1 : LB1233 (DIP8) * IC1 : LB1233 (DIP8)
* IC2, IC3: LB1235 (DIP8) * IC2, IC3: LB1235 (DIP8)
* *
* JC1, JC2: Connectors to plug in CPU PCB * JC1, JC2: Connectors to plug in CPU PCB
* JD1, JD2: Connectors to plug in DSP PCB * JD1, JD2: Connectors to plug in DSP PCB
* JR1 : Connector to plug in MROM PCB * JR1 : Connector to plug in MROM PCB
* JV1, JV2: Connectors to plug in VIDEO PCB * JV1, JV2: Connectors to plug in VIDEO PCB
* *
* J1 : 9 pin power input socket Pin Use * J1 : 9 pin power input socket Pin Use
* ----------- * -----------
* 1 +5V * 1 +5V
@ -858,7 +858,7 @@
* 7 Ground * 7 Ground
* 8 NC * 8 NC
* 9 +12V * 9 +12V
* *
* J2 : 9 pin link connector Pin Use * J2 : 9 pin link connector Pin Use
* -------------- * --------------
* 1 Ring In+ * 1 Ring In+
@ -870,7 +870,7 @@
* 7 /TXD (NC) * 7 /TXD (NC)
* 8 GND (NC) * 8 GND (NC)
* 9 +5V (NC) * 9 +5V (NC)
* *
* J3 : 9 pin socket Pin Use * J3 : 9 pin socket Pin Use
* ------------------- * -------------------
* 1 Service Credit * 1 Service Credit
@ -882,7 +882,7 @@
* 7 Ground * 7 Ground
* 8 Coin Sw * 8 Coin Sw
* 9 NC * 9 NC
* *
* J4 : 8 pin connector Pin Use * J4 : 8 pin connector Pin Use
* ------------------------------------- * -------------------------------------
* 1 Start * 1 Start
@ -893,7 +893,7 @@
* 6 NC * 6 NC
* 7 Ground * 7 Ground
* 8 Ground * 8 Ground
* *
* J5 : 15 pin socket Pin Use * J5 : 15 pin socket Pin Use
* --------------- * ---------------
* 1 Relay1 * 1 Relay1
@ -911,7 +911,7 @@
* 13 +12V * 13 +12V
* 14 +5V * 14 +5V
* 15 NC * 15 NC
* *
* J6 : 12 pin audio output connector Pin Use * J6 : 12 pin audio output connector Pin Use
* ---------- * ----------
* 1 SPKL+ * 1 SPKL+
@ -926,7 +926,7 @@
* 10 NC * 10 NC
* 11 NC * 11 NC
* 12 NC * 12 NC
* *
* J7 : 12 pin analog controls socket Pin Use * J7 : 12 pin analog controls socket Pin Use
* --------------------------- * ---------------------------
* 1 +5V * 1 +5V
@ -941,9 +941,9 @@
* 10 NC * 10 NC
* 11 NC * 11 NC
* 12 NC * 12 NC
* *
* J8 : 10 pin connector (not used?) * J8 : 10 pin connector (not used?)
* *
* J9 : 6 pin video output socket Pin Use * J9 : 6 pin video output socket Pin Use
* --------- * ---------
* 1 Red * 1 Red
@ -952,11 +952,11 @@
* 4 Composite Sync (VSync 15kHz interlaced) * 4 Composite Sync (VSync 15kHz interlaced)
* 5 Ground * 5 Ground
* 6 NC * 6 NC
* *
* J10: 16 pin flat cable connector (only populated on Mother(C) PCB, use not known) * J10: 16 pin flat cable connector (only populated on Mother(C) PCB, use not known)
* *
* *
* *
* AMP PCB * AMP PCB
* ------- * -------
* SYSTEM SUPER22 AMP(4) PCB 8647960100 (8647970100) (sticker 'AMP(2) PCB 8647961100') * SYSTEM SUPER22 AMP(4) PCB 8647960100 (8647970100) (sticker 'AMP(2) PCB 8647961100')
@ -971,14 +971,14 @@
* 1 +12V * 1 +12V
* 2 Ground * 2 Ground
* 3 NC * 3 NC
* *
* J2 : 4 pin dual speaker output socket Pin Use * J2 : 4 pin dual speaker output socket Pin Use
* --------- * ---------
* 1 SP1+ * 1 SP1+
* 2 SP1- * 2 SP1-
* 3 SP2+ * 3 SP2+
* 4 SP2- * 4 SP2-
* *
* J3 : 8 pin sound data input connector from Mother PCB J6 Pin Use * J3 : 8 pin sound data input connector from Mother PCB J6 Pin Use
* ---------- * ----------
* 1 SPKL+ * 1 SPKL+
@ -989,7 +989,7 @@
* 6 NC * 6 NC
* 7 NC * 7 NC
* 8 NC * 8 NC
* *
* *1 : Unpopulated position for a 2nd LA4705 Power Amp * *1 : Unpopulated position for a 2nd LA4705 Power Amp
* *2 : J4 - Unpopulated position for another 4 pin dual speaker output socket * *2 : J4 - Unpopulated position for another 4 pin dual speaker output socket
* J5 : 2 pin connector used for sound mute Pin Use * J5 : 2 pin connector used for sound mute Pin Use

2
src/mame/video/ampoker2.c
View File

@ -29,7 +29,7 @@
Resistor Network Resistor Network
---------------- ----------------
The following diagram is related to taiwanese and argentine PCBs. The following diagram is related to taiwanese and argentine PCBs.

2
src/mame/video/xevious.c
View File

@ -460,7 +460,7 @@ static void draw_sprites(running_machine *machine, bitmap_t *bitmap,const rectan
flipy = !flipy; flipy = !flipy;
sy += 48; sy += 48;
} }
transmask = colortable_get_transpen_mask(machine->colortable, machine->gfx[bank], color, 0x80); transmask = colortable_get_transpen_mask(machine->colortable, machine->gfx[bank], color, 0x80);
if (spriteram_3[offs] & 2) /* double height (?) */ if (spriteram_3[offs] & 2) /* double height (?) */