Sprinter/mame
2
0
Fork 0
mirror of https://github.com/holub/mame synced 2025-06-01 10:31:48 +03:00
Code Issues Actions 3 Packages Projects Releases Wiki Activity

Groundworks for TMS320C82 core.

Browse Source
This commit is contained in:
Ville Linde 2013-07-15 19:44:38 +00:00
parent 2ee1fc4422
commit c85b5c9130
6 changed files with 587 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
.gitattributes vendored
View File

@ -875,6 +875,9 @@ src/emu/cpu/tms32051/32051ops.h svneol=native#text/plain
src/emu/cpu/tms32051/dis32051.c svneol=native#text/plain
src/emu/cpu/tms32051/tms32051.c svneol=native#text/plain
src/emu/cpu/tms32051/tms32051.h svneol=native#text/plain
src/emu/cpu/tms32082/dis32082.c svneol=native#text/plain
src/emu/cpu/tms32082/tms32082.c svneol=native#text/plain
src/emu/cpu/tms32082/tms32082.h svneol=native#text/plain
src/emu/cpu/tms34010/34010dsm.c svneol=native#text/plain
src/emu/cpu/tms34010/34010fld.c svneol=native#text/plain
src/emu/cpu/tms34010/34010gfx.c svneol=native#text/plain

16
src/emu/cpu/cpu.mak
View File

@ -1992,6 +1992,22 @@ $(CPUOBJ)/tms32051/tms32051.o: $(CPUSRC)/tms32051/tms32051.c \
#-------------------------------------------------
# Texas Instruments TMS3208x DSP
#@src/emu/cpu/tms32082/tms32082.h,CPUS += TMS32082_MP
#-------------------------------------------------
ifneq ($(filter TMS32082,$(CPUS)),)
OBJDIRS += $(CPUOBJ)/tms32082
CPUOBJS += $(CPUOBJ)/tms32082/tms32082.o
DASMOBJS += $(CPUOBJ)/tms32082/dis32082.o
endif
$(CPUOBJ)/tms32082/tms32082.o: $(CPUSRC)/tms32082/tms32082.c \
$(CPUSRC)/tms32082/tms32082.h
#-------------------------------------------------
# Texas Instruments TMS57002 DSP
#@src/emu/cpu/tms57002/tms57002.h,CPUS += TMS57002

349
src/emu/cpu/tms32082/dis32082.c Normal file
View File

@ -0,0 +1,349 @@
// TMS32082 MP/PP Disassembler
#include "emu.h"
#define SIMM15(v) (INT32)((v & 0x4000) ? (v | 0xffffe000) : (v))
#define UIMM15(v) (v)
static const char *BCND_CONDITION[32] =
{
"nev.b", "gt0.b", "eq0.b", "ge0.b", "lt0.b", "ne0.b", "le0.b", "alw.b",
"nev.h", "gt0.h", "eq0.h", "ge0.h", "lt0.h", "ne0.h", "le0.h", "alw.h",
"nev.w", "gt0.w", "eq0.w", "ge0.w", "lt0.w", "ne0.w", "le0.w", "alw.w",
"nev.d", "gt0.d", "eq0.d", "ge0.d", "lt0.d", "ne0.d", "le0.d", "alw.d",
};
static char *output;
static const UINT8 *opdata;
static int opbytes;
static void ATTR_PRINTF(1,2) print(const char *fmt, ...)
{
va_list vl;
va_start(vl, fmt);
output += vsprintf(output, fmt, vl);
va_end(vl);
}
static UINT32 fetch(void)
{
UINT32 d = ((UINT32)(opdata[0]) << 24) | ((UINT32)(opdata[1]) << 16) | ((UINT32)(opdata[2]) << 8) | opdata[3];
opdata += 4;
opbytes += 4;
return d;
}
static offs_t tms32082_disasm_mp(char *buffer, offs_t pc, const UINT8 *oprom)
{
output = buffer;
opdata = oprom;
opbytes = 0;
UINT32 flags = 0;
UINT32 op = fetch();
int rd = (op >> 27) & 0x1f;
int link = rd;
int bitnum = rd;
int rs = (op >> 22) & 0x1f;
int endmask = (op >> 5) & 0x1f;
int rotate = (op & 0x1f);
int src1 = rotate;
UINT32 uimm15 = op & 0x7fff;
switch ((op >> 20) & 3)
{
case 0: case 1: case 2: // Short immediate
{
int subop = (op >> 15) & 0x7f;
switch (subop)
{
case 0x00: print("illop0 "); break;
case 0x01: print("trap %d", UIMM15(uimm15)); break;
case 0x02: print("cmnd 0x%04X", UIMM15(uimm15)); break;
case 0x04: print("rdcr R%d, CR 0x%04X", rd, UIMM15(uimm15)); break;
case 0x05: print("swcr CR 0x%04X, R%d, R%d", UIMM15(uimm15), rs, rd); break;
case 0x06: print("brcr 0x%04X", UIMM15(uimm15)); break;
case 0x08: print("shift.dz %d, %d, R%d, R%d", rotate, endmask, rs, rd); break;
case 0x09: print("shift.dm %d, %d, R%d, R%d", rotate, endmask, rs, rd); break;
case 0x0a: print("shift.ds %d, %d, R%d, R%d", rotate, endmask, rs, rd); break;
case 0x0b: print("shift.ez %d, %d, R%d, R%d", rotate, endmask, rs, rd); break;
case 0x0c: print("shift.em %d, %d, R%d, R%d", rotate, endmask, rs, rd); break;
case 0x0d: print("shift.es %d, %d, R%d, R%d", rotate, endmask, rs, rd); break;
case 0x0e: print("shift.iz %d, %d, R%d, R%d", rotate, endmask, rs, rd); break;
case 0x0f: print("shift.im %d, %d, R%d, R%d", rotate, endmask, rs, rd); break;
case 0x10: print("and 0x%04X, R%d, R%d", UIMM15(uimm15), rs, rd); break;
case 0x12: print("and.tf 0x%04X, R%d, R%d", UIMM15(uimm15), rs, rd); break;
case 0x14: print("and.ft 0x%04X, R%d, R%d", UIMM15(uimm15), rs, rd); break;
case 0x16: print("xor 0x%04X, R%d, R%d", UIMM15(uimm15), rs, rd); break;
case 0x17: print("or 0x%04X, R%d, R%d", UIMM15(uimm15), rs, rd); break;
case 0x18: print("and.ff 0x%04X, R%d, R%d", UIMM15(uimm15), rs, rd); break;
case 0x19: print("xnor 0x%04X, R%d, R%d", UIMM15(uimm15), rs, rd); break;
case 0x1b: print("or.tf 0x%04X, R%d, R%d", UIMM15(uimm15), rs, rd); break;
case 0x1d: print("or.ft 0x%04X, R%d, R%d", UIMM15(uimm15), rs, rd); break;
case 0x1e: print("or.ff 0x%04X, R%d, R%d", UIMM15(uimm15), rs, rd); break;
case 0x24: case 0x20:
print("ld.b 0x%04X(R%d), R%d", UIMM15(uimm15), rs, rd);
break;
case 0x25: case 0x21:
print("ld.h 0x%04X(R%d), R%d", UIMM15(uimm15), rs, rd);
break;
case 0x26: case 0x22:
print("ld 0x%04X(R%d), R%d", UIMM15(uimm15), rs, rd);
break;
case 0x27: case 0x23:
print("ld.d 0x%04X(R%d), R%d", UIMM15(uimm15), rs, rd);
break;
case 0x2c: case 0x28:
print("ld.ub 0x%04X(R%d), R%d", UIMM15(uimm15), rs, rd);
break;
case 0x2d: case 0x29:
print("ld.uh 0x%04X(R%d), R%d", UIMM15(uimm15), rs, rd);
break;
case 0x34: case 0x30:
print("st.b R%d, 0x%04X(R%d)", rd, UIMM15(uimm15), rs);
break;
case 0x35: case 0x31:
print("st.h R%d, 0x%04X(R%d)", rd, UIMM15(uimm15), rs);
break;
case 0x36: case 0x32:
print("st R%d, 0x%04X(R%d)", rd, UIMM15(uimm15), rs);
break;
case 0x37: case 0x33:
print("st.d R%d, 0x%04X(R%d)", rd, UIMM15(uimm15), rs);
break;
case 0x40: print("bsr 0x%08X, R%d", pc + (SIMM15(uimm15) * 4), link); break;
case 0x41: print("bsr.a 0x%08X, R%d", pc + (SIMM15(uimm15) * 4), link); break;
case 0x44: print("jsr 0x%04X(R%d), R%d", SIMM15(uimm15), rs, link); break;
case 0x45: print("jsr.a 0x%04X(R%d), R%d", SIMM15(uimm15), rs, link); break;
case 0x48: print("bbz 0x%08X, R%d, #%d", pc + (SIMM15(uimm15) * 4), rs, bitnum); break;
case 0x49: print("bbz.a 0x%08X, R%d, #%d", pc + (SIMM15(uimm15) * 4), rs, bitnum); break;
case 0x4a: print("bbo 0x%08X, R%d, #%d", pc + (SIMM15(uimm15) * 4), rs, bitnum); break;
case 0x4b: print("bbo.a 0x%08X, R%d, #%d", pc + (SIMM15(uimm15) * 4), rs, bitnum); break;
case 0x4c: print("bcnd 0x%08X, R%d, %s", pc + (SIMM15(uimm15) * 4), rs, BCND_CONDITION[rd]); break;
case 0x4d: print("bcnd.a 0x%08X, R%d, %s", pc + (SIMM15(uimm15) * 4), rs, BCND_CONDITION[rd]); break;
case 0x50: print("cmp 0x%08X, R%d, R%d", SIMM15(uimm15), rs, rd); break;
case 0x58: print("add 0x%08X, R%d, R%d", SIMM15(uimm15), rs, rd); break;
case 0x59: print("addu 0x%08X, R%d, R%d", SIMM15(uimm15), rs, rd); break;
case 0x5a: print("sub 0x%08X, R%d, R%d", SIMM15(uimm15), rs, rd); break;
case 0x5b: print("subu 0x%08X, R%d, R%d", SIMM15(uimm15), rs, rd); break;
}
break;
}
case 3: // Register / Long immediate
{
int subop = (op >> 12) & 0xff;
UINT32 imm32 = 0;
if (op & (1 << 12)) // fetch 32-bit immediate if needed
imm32 = fetch();
switch (subop)
{
case 0x02: print("trap %d", src1); break;
case 0x03: print("trap %d", imm32); break;
case 0x04: print("cmnd R%d", src1); break;
case 0x05: print("cmnd 0x%08X", imm32); break;
case 0x08: print("rdcr R%d, R%d", rd, src1); break;
case 0x09: print("rdcr R%d, 0x%08X", rd, imm32); break;
case 0x0a: print("swcr R%d, R%d, R%d", src1, rs, rd); break;
case 0x0b: print("swcr 0x%08X, R%d, R%d", imm32, rs, rd); break;
case 0x0c: print("brcr R%d", src1); break;
case 0x0d: print("brcr 0x%08X", imm32); break;
case 0x10: print("shift.dz %d, %d, R%d, R%d", rotate, endmask, rs, rd); break;
case 0x12: print("shift.dm %d, %d, R%d, R%d", rotate, endmask, rs, rd); break;
case 0x14: print("shift.ds %d, %d, R%d, R%d", rotate, endmask, rs, rd); break;
case 0x16: print("shift.ez %d, %d, R%d, R%d", rotate, endmask, rs, rd); break;
case 0x18: print("shift.em %d, %d, R%d, R%d", rotate, endmask, rs, rd); break;
case 0x1a: print("shift.es %d, %d, R%d, R%d", rotate, endmask, rs, rd); break;
case 0x1c: print("shift.iz %d, %d, R%d, R%d", rotate, endmask, rs, rd); break;
case 0x1e: print("shift.im %d, %d, R%d, R%d", rotate, endmask, rs, rd); break;
case 0x22: print("and R%d, R%d, R%d", src1, rs, rd); break;
case 0x23: print("and 0x%08X, R%d, R%d", imm32, rs, rd); break;
case 0x24: print("and.tf R%d, R%d, R%d", src1, rs, rd); break;
case 0x25: print("and.tf 0x%08X, R%d, R%d", imm32, rs, rd); break;
case 0x28: print("and.ft R%d, R%d, R%d", src1, rs, rd); break;
case 0x29: print("and.ft 0x%08X, R%d, R%d", imm32, rs, rd); break;
case 0x2c: print("xor R%d, R%d, R%d", src1, rs, rd); break;
case 0x2d: print("xor 0x%08X, R%d, R%d", imm32, rs, rd); break;
case 0x2e: print("or R%d, R%d, R%d", src1, rs, rd); break;
case 0x2f: print("or 0x%08X, R%d, R%d", imm32, rs, rd); break;
case 0x30: print("and.ff R%d, R%d, R%d", src1, rs, rd); break;
case 0x31: print("and.ff 0x%08X, R%d, R%d", imm32, rs, rd); break;
case 0x32: print("xnor R%d, R%d, R%d", src1, rs, rd); break;
case 0x33: print("xnor 0x%08X, R%d, R%d", imm32, rs, rd); break;
case 0x36: print("or.tf R%d, R%d, R%d", src1, rs, rd); break;
case 0x37: print("or.tf 0x%08X, R%d, R%d", imm32, rs, rd); break;
case 0x3a: print("or.ft R%d, R%d, R%d", src1, rs, rd); break;
case 0x3b: print("or.ft 0x%08X, R%d, R%d", imm32, rs, rd); break;
case 0x3c: print("or.ff R%d, R%d, R%d", src1, rs, rd); break;
case 0x3d: print("or.ff 0x%08X, R%d, R%d", imm32, rs, rd); break;
case 0x48: case 0x40:
print("ld.b R%d(R%d), R%d", src1, rs, rd);
break;
case 0x49: case 0x41:
print("ld.b 0x%08X(R%d), R%d", imm32, rs, rd);
break;
case 0x4a: case 0x42:
print("ld.h R%d(R%d), R%d", src1, rs, rd);
break;
case 0x4b: case 0x43:
print("ld.h 0x%08X(R%d), R%d", imm32, rs, rd);
break;
case 0x4c: case 0x44:
print("ld R%d(R%d), R%d", src1, rs, rd);
break;
case 0x4d: case 0x45:
print("ld 0x%08X(R%d), R%d", imm32, rs, rd);
break;
case 0x4e: case 0x46:
print("ld.d R%d(R%d), R%d", src1, rs, rd);
break;
case 0x4f: case 0x47:
print("ld.d 0x%08X(R%d), R%d", imm32, rs, rd);
break;
case 0x58: case 0x50:
print("ld.ub R%d(R%d), R%d", src1, rs, rd);
break;
case 0x59: case 0x51:
print("ld.ub 0x%08X(R%d), R%d", imm32, rs, rd);
break;
case 0x5a: case 0x52:
print("ld.uh R%d(R%d), R%d", src1, rs, rd);
break;
case 0x5b: case 0x53:
print("ld.uh 0x%08X(R%d), R%d", imm32, rs, rd);
break;
case 0x68: case 0x60:
print("st.b R%d, R%d(R%d)", rd, src1, rs);
break;
case 0x69: case 0x61:
print("st.b R%d, 0x%08X(R%d)", rd, imm32, rs);
break;
case 0x6a: case 0x62:
print("st.h R%d, R%d(R%d)", rd, src1, rs);
break;
case 0x6b: case 0x63:
print("st.h R%d, 0x%08X(R%d)", rd, imm32, rs);
break;
case 0x6c: case 0x64:
print("st R%d, R%d(R%d)", rd, src1, rs);
break;
case 0x6d: case 0x65:
print("st R%d, 0x%08X(R%d)", rd, imm32, rs);
break;
case 0x6e: case 0x66:
print("st.d R%d, R%d(R%d)", rd, src1, rs);
break;
case 0x6f: case 0x67:
print("st.d R%d, 0x%08X(R%d)", rd, imm32, rs);
break;
case 0x78: case 0x70:
print("dcache R%d(R%d)", src1, rs);
break;
case 0x79: case 0x71:
print("dcache 0x%08X(R%d)", imm32, rs);
break;
case 0x80: print("bsr R%d, R%d", src1, link); break;
case 0x81: print("bsr 0x%08X, R%d", imm32, link); break;
case 0x82: print("bsr.a R%d, R%d", src1, rd); break;
case 0x83: print("bsr.a 0x%08X, R%d", imm32, link); break;
case 0x88: print("jsr R%d, R%d", src1, link); break;
case 0x89: print("jsr 0x%08X, R%d", imm32, link); break;
case 0x8a: print("jsr.a R%d, R%d", src1, link); break;
case 0x8b: print("jsr.a 0x%08X, R%d", imm32, link); break;
case 0x90: print("bbz R%d, R%d, #%d", src1, rs, bitnum); break;
case 0x91: print("bbz 0x%08X, R%d, #%d", imm32, rs, bitnum); break;
case 0x92: print("bbz.a R%d, R%d, #%d", src1, rs, bitnum); break;
case 0x93: print("bbz.a 0x%08X, R%d, #%d", imm32, rs, bitnum); break;
case 0x94: print("bbo R%d, R%d, #%d", src1, rs, bitnum); break;
case 0x95: print("bbo 0x%08X, R%d, #%d", imm32, rs, bitnum); break;
case 0x96: print("bbo.a R%d, R%d, #%d", src1, rs, bitnum); break;
case 0x97: print("bbo.a 0x%08X, R%d, #%d", imm32, rs, bitnum); break;
case 0x98: print("bcnd R%d, R%d, %s", src1, rs, BCND_CONDITION[rd]); break;
case 0x99: print("bcnd 0x%08X, R%d, %s", imm32, rs, BCND_CONDITION[rd]); break;
case 0x9a: print("bcnd.a R%d, R%d, %s", src1, rs, BCND_CONDITION[rd]); break;
case 0x9b: print("bcnd.a 0x%08X, R%d, %s", imm32, rs, BCND_CONDITION[rd]); break;
case 0xa0: print("cmp R%d, R%d, R%d", src1, rs, rd); break;
case 0xa1: print("cmp 0x%08X, R%d, R%d", imm32, rs, rd); break;
case 0xb0: print("add R%d, R%d, R%d", src1, rs, rd); break;
case 0xb1: print("add 0x%08X, R%d, R%d", imm32, rs, rd); break;
case 0xb2: print("addu R%d, R%d, R%d", src1, rs, rd); break;
case 0xb3: print("addu 0x%08X, R%d, R%d", imm32, rs, rd); break;
case 0xb4: print("sub R%d, R%d, R%d", src1, rs, rd); break;
case 0xb5: print("sub 0x%08X, R%d, R%d", imm32, rs, rd); break;
case 0xb6: print("subu R%d, R%d, R%d", src1, rs, rd); break;
case 0xb7: print("subu 0x%08X, R%d, R%d", imm32, rs, rd); break;
case 0xc0: print("vadd R%d, R%d, R%d", src1, rs, rd); break;
case 0xc1: print("vadd 0x%08X, R%d, R%d", imm32, rs, rd); break;
case 0xc2: print("vsub R%d, R%d, R%d", src1, rs, rd); break;
case 0xc3: print("vsub 0x%08X, R%d, R%d", imm32, rs, rd); break;
case 0xc4: print("vmpy R%d, R%d, R%d", src1, rs, rd); break;
case 0xc5: print("vmpy 0x%08X, R%d, R%d", imm32, rs, rd); break;
case 0xd6: case 0xc6:
print("vmsub R%d, R%d, R%d", src1, rs, rd);
break;
case 0xd7: case 0xc7:
print("vmsub 0x%08X, R%d, R%d", imm32, rs, rd);
break;
case 0xd8: case 0xc8:
print("vrnd R%d, R%d, R%d", src1, rs, rd);
break;
case 0xd9: case 0xc9:
print("vrnd 0x%08X, R%d, R%d", imm32, rs, rd);
break;
case 0xca: print("vrnd R%d, R%d, R%d", src1, rs, rd); break;
case 0xcb: print("vrnd 0x%08X, R%d, R%d", imm32, rs, rd); break;
case 0xcc: print("vmac R%d, R%d, R%d", src1, rs, rd); break;
case 0xcd: print("vmac 0x%08X, R%d, R%d", imm32, rs, rd); break;
case 0xce: print("vmsc R%d, R%d, R%d", src1, rs, rd); break;
case 0xcf: print("vmsc 0x%08X, R%d, R%d", imm32, rs, rd); break;
case 0xe0: print("fadd R%d, R%d, R%d", src1, rs, rd); break;
case 0xe1: print("fadd 0x%08X, R%d, R%d", imm32, rs, rd); break;
case 0xe2: print("fsub R%d, R%d, R%d", src1, rs, rd); break;
case 0xe3: print("fsub 0x%08X, R%d, R%d", imm32, rs, rd); break;
case 0xe4: print("fmpy R%d, R%d, R%d", src1, rs, rd); break;
case 0xe5: print("fmpy 0x%08X, R%d, R%d", imm32, rs, rd); break;
case 0xe6: print("fdiv R%d, R%d, R%d", src1, rs, rd); break;
case 0xe7: print("fdiv 0x%08X, R%d, R%d", imm32, rs, rd); break;
case 0xe8: print("frndx R%d, R%d", src1, rd); break;
case 0xe9: print("frndx 0x%08X, R%d", imm32, rd); break;
case 0xea: print("fcmp R%d, R%d, R%d", src1, rs, rd); break;
case 0xeb: print("fcmp 0x%08X, R%d, R%d", imm32, rs, rd); break;
case 0xee: print("fsqrt R%d, R%d", src1, rd); break;
case 0xef: print("fsqrt 0x%08X, R%d", imm32, rd); break;
case 0xf0: print("lmo R%d, R%d", rs, rd); break;
case 0xf2: print("rmo R%d, R%d", rs, rd); break;
case 0xfc: print("estop "); break;
case 0xfe: case 0xff:
print("illopF ");
break;
}
break;
}
}
return opbytes | flags | DASMFLAG_SUPPORTED;
}
CPU_DISASSEMBLE(tms32082_mp)
{
return tms32082_disasm_mp(buffer, pc, oprom);
}

120
src/emu/cpu/tms32082/tms32082.c Normal file
View File

@ -0,0 +1,120 @@
/*
Texas Instruments TMS320C82 DSP Emulator
Written by Ville Linde
*/
#include "emu.h"
#include "debugger.h"
#include "tms32082.h"
extern CPU_DISASSEMBLE(tms32082_mp);
const device_type TMS32082_MP = &device_creator<tms32082_mp_device>;
tms32082_mp_device::tms32082_mp_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
: cpu_device(mconfig, TMS32082_MP, "TMS32082 MP", tag, owner, clock, "tms32082_mp", __FILE__)
, m_program_config("program", ENDIANNESS_BIG, 32, 32, 0)
{
}
offs_t tms32082_mp_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options)
{
return CPU_DISASSEMBLE_NAME(tms32082_mp)(this, buffer, pc, oprom, opram, options);
}
void tms32082_mp_device::device_start()
{
m_program = &space(AS_PROGRAM);
save_item(NAME(m_pc));
save_item(NAME(m_fetchpc));
save_item(NAME(m_reg));
save_item(NAME(m_acc));
// Register state for debugger
state_add(MP_PC, "pc", m_pc).formatstr("%08X");
state_add(MP_R0, "r0", m_reg[0]).formatstr("%08X");
state_add(MP_R1, "r1", m_reg[1]).formatstr("%08X");
state_add(MP_R2, "r2", m_reg[2]).formatstr("%08X");
state_add(MP_R3, "r3", m_reg[3]).formatstr("%08X");
state_add(MP_R4, "r4", m_reg[4]).formatstr("%08X");
state_add(MP_R5, "r5", m_reg[5]).formatstr("%08X");
state_add(MP_R6, "r6", m_reg[6]).formatstr("%08X");
state_add(MP_R7, "r7", m_reg[7]).formatstr("%08X");
state_add(MP_R8, "r8", m_reg[8]).formatstr("%08X");
state_add(MP_R9, "r9", m_reg[9]).formatstr("%08X");
state_add(MP_R10, "r10", m_reg[10]).formatstr("%08X");
state_add(MP_R11, "r11", m_reg[11]).formatstr("%08X");
state_add(MP_R12, "r12", m_reg[12]).formatstr("%08X");
state_add(MP_R13, "r13", m_reg[13]).formatstr("%08X");
state_add(MP_R14, "r14", m_reg[14]).formatstr("%08X");
state_add(MP_R15, "r15", m_reg[15]).formatstr("%08X");
state_add(MP_R16, "r16", m_reg[16]).formatstr("%08X");
state_add(MP_R17, "r17", m_reg[17]).formatstr("%08X");
state_add(MP_R18, "r18", m_reg[18]).formatstr("%08X");
state_add(MP_R19, "r19", m_reg[19]).formatstr("%08X");
state_add(MP_R20, "r20", m_reg[20]).formatstr("%08X");
state_add(MP_R21, "r21", m_reg[21]).formatstr("%08X");
state_add(MP_R22, "r22", m_reg[22]).formatstr("%08X");
state_add(MP_R23, "r23", m_reg[23]).formatstr("%08X");
state_add(MP_R24, "r24", m_reg[24]).formatstr("%08X");
state_add(MP_R25, "r25", m_reg[25]).formatstr("%08X");
state_add(MP_R26, "r26", m_reg[26]).formatstr("%08X");
state_add(MP_R27, "r27", m_reg[27]).formatstr("%08X");
state_add(MP_R28, "r28", m_reg[28]).formatstr("%08X");
state_add(MP_R29, "r29", m_reg[29]).formatstr("%08X");
state_add(MP_R30, "r30", m_reg[30]).formatstr("%08X");
state_add(MP_R31, "r31", m_reg[31]).formatstr("%08X");
state_add(MP_ACC0, "acc0", m_acc[0]).formatstr("%016X");
state_add(MP_ACC1, "acc1", m_acc[1]).formatstr("%016X");
state_add(MP_ACC2, "acc2", m_acc[2]).formatstr("%016X");
state_add(MP_ACC3, "acc3", m_acc[3]).formatstr("%016X");
state_add(STATE_GENPC, "curpc", m_pc).noshow();
m_icountptr = &m_icount;
}
void tms32082_mp_device::state_string_export(const device_state_entry &entry, astring &string)
{
switch (entry.index())
{
case STATE_GENFLAGS:
string.printf("?");
break;
}
}
void tms32082_mp_device::device_reset()
{
m_pc = 0;
m_fetchpc = 0xfffffff8;
for (int i=0; i < 32; i++)
{
m_reg[i] = 0;
}
m_acc[0] = 0;
m_acc[1] = 0;
m_acc[2] = 0;
m_acc[3] = 0;
}
void tms32082_mp_device::execute_run()
{
m_pc = m_fetchpc;
debugger_instruction_hook(this, m_pc);
m_icount = 0;
return;
}

98
src/emu/cpu/tms32082/tms32082.h Normal file
View File

@ -0,0 +1,98 @@
#pragma once
#ifndef __TMS32082_H__
#define __TMS32082_H__
class tms32082_mp_device : public cpu_device
{
public:
// construction/destruction
tms32082_mp_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
enum
{
MP_PC=1,
MP_R0,
MP_R1,
MP_R2,
MP_R3,
MP_R4,
MP_R5,
MP_R6,
MP_R7,
MP_R8,
MP_R9,
MP_R10,
MP_R11,
MP_R12,
MP_R13,
MP_R14,
MP_R15,
MP_R16,
MP_R17,
MP_R18,
MP_R19,
MP_R20,
MP_R21,
MP_R22,
MP_R23,
MP_R24,
MP_R25,
MP_R26,
MP_R27,
MP_R28,
MP_R29,
MP_R30,
MP_R31,
MP_ACC0,
MP_ACC1,
MP_ACC2,
MP_ACC3,
};
protected:
// device level overrides
virtual void device_start();
virtual void device_reset();
// device_execute_interface overrides
virtual UINT32 execute_min_cycles() const { return 1; }
virtual UINT32 execute_max_cycles() const { return 1; }
virtual UINT32 execute_input_lines() const { return 0; }
virtual void execute_run();
// device_memory_interface overrides
virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const
{
switch (spacenum)
{
case AS_PROGRAM: return &m_program_config;
default: return NULL;
}
}
// device_state_interface overrides
void state_string_export(const device_state_entry &entry, astring &string);
// device_disasm_interface overrides
virtual UINT32 disasm_min_opcode_bytes() const { return 4; }
virtual UINT32 disasm_max_opcode_bytes() const { return 8; }
virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options);
address_space_config m_program_config;
UINT32 m_pc;
UINT32 m_fetchpc;
UINT32 m_reg[32];
UINT64 m_acc[4];
int m_icount;
address_space *m_program;
};
extern const device_type TMS32082_MP;
#endif /* __TMS32082_H__ */

1
src/mame/mame.mak
View File

@ -72,6 +72,7 @@ CPUS += TMS32010
CPUS += TMS32025
CPUS += TMS32031
CPUS += TMS32051
CPUS += TMS32082
CPUS += TMS57002
CPUS += CCPU
CPUS += ADSP21XX