mirror of
https://github.com/holub/mame
synced 2025-06-05 20:33:45 +03:00
Added basic implementation of the NSC810 RAM-I/O-Timer device, and plugged it into the Husky Hunter 2 driver. [Barry Rodewald]
This commit is contained in:
mahlemiut
parent
e6dcbb90e4
commit
c86b56168c
2
.gitattributes
vendored
2
.gitattributes
vendored
@ -2341,6 +2341,8 @@ src/emu/machine/netlist.c svneol=native#text/plain
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src/emu/machine/netlist.h svneol=native#text/plain
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src/emu/machine/nmc9306.c svneol=native#text/plain
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src/emu/machine/nmc9306.h svneol=native#text/plain
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src/emu/machine/nsc810.c svneol=native#text/plain
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src/emu/machine/nsc810.h svneol=native#text/plain
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src/emu/machine/nscsi_bus.c svneol=native#text/plain
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src/emu/machine/nscsi_bus.h svneol=native#text/plain
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src/emu/machine/nscsi_cb.c svneol=native#text/plain
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311
src/emu/machine/nsc810.c
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311
src/emu/machine/nsc810.c
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@ -0,0 +1,311 @@
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/*
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* nsc810.c
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*
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* Created on: 10/03/2014
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*
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* TODO:
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* - 128 byte RAM
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* - other timer modes (only mode 1 - event counter - is implemented currently)
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* - port bit set/clear
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* - and lots of other stuff
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*/
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#include "nsc810.h"
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//**************************************************************************
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// DEVICE DEFINITIONS
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//**************************************************************************
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#define LOG (1)
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const device_type NSC810 = &device_creator<nsc810_device>;
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nsc810_device::nsc810_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
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device_t(mconfig, NSC810, "National Semiconductor NSC810", tag, owner, clock, "nsc810", __FILE__),
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m_portA_r(*this),
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m_portB_r(*this),
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m_portC_r(*this),
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m_portA_w(*this),
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m_portB_w(*this),
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m_portC_w(*this),
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m_timer0_out(*this),
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m_timer1_out(*this)
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{
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}
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void nsc810_device::device_start()
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{
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m_portA_r.resolve_safe(0);
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m_portB_r.resolve_safe(0);
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m_portC_r.resolve_safe(0);
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m_portA_w.resolve_safe();
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m_portB_w.resolve_safe();
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m_portC_w.resolve_safe();
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m_timer0_out.resolve_safe();
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m_timer1_out.resolve_safe();
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m_portA_w(0);
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m_portB_w(0);
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m_portC_w(0);
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m_timer0_out(0);
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m_timer1_out(0);
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m_timer0 = timer_alloc(TIMER0_CLOCK);
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m_timer1 = timer_alloc(TIMER1_CLOCK);
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}
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void nsc810_device::device_reset()
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{
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m_portA_latch = 0;
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m_portB_latch = 0;
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m_portC_latch = 0;
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m_ddrA = 0;
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m_ddrB = 0;
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m_ddrC = 0;
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m_mode = 0;
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m_timer0_mode = 0;
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m_timer1_mode = 0;
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m_timer0_counter = 0;
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m_timer1_counter = 0;
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m_timer0_running = false;
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m_timer1_running = false;
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m_ramselect = false;
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}
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void nsc810_device::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr)
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{
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switch(id)
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{
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case TIMER0_CLOCK:
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m_timer0_counter--;
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if((m_timer0_mode & 0x07) == 0x01 || (m_timer0_mode & 0x07) == 0x02)
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{
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if(m_timer0_counter == 0)
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{
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m_timer0_out(ASSERT_LINE);
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m_timer0_counter = m_timer0_base;
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if(LOG) logerror("NSC810 '%s': Timer 0 output set\n",tag());
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}
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}
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break;
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case TIMER1_CLOCK:
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m_timer1_counter--;
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if((m_timer1_mode & 0x07) == 0x01 || (m_timer1_mode & 0x07) == 0x02)
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{
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if(m_timer1_counter == 0)
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{
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m_timer1_out(ASSERT_LINE);
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m_timer1_counter = m_timer1_base;
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if(LOG) logerror("NSC810 '%s': Timer 1 output set\n",tag());
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}
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}
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break;
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}
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}
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READ8_MEMBER(nsc810_device::read)
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{
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UINT8 res = 0xff;
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if(m_ramselect)
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{
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// TODO: 128 byte RAM access
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}
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else
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{
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// Register access
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switch(offset & 0x1f)
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{
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case REG_PORTA:
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res = m_portA_latch &= m_ddrA;
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res |= (m_portA_r() & ~m_ddrA);
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//if(LOG) logerror("NSC810 '%s': Port A data read %02x\n",tag(),res);
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break;
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case REG_PORTB:
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res = m_portB_latch &= m_ddrB;
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res |= (m_portB_r() & ~m_ddrB);
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//if(LOG) logerror("NSC810 '%s': Port B data read %02x\n",tag(),res);
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break;
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case REG_PORTC:
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res = m_portC_latch &= m_ddrC;
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res |= (m_portC_r() & ~m_ddrC);
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//if(LOG) logerror("NSC810 '%s': Port C data read %02x\n",tag(),res);
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break;
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case REG_MODE_TIMER0:
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res = m_timer0_mode;
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break;
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case REG_MODE_TIMER1:
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res = m_timer1_mode;
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break;
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case REG_TIMER0_LOW:
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res = m_timer0_counter & 0xff;
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if((m_timer0_mode & 0x07) == 0x01 || (m_timer0_mode & 0x07) == 0x02)
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{
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m_timer0_out(CLEAR_LINE);
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if(LOG) logerror("NSC810 '%s': Timer 0 output reset\n",tag());
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}
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break;
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case REG_TIMER0_HIGH:
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res = m_timer0_counter >> 8;
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if((m_timer0_mode & 0x07) == 0x01 || (m_timer0_mode & 0x07) == 0x02)
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{
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m_timer0_out(CLEAR_LINE);
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if(LOG) logerror("NSC810 '%s': Timer 0 output reset\n",tag());
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}
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break;
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case REG_TIMER1_LOW:
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res = m_timer1_counter & 0xff;
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if((m_timer1_mode & 0x07) == 0x01 || (m_timer1_mode & 0x07) == 0x02)
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{
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m_timer1_out(0);
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if(LOG) logerror("NSC810 '%s': Timer 1 output reset\n",tag());
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}
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break;
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case REG_TIMER1_HIGH:
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res = m_timer1_counter >> 8;
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if((m_timer1_mode & 0x07) == 0x01 || (m_timer1_mode & 0x07) == 0x02)
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{
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m_timer1_out(0);
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if(LOG) logerror("NSC810 '%s': Timer 1 output reset\n",tag());
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}
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break;
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default:
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if(LOG) logerror("NSC810 '%s': unused port %02x read\n",tag(),offset);
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}
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}
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return res;
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}
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WRITE8_MEMBER(nsc810_device::write)
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{
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UINT32 rate;
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if(m_ramselect)
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{
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// TODO: 128 byte RAM access
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}
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else
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{
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// Register access
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switch(offset & 0x1f)
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{
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case REG_PORTA:
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m_portA_latch = data & ~m_ddrA;
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m_portA_w(data & m_ddrA);
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if(LOG) logerror("NSC810 '%s': Port A data write %02x\n",tag(),data);
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break;
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case REG_PORTB:
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m_portB_latch = data & ~m_ddrB;
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m_portB_w(data & m_ddrB);
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if(LOG) logerror("NSC810 '%s': Port B data write %02x\n",tag(),data);
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break;
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case REG_PORTC:
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m_portC_latch = data & ~m_ddrC;
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m_portC_w(data & m_ddrC);
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if(LOG) logerror("NSC810 '%s': Port C data write %02x\n",tag(),data);
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break;
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case REG_DDRA:
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m_ddrA = data;
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if(LOG) logerror("NSC810 '%s': Port A direction write %02x\n",tag(),data);
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break;
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case REG_DDRB:
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m_ddrB = data;
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if(LOG) logerror("NSC810 '%s': Port B direction write %02x\n",tag(),data);
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break;
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case REG_DDRC:
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m_ddrC = data;
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if(LOG) logerror("NSC810 '%s': Port C direction write %02x\n",tag(),data);
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break;
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case REG_MODE_DEF:
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if(LOG) logerror("NSC810 '%s': Mode Definition write %02x\n",tag(),data);
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break;
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case REG_PORTA_BITCLR:
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if(LOG) logerror("NSC810 '%s': Port A bit-clear write %02x\n",tag(),data);
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break;
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case REG_PORTB_BITCLR:
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if(LOG) logerror("NSC810 '%s': Port B bit-clear write %02x\n",tag(),data);
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break;
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case REG_PORTC_BITCLR:
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if(LOG) logerror("NSC810 '%s': Port C bit-clear write %02x\n",tag(),data);
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break;
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case REG_PORTA_BITSET:
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if(LOG) logerror("NSC810 '%s': Port A bit-set write %02x\n",tag(),data);
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break;
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case REG_PORTB_BITSET:
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if(LOG) logerror("NSC810 '%s': Port B bit-set write %02x\n",tag(),data);
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break;
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case REG_PORTC_BITSET:
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if(LOG) logerror("NSC810 '%s': Port C bit-set write %02x\n",tag(),data);
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break;
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case REG_TIMER0_LOW:
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m_timer0_base = (m_timer0_base & 0xff00) | data;
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m_timer0_counter = (m_timer0_counter & 0xff00) | data;
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if(LOG) logerror("NSC810 '%s': Timer 0 low-byte write %02x (base=%04x)\n",tag(),data,m_timer0_base);
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break;
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case REG_TIMER0_HIGH:
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m_timer0_base = (m_timer0_base & 0x00ff) | (data << 8);
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m_timer0_counter = (m_timer0_counter & 0x00ff) | (data << 8);
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if(LOG) logerror("NSC810 '%s': Timer 0 high-byte write %02x (base=%04x)\n",tag(),data,m_timer0_base);
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break;
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case REG_TIMER1_LOW:
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m_timer1_base = (m_timer1_base & 0xff00) | data;
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m_timer1_counter = (m_timer1_counter & 0xff00) | data;
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if(LOG) logerror("NSC810 '%s': Timer 1 low-byte write %02x (base=%04x)\n",tag(),data,m_timer1_base);
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break;
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case REG_TIMER1_HIGH:
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m_timer1_base = (m_timer1_base & 0x00ff) | (data << 8);
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m_timer1_counter = (m_timer1_counter & 0x00ff) | (data << 8);
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if(LOG) logerror("NSC810 '%s': Timer 1 high-byte write %02x (base=%04x)\n",tag(),data,m_timer1_base);
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break;
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case REG_TIMER0_STOP:
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m_timer0_running = false;
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m_timer0->reset();
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if(LOG) logerror("NSC810 '%s': Timer 0 Stop write %02x\n",tag(),data);
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break;
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case REG_TIMER0_START:
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if((m_timer0_mode & 0x07) != 0x00 && (m_timer0_mode & 0x07) != 0x07)
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{
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m_timer0_running = true;
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if(m_timer0_mode & 0x10)
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rate = m_timer0_clock / 64;
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else
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if(m_timer0_mode & 0x08)
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rate = m_timer0_clock / 2;
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else
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rate = m_timer0_clock;
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m_timer0->adjust(attotime::zero,0,attotime::from_hz(rate));
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}
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if(LOG) logerror("NSC810 '%s': Timer 0 Start write %02x\n",tag(),data);
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break;
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case REG_TIMER1_STOP:
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m_timer1_running = false;
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m_timer1->reset();
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if(LOG) logerror("NSC810 '%s': Timer 1 Stop write %02x\n",tag(),data);
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break;
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case REG_TIMER1_START:
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if((m_timer1_mode & 0x07) != 0x00 && (m_timer1_mode & 0x07) != 0x07)
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{
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m_timer1_running = true;
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// no /64 prescaler on timer 1
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if(m_timer0_mode & 0x08)
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rate = m_timer0_clock / 2;
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else
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rate = m_timer0_clock;
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m_timer1->adjust(attotime::zero,0,attotime::from_hz(rate));
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}
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if(LOG) logerror("NSC810 '%s': Timer 1 Start write %02x\n",tag(),data);
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break;
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case REG_MODE_TIMER0:
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m_timer0_mode = data;
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if(LOG) logerror("NSC810 '%s': Timer 0 Mode write %02x\n",tag(),data);
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break;
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case REG_MODE_TIMER1:
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m_timer1_mode = data;
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if(LOG) logerror("NSC810 '%s': Timer 1 Mode write %02x\n",tag(),data);
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break;
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default:
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logerror("NSC810 '%s': Unused register %02x write %02x\n",tag(),offset,data);
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}
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}
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}
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133
src/emu/machine/nsc810.h
Normal file
133
src/emu/machine/nsc810.h
Normal file
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/*
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* nsc810.h
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*
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* Created on: 10/03/2014
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*/
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#ifndef NSC810_H_
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#define NSC810_H_
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#include "emu.h"
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class nsc810_device : public device_t
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{
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public:
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// construction/destruction
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nsc810_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
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template<class _Object> static devcb2_base &set_portA_read_callback(device_t &device, _Object object) { return downcast<nsc810_device &>(device).m_portA_r.set_callback(object); }
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template<class _Object> static devcb2_base &set_portB_read_callback(device_t &device, _Object object) { return downcast<nsc810_device &>(device).m_portB_r.set_callback(object); }
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template<class _Object> static devcb2_base &set_portC_read_callback(device_t &device, _Object object) { return downcast<nsc810_device &>(device).m_portC_r.set_callback(object); }
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template<class _Object> static devcb2_base &set_portA_write_callback(device_t &device, _Object object) { return downcast<nsc810_device &>(device).m_portA_w.set_callback(object); }
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template<class _Object> static devcb2_base &set_portB_write_callback(device_t &device, _Object object) { return downcast<nsc810_device &>(device).m_portB_w.set_callback(object); }
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template<class _Object> static devcb2_base &set_portC_write_callback(device_t &device, _Object object) { return downcast<nsc810_device &>(device).m_portC_w.set_callback(object); }
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template<class _Object> static devcb2_base &set_timer0_callback(device_t &device, _Object object) { return downcast<nsc810_device &>(device).m_timer0_out.set_callback(object); }
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template<class _Object> static devcb2_base &set_timer1_callback(device_t &device, _Object object) { return downcast<nsc810_device &>(device).m_timer1_out.set_callback(object); }
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void set_timer0_clock(UINT32 clk) { m_timer0_clock = clk; }
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void set_timer1_clock(UINT32 clk) { m_timer1_clock = clk; }
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DECLARE_READ8_MEMBER(read);
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DECLARE_WRITE8_MEMBER(write);
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protected:
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virtual void device_start();
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virtual void device_reset();
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virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr);
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private:
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UINT8 m_portA_latch;
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UINT8 m_portB_latch;
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UINT8 m_portC_latch;
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UINT8 m_ddrA;
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UINT8 m_ddrB;
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UINT8 m_ddrC;
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UINT8 m_mode;
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emu_timer* m_timer0;
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emu_timer* m_timer1;
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UINT8 m_timer0_mode;
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UINT8 m_timer1_mode;
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UINT16 m_timer0_counter;
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UINT16 m_timer1_counter;
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UINT16 m_timer0_base;
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UINT16 m_timer1_base;
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bool m_timer0_running;
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bool m_timer1_running;
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UINT32 m_timer0_clock;
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UINT32 m_timer1_clock;
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bool m_ramselect;
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devcb2_read8 m_portA_r;
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devcb2_read8 m_portB_r;
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devcb2_read8 m_portC_r;
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devcb2_write8 m_portA_w;
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devcb2_write8 m_portB_w;
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devcb2_write8 m_portC_w;
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devcb2_write_line m_timer0_out;
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devcb2_write_line m_timer1_out;
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static const device_timer_id TIMER0_CLOCK = 0;
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static const device_timer_id TIMER1_CLOCK = 1;
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enum
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{
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REG_PORTA = 0x00,
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REG_PORTB,
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REG_PORTC,
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REG_DDRA = 0x04,
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REG_DDRB,
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REG_DDRC,
|
||||
REG_MODE_DEF,
|
||||
REG_PORTA_BITCLR,
|
||||
REG_PORTB_BITCLR,
|
||||
REG_PORTC_BITCLR,
|
||||
REG_PORTA_BITSET = 0x0c,
|
||||
REG_PORTB_BITSET,
|
||||
REG_PORTC_BITSET,
|
||||
REG_TIMER0_LOW = 0x10,
|
||||
REG_TIMER0_HIGH,
|
||||
REG_TIMER1_LOW,
|
||||
REG_TIMER1_HIGH,
|
||||
REG_TIMER0_STOP,
|
||||
REG_TIMER0_START,
|
||||
REG_TIMER1_STOP,
|
||||
REG_TIMER1_START,
|
||||
REG_MODE_TIMER0,
|
||||
REG_MODE_TIMER1
|
||||
};
|
||||
};
|
||||
|
||||
#define MCFG_NSC810_ADD(_tag, _t0clk, _t1clk) \
|
||||
MCFG_DEVICE_ADD(_tag, NSC810, 0) \
|
||||
downcast<nsc810_device *>(device)->set_timer0_clock(_t0clk); \
|
||||
downcast<nsc810_device *>(device)->set_timer1_clock(_t1clk);
|
||||
|
||||
#define MCFG_NSC810_PORTA_READ(_read) \
|
||||
devcb = &nsc810_device::set_portA_read_callback(*device, DEVCB2_##_read);
|
||||
|
||||
#define MCFG_NSC810_PORTB_READ(_read) \
|
||||
devcb = &nsc810_device::set_portB_read_callback(*device, DEVCB2_##_read);
|
||||
|
||||
#define MCFG_NSC810_PORTC_READ(_read) \
|
||||
devcb = &nsc810_device::set_portC_read_callback(*device, DEVCB2_##_read);
|
||||
|
||||
#define MCFG_NSC810_PORTA_WRITE(_write) \
|
||||
devcb = &nsc810_device::set_portA_write_callback(*device, DEVCB2_##_write);
|
||||
|
||||
#define MCFG_NSC810_PORTB_WRITE(_write) \
|
||||
devcb = &nsc810_device::set_portB_write_callback(*device, DEVCB2_##_write);
|
||||
|
||||
#define MCFG_NSC810_PORTC_WRITE(_write) \
|
||||
devcb = &nsc810_device::set_portC_write_callback(*device, DEVCB2_##_write);
|
||||
|
||||
#define MCFG_NSC810_TIMER0_OUT(_write) \
|
||||
devcb = &nsc810_device::set_timer0_callback(*device, DEVCB2_##_write);
|
||||
|
||||
#define MCFG_NSC810_TIMER1_OUT(_write) \
|
||||
devcb = &nsc810_device::set_timer1_callback(*device, DEVCB2_##_write);
|
||||
|
||||
// device type definition
|
||||
extern const device_type NSC810;
|
||||
|
||||
|
||||
#endif /* NSC810_H_ */
|
||||
@ -29,6 +29,7 @@
|
||||
#include "machine/mm58274c.h"
|
||||
#include "rendlay.h"
|
||||
#include "sound/speaker.h"
|
||||
#include "machine/nsc810.h"
|
||||
|
||||
class hunter2_state : public driver_device
|
||||
{
|
||||
@ -40,6 +41,7 @@ public:
|
||||
{ }
|
||||
|
||||
DECLARE_READ8_MEMBER(port00_r);
|
||||
DECLARE_READ8_MEMBER(port01_r);
|
||||
DECLARE_WRITE8_MEMBER(port01_w);
|
||||
DECLARE_READ8_MEMBER(port02_r);
|
||||
DECLARE_WRITE8_MEMBER(port60_w);
|
||||
@ -50,6 +52,7 @@ public:
|
||||
TIMER_DEVICE_CALLBACK_MEMBER(a_timer);
|
||||
DECLARE_PALETTE_INIT(hunter2);
|
||||
DECLARE_DRIVER_INIT(hunter2);
|
||||
DECLARE_WRITE_LINE_MEMBER(timer0_out);
|
||||
|
||||
private:
|
||||
UINT8 m_keydata;
|
||||
@ -70,11 +73,11 @@ ADDRESS_MAP_END
|
||||
static ADDRESS_MAP_START(hunter2_io, AS_IO, 8, hunter2_state)
|
||||
ADDRESS_MAP_UNMAP_HIGH
|
||||
ADDRESS_MAP_GLOBAL_MASK(0xff)
|
||||
//AM_RANGE(0x00, 0x1f) AM_DEVREADWRITE("nsc810", nsc810_device, read, write) // device not yet emulated
|
||||
AM_RANGE(0x00, 0x00) AM_READ(port00_r)
|
||||
AM_RANGE(0x01, 0x01) AM_WRITE(port01_w)
|
||||
AM_RANGE(0x02, 0x02) AM_READ(port02_r)
|
||||
AM_RANGE(0x03, 0x1F) AM_WRITENOP
|
||||
AM_RANGE(0x00, 0x1f) AM_DEVREADWRITE("iotimer", nsc810_device, read, write) // device not yet emulated
|
||||
// AM_RANGE(0x00, 0x00) AM_READ(port00_r)
|
||||
// AM_RANGE(0x01, 0x01) AM_WRITE(port01_w)
|
||||
// AM_RANGE(0x02, 0x02) AM_READ(port02_r)
|
||||
// AM_RANGE(0x03, 0x1F) AM_WRITENOP
|
||||
AM_RANGE(0x20, 0x20) AM_DEVWRITE("lcdc", hd61830_device, data_w)
|
||||
AM_RANGE(0x21, 0x21) AM_DEVREADWRITE("lcdc", hd61830_device, status_r, control_w)
|
||||
AM_RANGE(0x3e, 0x3e) AM_DEVREAD("lcdc", hd61830_device, data_r)
|
||||
@ -176,14 +179,21 @@ READ8_MEMBER( hunter2_state::port00_r )
|
||||
return data;
|
||||
}
|
||||
|
||||
READ8_MEMBER( hunter2_state::port01_r )
|
||||
{
|
||||
// TODO: bit 7 = RS232 DSR line
|
||||
return 0x00;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER( hunter2_state::port01_w )
|
||||
{
|
||||
m_keydata = data;
|
||||
logerror("Key row select %02x\n",data);
|
||||
}
|
||||
|
||||
READ8_MEMBER( hunter2_state::port02_r )
|
||||
{
|
||||
return 0x2c;
|
||||
return 0x28;
|
||||
}
|
||||
|
||||
WRITE8_MEMBER( hunter2_state::port60_w )
|
||||
@ -305,6 +315,12 @@ TIMER_DEVICE_CALLBACK_MEMBER(hunter2_state::a_timer)
|
||||
m_maincpu->set_input_line(NSC800_RSTA, HOLD_LINE);
|
||||
}
|
||||
|
||||
WRITE_LINE_MEMBER(hunter2_state::timer0_out)
|
||||
{
|
||||
if(state == ASSERT_LINE)
|
||||
m_maincpu->set_input_line(INPUT_LINE_NMI, PULSE_LINE);
|
||||
}
|
||||
|
||||
static MACHINE_CONFIG_START( hunter2, hunter2_state )
|
||||
/* basic machine hardware */
|
||||
MCFG_CPU_ADD("maincpu", NSC800, 4000000)
|
||||
@ -330,6 +346,14 @@ static MACHINE_CONFIG_START( hunter2, hunter2_state )
|
||||
/* Devices */
|
||||
MCFG_MM58274C_ADD("rtc", rtc_intf)
|
||||
//MCFG_TIMER_DRIVER_ADD_PERIODIC("hunter_a", hunter2_state, a_timer, attotime::from_hz(61))
|
||||
|
||||
MCFG_NSC810_ADD("iotimer",XTAL_4MHz,XTAL_4MHz)
|
||||
MCFG_NSC810_PORTA_READ(READ8(hunter2_state,port00_r))
|
||||
MCFG_NSC810_PORTB_READ(READ8(hunter2_state,port01_r))
|
||||
MCFG_NSC810_PORTB_WRITE(WRITE8(hunter2_state,port01_w))
|
||||
MCFG_NSC810_PORTC_READ(READ8(hunter2_state,port02_r))
|
||||
MCFG_NSC810_TIMER0_OUT(WRITELINE(hunter2_state,timer0_out))
|
||||
MCFG_NSC810_TIMER1_OUT(INPUTLINE("maincpu",NSC800_RSTA))
|
||||
MACHINE_CONFIG_END
|
||||
|
||||
/* ROM definition */
|
||||
|
||||
@ -486,6 +486,7 @@ MACHINES += PC_FDC
|
||||
MACHINES += DP8390
|
||||
MACHINES += MPU401
|
||||
MACHINES += AT_KEYBC
|
||||
MACHINES += NSC810
|
||||
#MACHINES += PROFILE
|
||||
|
||||
#-------------------------------------------------
|
||||
@ -2096,6 +2097,7 @@ $(MESSOBJ)/skeleton.a: \
|
||||
$(MESS_DRIVERS)/hpz80unk.o \
|
||||
$(MESS_DRIVERS)/ht68k.o \
|
||||
$(MESS_DRIVERS)/hunter2.o \
|
||||
$(EMU_MACHINE)/nsc810.o \
|
||||
$(MESS_DRIVERS)/ibm6580.o \
|
||||
$(MESS_DRIVERS)/ie15.o \
|
||||
$(MESS_DRIVERS)/if800.o \
|
||||
|
||||
Loading…
Reference in New Issue
Block a user