mirror of
https://github.com/holub/mame
synced 2025-10-06 09:00:04 +03:00
tube: New TUBE device. Acorn Tube ULA for use in Acorn 2nd Processors
This commit is contained in:
Nigel Barnes
parent
70b91571ce
commit
c967171c7a
@ -2509,6 +2509,18 @@ if (MACHINES["TMS9902"]~=null) then
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}
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end
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---------------------------------------------------
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--
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--@src/devices/machine/tube.h,MACHINES["TUBE"] = true
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---------------------------------------------------
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if (MACHINES["TUBE"]~=null) then
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files {
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MAME_DIR .. "src/devices/machine/tube.cpp",
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MAME_DIR .. "src/devices/machine/tube.h",
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}
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end
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---------------------------------------------------
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--
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--@src/devices/machine/upd1990a.h,MACHINES["UPD1990A"] = true
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@ -564,6 +564,7 @@ MACHINES["TTL74175"] = true
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MACHINES["TTL74181"] = true
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MACHINES["TTL74259"] = true
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MACHINES["TTL7474"] = true
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MACHINES["TUBE"] = true
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MACHINES["UPD1990A"] = true
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--MACHINES["UPD4992"] = true
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MACHINES["UPD4701"] = true
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315
src/devices/machine/tube.cpp
Normal file
315
src/devices/machine/tube.cpp
Normal file
@ -0,0 +1,315 @@
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// license:BSD-3-Clause
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// copyright-holders:Nigel Barnes
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/**********************************************************************
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Acorn Tube ULA emulation
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The Tube ULA acts as a parallel interface between two asynchronous
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processor systems. It consists of four byte-wide read-only registers
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and four byte-wide write-only registers. Eight bytes of memory mapped
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I/O space are used to address these registers, four for the data
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registers and four for the associated status registers.
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**********************************************************************/
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#include "emu.h"
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#include "machine/tube.h"
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//**************************************************************************
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// DEVICE DEFINITIONS
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//**************************************************************************
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DEFINE_DEVICE_TYPE(TUBE, tube_device, "tube", "Acorn Tube ULA")
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//-------------------------------------------------
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// bbc_tube_slot_device - constructor
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//-------------------------------------------------
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tube_device::tube_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) :
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device_t(mconfig, TUBE, tag, owner, clock),
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m_hirq_handler(*this),
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m_pnmi_handler(*this),
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m_pirq_handler(*this),
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m_drq_handler(*this)
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{
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}
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//-------------------------------------------------
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// device_start - device-specific startup
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//-------------------------------------------------
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void tube_device::device_start()
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{
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// resolve callbacks
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m_hirq_handler.resolve_safe();
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m_pnmi_handler.resolve_safe();
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m_pirq_handler.resolve_safe();
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m_drq_handler.resolve_safe();
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}
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//-------------------------------------------------
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// device_reset - device-specific reset
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//-------------------------------------------------
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void tube_device::device_reset()
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{
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m_ph1pos = m_hp3pos = 0;
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m_ph3pos = 1;
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m_r1stat = 0;
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m_hstat[0] = m_hstat[1] = m_hstat[3] = 0x40;
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m_hstat[2] = 0xc0;
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m_pstat[0] = m_pstat[1] = m_pstat[2] = m_pstat[3] = 0x40;
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}
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void tube_device::update_interrupts()
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{
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m_hirq_handler(BIT(m_r1stat, 0) && BIT(m_hstat[3], 7) ? ASSERT_LINE : CLEAR_LINE);
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m_pirq_handler((BIT(m_r1stat, 1) && BIT(m_pstat[0], 7)) || (BIT(m_r1stat, 2) && BIT(m_pstat[3], 7)) ? ASSERT_LINE : CLEAR_LINE);
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m_pnmi_handler(BIT(m_r1stat, 3) && ((m_hp3pos > BIT(m_r1stat, 4)) || (m_ph3pos == 0)) ? ASSERT_LINE : CLEAR_LINE);
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m_drq_handler(!BIT(m_r1stat, 4) && ((m_hp3pos > BIT(m_r1stat, 4)) || (m_ph3pos == 0)) ? ASSERT_LINE : CLEAR_LINE);
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}
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READ8_MEMBER(tube_device::host_r)
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{
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uint8_t data = 0xfe;
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switch (offset & 0x07)
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{
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case 0: /* Status and Register 1 flags */
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data = (m_hstat[0] & 0xc0) | m_r1stat;
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break;
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case 1: /* Register 1 */
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data = m_ph1[0];
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for (int i = 0; i < 23; i++) m_ph1[i] = m_ph1[i + 1];
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m_ph1pos--;
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m_pstat[0] |= 0x40;
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if (!m_ph1pos) m_hstat[0] &= ~0x80;
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break;
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case 2: /* Register 2 flags */
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data = m_hstat[1];
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break;
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case 3: /* Register 2 */
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data = m_ph2;
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if (m_hstat[1] & 0x80)
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{
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m_hstat[1] &= ~0x80;
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m_pstat[1] |= 0x40;
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}
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break;
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case 4: /* Register 3 flags */
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data = m_hstat[2];
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break;
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case 5: /* Register 3 */
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data = m_ph3[0];
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if (m_ph3pos > 0)
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{
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m_ph3[0] = m_ph3[1];
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m_ph3pos--;
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m_pstat[2] |= 0x40;
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if (!m_ph3pos) m_hstat[2] &= ~0x80;
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}
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break;
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case 6: /* Register 4 flags */
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data = m_hstat[3];
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break;
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case 7: /* Register 4 */
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data = m_ph4;
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if (m_hstat[3] & 0x80)
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{
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m_hstat[3] &= ~0x80;
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m_pstat[3] |= 0x40;
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}
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break;
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}
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update_interrupts();
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return data;
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}
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WRITE8_MEMBER(tube_device::host_w)
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{
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switch (offset & 0x07)
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{
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case 0: /* Status flags */
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if (data & 0x80)
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m_r1stat |= (data & 0x3f);
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else
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m_r1stat &= ~(data & 0x3f);
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m_hstat[0] = (m_hstat[0] & 0xc0) | (data & 0x3f);
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break;
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case 1: /* Register 1 */
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m_hp1 = data;
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m_pstat[0] |= 0x80;
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m_hstat[0] &= ~0x40;
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break;
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case 3: /* Register 2 */
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m_hp2 = data;
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m_pstat[1] |= 0x80;
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m_hstat[1] &= ~0x40;
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break;
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case 5: /* Register 3 */
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if (m_r1stat & 0x10)
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{
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if (m_hp3pos < 2)
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m_hp3[m_hp3pos++] = data;
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if (m_hp3pos == 2)
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{
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m_pstat[2] |= 0x80;
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m_hstat[2] &= ~0x40;
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}
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}
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else
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{
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m_hp3[0] = data;
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m_hp3pos = 1;
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m_pstat[2] |= 0x80;
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m_hstat[2] &= ~0x40;
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}
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break;
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case 7: /* Register 4 */
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m_hp4 = data;
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m_pstat[3] |= 0x80;
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m_hstat[3] &= ~0x40;
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break;
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}
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update_interrupts();
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}
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READ8_MEMBER(tube_device::parasite_r)
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{
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uint8_t data = 0x00;
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switch (offset & 0x07)
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{
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case 0: /*Register 1 flags */
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data = m_pstat[0] | m_r1stat;
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break;
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case 1: /* Register 1 */
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data = m_hp1;
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if (m_pstat[0] & 0x80)
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{
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m_pstat[0] &= ~0x80;
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m_hstat[0] |= 0x40;
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}
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break;
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case 2: /* Register 2 flags */
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data = m_pstat[1];
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break;
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case 3: /* Register 2 */
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data = m_hp2;
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if (m_pstat[1] & 0x80)
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{
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m_pstat[1] &= ~0x80;
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m_hstat[1] |= 0x40;
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}
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break;
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case 4: /* Register 3 flags */
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data = m_pstat[2];
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break;
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case 5: /* Register 3 */
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data = m_hp3[0];
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if (m_hp3pos > 0)
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{
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m_hp3[0] = m_hp3[1];
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m_hp3pos--;
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if (!m_hp3pos)
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{
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m_hstat[2] |= 0x40;
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m_pstat[2] &= ~0x80;
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}
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}
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break;
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case 6: /* Register 4 flags */
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data = m_pstat[3];
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break;
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case 7: /* Register 4 */
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data = m_hp4;
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if (m_pstat[3] & 0x80)
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{
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m_pstat[3] &= ~0x80;
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m_hstat[3] |= 0x40;
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}
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break;
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}
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update_interrupts();
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return data;
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}
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WRITE8_MEMBER(tube_device::parasite_w)
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{
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switch (offset & 0x07)
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{
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case 1: /* Register 1 */
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if (m_ph1pos < 24)
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{
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m_ph1[m_ph1pos++] = data;
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m_hstat[0] |= 0x80;
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if (m_ph1pos == 24)
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m_pstat[0] &= ~0x40;
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}
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break;
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case 3: /* Register 2 */
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m_ph2 = data;
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m_hstat[1] |= 0x80;
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m_pstat[1] &= ~0x40;
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break;
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case 5: /* Register 3 */
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if (m_r1stat & 0x10)
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{
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if (m_ph3pos < 2)
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m_ph3[m_ph3pos++] = data;
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if (m_ph3pos == 2)
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{
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m_hstat[2] |= 0x80;
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m_pstat[2] &= ~0x40;
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}
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}
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else
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{
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m_ph3[0] = data;
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m_ph3pos = 1;
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m_hstat[2] |= 0x80;
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m_pstat[2] &= ~0x40;
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}
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break;
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case 7: /* Register 4 */
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m_ph4 = data;
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m_hstat[3] |= 0x80;
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m_pstat[3] &= ~0x40;
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break;
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}
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update_interrupts();
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}
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94
src/devices/machine/tube.h
Normal file
94
src/devices/machine/tube.h
Normal file
@ -0,0 +1,94 @@
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// license:BSD-3-Clause
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// copyright-holders:Nigel Barnes
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/**********************************************************************
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Acorn Tube ULA emulation
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**********************************************************************/
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#ifndef MAME_MACHINE_TUBE_H
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#define MAME_MACHINE_TUBE_H
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#pragma once
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//**************************************************************************
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// INTERFACE CONFIGURATION MACROS
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//**************************************************************************
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#define MCFG_TUBE_ADD(_tag) \
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MCFG_DEVICE_ADD(_tag, TUBE, 0);
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#define MCFG_TUBE_HIRQ_HANDLER(_devcb) \
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devcb = &tube_device::set_hirq_handler(*device, DEVCB_##_devcb);
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#define MCFG_TUBE_PNMI_HANDLER(_devcb) \
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devcb = &tube_device::set_pnmi_handler(*device, DEVCB_##_devcb);
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#define MCFG_TUBE_PIRQ_HANDLER(_devcb) \
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devcb = &tube_device::set_pirq_handler(*device, DEVCB_##_devcb);
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#define MCFG_TUBE_DRQ_HANDLER(_devcb) \
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devcb = &tube_device::set_drq_handler(*device, DEVCB_##_devcb);
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//**************************************************************************
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// TYPE DEFINITIONS
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//**************************************************************************
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// ======================> tube_device
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class tube_device : public device_t
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{
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public:
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// construction/destruction
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tube_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
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// callbacks
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template <class Object> static devcb_base &set_hirq_handler(device_t &device, Object &&cb) { return downcast<tube_device &>(device).m_hirq_handler.set_callback(std::forward<Object>(cb)); }
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template <class Object> static devcb_base &set_pnmi_handler(device_t &device, Object &&cb) { return downcast<tube_device &>(device).m_pnmi_handler.set_callback(std::forward<Object>(cb)); }
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template <class Object> static devcb_base &set_pirq_handler(device_t &device, Object &&cb) { return downcast<tube_device &>(device).m_pirq_handler.set_callback(std::forward<Object>(cb)); }
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template <class Object> static devcb_base &set_drq_handler(device_t &device, Object &&cb) { return downcast<tube_device &>(device).m_drq_handler.set_callback(std::forward<Object>(cb)); }
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DECLARE_READ8_MEMBER(host_r);
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DECLARE_WRITE8_MEMBER(host_w);
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DECLARE_READ8_MEMBER(parasite_r);
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DECLARE_WRITE8_MEMBER(parasite_w);
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protected:
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// device-level overrides
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virtual void device_start() override;
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virtual void device_reset() override;
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private:
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uint8_t m_ph1[24];
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uint8_t m_ph2;
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uint8_t m_ph3[2];
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uint8_t m_ph4;
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uint8_t m_hp1;
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uint8_t m_hp2;
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uint8_t m_hp3[2];
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uint8_t m_hp4;
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uint8_t m_hstat[4];
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uint8_t m_pstat[4];
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uint8_t m_r1stat;
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int m_ph1pos;
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int m_ph3pos;
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int m_hp3pos;
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void update_interrupts();
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devcb_write_line m_hirq_handler;
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devcb_write_line m_pnmi_handler;
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devcb_write_line m_pirq_handler;
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devcb_write_line m_drq_handler;
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};
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// device type definition
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DECLARE_DEVICE_TYPE(TUBE, tube_device)
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#endif // MAME_MACHINE_TUBE_H
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Block a user