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https://github.com/holub/mame
synced 2025-10-06 17:08:28 +03:00
AM_BASE_LEGACY breathes its last.
This commit is contained in:
Aaron Giles
parent
0343824418
commit
c9e2a03013
@ -736,9 +736,6 @@ void _class :: _name(address_map &map, const device_t &device) \
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#define AM_SHARE(_tag) \
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curentry->set_share(_tag); \
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#define AM_BASE_LEGACY(_base) \
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curentry->set_baseptr(_base); \
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// common shortcuts
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#define AM_ROMBANK(_bank) AM_READ_BANK(_bank)
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@ -162,6 +162,11 @@ enum
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static UINT8 *t5182_sharedram;
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static int irqstate;
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void t5182_init(running_machine &machine)
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{
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t5182_sharedram = reinterpret_cast<UINT8 *>(machine.root_device().memshare("t5182_sharedram")->ptr());
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}
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READ8_HANDLER(t5182_sharedram_r)
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{
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return t5182_sharedram[offset];
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@ -298,7 +303,7 @@ const ym2151_interface t5182_ym2151_interface =
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ADDRESS_MAP_START( t5182_map, AS_PROGRAM, 8, driver_device )
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AM_RANGE(0x0000, 0x1fff) AM_ROM // internal ROM
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AM_RANGE(0x2000, 0x27ff) AM_RAM AM_MIRROR(0x1800) // internal RAM
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AM_RANGE(0x4000, 0x40ff) AM_RAM AM_MIRROR(0x3F00) AM_BASE_LEGACY(&t5182_sharedram) // 2016 with four 74ls245s, one each for main and t5182 address and data. pins 23, 22, 20, 19, 18 are all tied low so only 256 bytes are usable
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AM_RANGE(0x4000, 0x40ff) AM_RAM AM_MIRROR(0x3F00) AM_SHARE("t5182_sharedram") // 2016 with four 74ls245s, one each for main and t5182 address and data. pins 23, 22, 20, 19, 18 are all tied low so only 256 bytes are usable
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AM_RANGE(0x8000, 0xffff) AM_ROM // external ROM
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ADDRESS_MAP_END
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@ -5,6 +5,8 @@
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#define CPUTAG_T5182 "t5182"
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#define T5182COINPORT "T5182_COIN"
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void t5182_init(running_machine &machine);
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ADDRESS_MAP_EXTERN( t5182_map, 8 );
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ADDRESS_MAP_EXTERN( t5182_io, 8 );
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@ -276,11 +276,11 @@ static READ32_HANDLER( aleck_dips_r )
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*/
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static ADDRESS_MAP_START( n64_map, AS_PROGRAM, 32, n64_state )
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AM_RANGE(0x00000000, 0x007fffff) AM_RAM /*AM_MIRROR(0xc0000000)*/ AM_BASE_LEGACY(&rdram) // RDRAM
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AM_RANGE(0x00000000, 0x007fffff) AM_RAM /*AM_MIRROR(0xc0000000)*/ AM_SHARE("rdram") // RDRAM
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AM_RANGE(0x03f00000, 0x03f00027) AM_DEVREADWRITE("rcp", n64_periphs, rdram_reg_r, rdram_reg_w)
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AM_RANGE(0x04000000, 0x04000fff) AM_RAM AM_SHARE("dmem") // RSP DMEM
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AM_RANGE(0x04001000, 0x04001fff) AM_RAM AM_SHARE("imem") // RSP IMEM
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AM_RANGE(0x04000000, 0x04000fff) AM_RAM AM_SHARE("rsp_dmem") // RSP DMEM
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AM_RANGE(0x04001000, 0x04001fff) AM_RAM AM_SHARE("rsp_imem") // RSP IMEM
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AM_RANGE(0x04040000, 0x040fffff) AM_DEVREADWRITE_LEGACY("rsp", n64_sp_reg_r, n64_sp_reg_w) // RSP
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AM_RANGE(0x04100000, 0x041fffff) AM_DEVREADWRITE_LEGACY("rsp", n64_dp_reg_r, n64_dp_reg_w) // RDP
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AM_RANGE(0x04300000, 0x043fffff) AM_DEVREADWRITE("rcp", n64_periphs, mi_reg_r, mi_reg_w) // MIPS Interface
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@ -305,10 +305,10 @@ static ADDRESS_MAP_START( n64_map, AS_PROGRAM, 32, n64_state )
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ADDRESS_MAP_END
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static ADDRESS_MAP_START( rsp_map, AS_PROGRAM, 32, n64_state )
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AM_RANGE(0x00000000, 0x00000fff) AM_RAM AM_SHARE("dmem")
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AM_RANGE(0x00001000, 0x00001fff) AM_RAM AM_SHARE("imem")
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AM_RANGE(0x04000000, 0x04000fff) AM_RAM AM_BASE_LEGACY(&rsp_dmem) AM_SHARE("dmem")
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AM_RANGE(0x04001000, 0x04001fff) AM_RAM AM_BASE_LEGACY(&rsp_imem) AM_SHARE("imem")
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AM_RANGE(0x00000000, 0x00000fff) AM_RAM AM_SHARE("rsp_dmem")
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AM_RANGE(0x00001000, 0x00001fff) AM_RAM AM_SHARE("rsp_imem")
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AM_RANGE(0x04000000, 0x04000fff) AM_RAM AM_SHARE("rsp_dmem")
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AM_RANGE(0x04001000, 0x04001fff) AM_RAM AM_SHARE("rsp_imem")
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ADDRESS_MAP_END
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static INPUT_PORTS_START( aleck64 )
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@ -408,6 +408,8 @@ DRIVER_INIT_MEMBER(darkmist_state,darkmist)
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UINT8 *buffer = auto_alloc_array(machine(), UINT8, 0x10000);
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UINT8 *decrypt = auto_alloc_array(machine(), UINT8, 0x8000);
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t5182_init(machine());
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decrypt_gfx(machine());
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decrypt_snd(machine());
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@ -1213,7 +1213,7 @@ static ADDRESS_MAP_START( gx_type3_map, AS_PROGRAM, 32, konamigx_state )
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//AM_RANGE(0xcc0000, 0xcc0007) AM_WRITE(type4_prot_w)
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AM_RANGE(0xe00000, 0xe0001f) AM_RAM AM_SHARE("k053936_0_ctrl")
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//AM_RANGE(0xe20000, 0xe20003) AM_WRITENOP
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AM_RANGE(0xe40000, 0xe40003) AM_WRITE(konamigx_type3_psac2_bank_w) AM_BASE_LEGACY(&konamigx_type3_psac2_bank)
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AM_RANGE(0xe40000, 0xe40003) AM_WRITE(konamigx_type3_psac2_bank_w) AM_SHARE("psac2_bank")
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AM_RANGE(0xe60000, 0xe60fff) AM_RAM AM_SHARE("k053936_0_line")
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AM_RANGE(0xe80000, 0xe83fff) AM_RAM AM_SHARE("paletteram") // main monitor palette
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AM_RANGE(0xea0000, 0xea3fff) AM_RAM AM_SHARE("subpaletteram")
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@ -363,7 +363,7 @@ static ADDRESS_MAP_START( ms32_map, AS_PROGRAM, 32, ms32_state )
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AM_RANGE(0xfce00034, 0xfce00037) AM_WRITENOP // irq ack?
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AM_RANGE(0xfce00038, 0xfce0003b) AM_WRITE(reset_sub_w)
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AM_RANGE(0xfce00050, 0xfce0005f) AM_WRITENOP // watchdog? I haven't investigated
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// AM_RANGE(0xfce00000, 0xfce0007f) AM_WRITEONLY AM_BASE_LEGACY(&ms32_fce00000) /* registers not ram? */
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// AM_RANGE(0xfce00000, 0xfce0007f) AM_WRITEONLY AM_SHARE("ms32_fce00000") /* registers not ram? */
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AM_RANGE(0xfce00000, 0xfce00003) AM_WRITE(ms32_gfxctrl_w) /* flip screen + other unknown bits */
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AM_RANGE(0xfce00280, 0xfce0028f) AM_WRITE(ms32_brightness_w) // global brightness control
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/**/AM_RANGE(0xfce00600, 0xfce0065f) AM_RAM AM_SHARE("roz_ctrl") /* roz control registers */
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@ -250,6 +250,8 @@ ROM_END
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DRIVER_INIT_MEMBER(mustache_state,mustache)
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{
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t5182_init(machine());
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int i;
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int G1 = machine().root_device().memregion("gfx1")->bytes()/3;
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@ -594,8 +594,8 @@ static ADDRESS_MAP_START( namcos2_68k_default_cpu_board_am, AS_PROGRAM, 16, namc
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AM_RANGE(0x440000, 0x44ffff) AM_READWRITE(paletteram_word_r,paletteram_word_w) AM_SHARE("paletteram")
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AM_RANGE(0x460000, 0x460fff) AM_READWRITE(dpram_word_r,dpram_word_w)
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AM_RANGE(0x468000, 0x468fff) AM_READWRITE(dpram_word_r,dpram_word_w) /* mirror */
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AM_RANGE(0x480000, 0x483fff) AM_READWRITE_LEGACY(namcos2_68k_serial_comms_ram_r,namcos2_68k_serial_comms_ram_w) AM_BASE_LEGACY(&namcos2_68k_serial_comms_ram)
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AM_RANGE(0x4a0000, 0x4a000f) AM_READWRITE_LEGACY(namcos2_68k_serial_comms_ctrl_r,namcos2_68k_serial_comms_ctrl_w)
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AM_RANGE(0x480000, 0x483fff) AM_READWRITE(serial_comms_ram_r,serial_comms_ram_w) AM_SHARE("serialram")
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AM_RANGE(0x4a0000, 0x4a000f) AM_READWRITE(serial_comms_ctrl_r,serial_comms_ctrl_w)
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ADDRESS_MAP_END
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/*************************************************************/
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@ -1582,7 +1582,7 @@ static ADDRESS_MAP_START( naomi_map, AS_PROGRAM, 64, dc_state )
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AM_RANGE(0x08000000, 0x09ffffff) AM_MIRROR(0x02000000) AM_NOP // 'Unassigned'
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/* Area 3 */
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AM_RANGE(0x0c000000, 0x0dffffff) AM_MIRROR(0xa2000000) AM_RAM AM_BASE_LEGACY(&naomi_ram64)
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AM_RANGE(0x0c000000, 0x0dffffff) AM_MIRROR(0xa2000000) AM_RAM AM_SHARE("dc_ram")
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/* Area 4 */
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AM_RANGE(0x10000000, 0x107fffff) AM_MIRROR(0x02000000) AM_WRITE_LEGACY(ta_fifo_poly_w )
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@ -1644,7 +1644,7 @@ static ADDRESS_MAP_START( naomi2_map, AS_PROGRAM, 64, dc_state )
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AM_RANGE(0x0a000000, 0x0bffffff) AM_RAM AM_SHARE("elan_ram") // T&L chip RAM
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/* Area 3 */
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AM_RANGE(0x0c000000, 0x0dffffff) AM_MIRROR(0xa2000000) AM_RAM AM_BASE_LEGACY(&naomi_ram64)
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AM_RANGE(0x0c000000, 0x0dffffff) AM_MIRROR(0xa2000000) AM_RAM AM_SHARE("dc_ram")
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/* Area 4 */
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AM_RANGE(0x10000000, 0x107fffff) AM_WRITE_LEGACY(ta_fifo_poly_w )
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@ -1786,13 +1786,13 @@ static ADDRESS_MAP_START( aw_map, AS_PROGRAM, 64, dc_state )
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AM_RANGE(0x08000000, 0x0bffffff) AM_NOP // 'Unassigned'
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/* Area 3 */
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AM_RANGE(0x0c000000, 0x0cffffff) AM_RAM AM_BASE_LEGACY(&naomi_ram64) AM_SHARE("share4")
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AM_RANGE(0x0d000000, 0x0dffffff) AM_RAM AM_SHARE("share4")// extra ram on Naomi (mirror on DC)
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AM_RANGE(0x0e000000, 0x0effffff) AM_RAM AM_SHARE("share4")// mirror
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AM_RANGE(0x0f000000, 0x0fffffff) AM_RAM AM_SHARE("share4")// mirror
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AM_RANGE(0x0c000000, 0x0cffffff) AM_RAM AM_SHARE("dc_ram")
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AM_RANGE(0x0d000000, 0x0dffffff) AM_RAM AM_SHARE("dc_ram")// extra ram on Naomi (mirror on DC)
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AM_RANGE(0x0e000000, 0x0effffff) AM_RAM AM_SHARE("dc_ram")// mirror
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AM_RANGE(0x0f000000, 0x0fffffff) AM_RAM AM_SHARE("dc_ram")// mirror
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AM_RANGE(0x8c000000, 0x8cffffff) AM_RAM AM_SHARE("share4") // RAM access through cache
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AM_RANGE(0x8d000000, 0x8dffffff) AM_RAM AM_SHARE("share4") // RAM access through cache
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AM_RANGE(0x8c000000, 0x8cffffff) AM_RAM AM_SHARE("dc_ram") // RAM access through cache
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AM_RANGE(0x8d000000, 0x8dffffff) AM_RAM AM_SHARE("dc_ram") // RAM access through cache
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/* Area 4 - half the texture memory, like dreamcast, not naomi */
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AM_RANGE(0x10000000, 0x107fffff) AM_MIRROR(0x02000000) AM_WRITE_LEGACY(ta_fifo_poly_w )
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@ -167,7 +167,6 @@
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*************************************/
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static UINT8 *memcard_data;
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static UINT16 *save_ram;
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static const char *audio_banks[4] =
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{
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@ -499,7 +498,7 @@ WRITE16_MEMBER(neogeo_state::save_ram_w)
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{
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if (m_save_ram_unlocked)
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COMBINE_DATA(&save_ram[offset]);
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COMBINE_DATA(&m_save_ram[offset]);
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}
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@ -992,7 +991,7 @@ static MACHINE_START( neogeo )
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neogeo_state *state = machine.driver_data<neogeo_state>();
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/* configure NVRAM */
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machine.device<nvram_device>("saveram")->set_base(save_ram, 0x10000);
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machine.device<nvram_device>("saveram")->set_base(state->m_save_ram, 0x10000);
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/* set the BIOS bank */
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state->membank(NEOGEO_BANK_BIOS)->set_base(state->memregion("mainbios")->base());
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@ -1105,7 +1104,7 @@ static ADDRESS_MAP_START( main_map, AS_PROGRAM, 16, neogeo_state )
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AM_RANGE(0x400000, 0x401fff) AM_MIRROR(0x3fe000) AM_READWRITE(neogeo_paletteram_r, neogeo_paletteram_w)
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AM_RANGE(0x800000, 0x800fff) AM_READWRITE(memcard_r, memcard_w)
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AM_RANGE(0xc00000, 0xc1ffff) AM_MIRROR(0x0e0000) AM_ROMBANK(NEOGEO_BANK_BIOS)
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AM_RANGE(0xd00000, 0xd0ffff) AM_MIRROR(0x0f0000) AM_RAM_WRITE(save_ram_w) AM_BASE_LEGACY(&save_ram)
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AM_RANGE(0xd00000, 0xd0ffff) AM_MIRROR(0x0f0000) AM_RAM_WRITE(save_ram_w) AM_SHARE("save_ram")
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AM_RANGE(0xe00000, 0xffffff) AM_READ(neogeo_unmapped_r)
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ADDRESS_MAP_END
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@ -882,8 +882,8 @@ static ADDRESS_MAP_START( tdragon_map, AS_PROGRAM, 16, nmk16_state )
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AM_RANGE(0x044022, 0x044023) AM_READNOP /* No Idea */
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// AM_RANGE(0x0b0000, 0x0b7fff) AM_RAM /* Work RAM */
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// AM_RANGE(0x0b8000, 0x0b8fff) AM_RAM AM_SHARE("spriteram") /* Sprite RAM */
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// AM_RANGE(0x0b9000, 0x0bdfff) AM_RAM AM_BASE_LEGACY(&nmk16_mcu_work_ram) /* Work RAM */
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// AM_RANGE(0x0be000, 0x0befff) AM_READWRITE(mcu_shared_r,tdragon_mcu_shared_w) AM_BASE_LEGACY(&nmk16_mcu_shared_ram) /* Work RAM */
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// AM_RANGE(0x0b9000, 0x0bdfff) AM_RAM AM_SHARE("mcu_work_ram") /* Work RAM */
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// AM_RANGE(0x0be000, 0x0befff) AM_READWRITE(mcu_shared_r,tdragon_mcu_shared_w) AM_SHARE("mcu_shared_ram") /* Work RAM */
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// AM_RANGE(0x0bf000, 0x0bffff) AM_RAM /* Work RAM */
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AM_RANGE(0x0b0000, 0x0bffff) AM_RAM_WRITE(tdragon_mainram_w ) AM_SHARE("mainram")
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AM_RANGE(0x0c0000, 0x0c0001) AM_READ_PORT("IN0")
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@ -619,6 +619,8 @@ DRIVER_INIT_MEMBER(panicr_state,panicr)
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int size;
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int i,j;
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t5182_init(machine());
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rom = machine().root_device().memregion("gfx1")->base();
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size = machine().root_device().memregion("gfx1")->bytes();
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@ -191,9 +191,6 @@ Notes:
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#include "includes/pgm.h"
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UINT16 *pgm_mainram;
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READ16_MEMBER(pgm_state::pgm_videoram_r)
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{
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@ -320,7 +317,7 @@ ADDRESS_MAP_END
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ADDRESS_MAP_START( pgm_base_mem, AS_PROGRAM, 16, pgm_state )
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AM_RANGE(0x700006, 0x700007) AM_WRITENOP // Watchdog?
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AM_RANGE(0x800000, 0x81ffff) AM_RAM AM_MIRROR(0x0e0000) AM_BASE_LEGACY(&pgm_mainram) AM_SHARE("sram") /* Main Ram */
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AM_RANGE(0x800000, 0x81ffff) AM_RAM AM_MIRROR(0x0e0000) AM_SHARE("sram") /* Main Ram */
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AM_RANGE(0x900000, 0x907fff) AM_MIRROR(0x0f8000) AM_READWRITE(pgm_videoram_r, pgm_videoram_w) AM_SHARE("videoram") /* IGS023 VIDEO CHIP */
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AM_RANGE(0xa00000, 0xa011ff) AM_RAM_WRITE(paletteram_xRRRRRGGGGGBBBBB_word_w) AM_SHARE("paletteram")
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@ -276,7 +276,7 @@ static ADDRESS_MAP_START( vcarn_map, AS_PROGRAM, 8, spool99_state )
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AM_RANGE(0xa800, 0xabff) AM_RAM_WRITE(paletteram_xxxxBBBBGGGGRRRR_byte_le_w) AM_SHARE("paletteram")
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AM_RANGE(0xb000, 0xdfff) AM_RAM
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// AM_RANGE(0xdf00, 0xdfff) AM_READWRITE(vcarn_io_r,vcarn_io_w) AM_BASE_LEGACY(&vcarn_io)
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// AM_RANGE(0xdf00, 0xdfff) AM_READWRITE(vcarn_io_r,vcarn_io_w) AM_SHARE("vcarn_io")
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AM_RANGE(0xe000, 0xefff) AM_RAM_WRITE(spool99_vram_w) AM_SHARE("vram")
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AM_RANGE(0xf000, 0xffff) AM_RAM_WRITE(spool99_cram_w) AM_SHARE("cram")
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ADDRESS_MAP_END
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@ -672,7 +672,7 @@ static ADDRESS_MAP_START( tmmjprd_map, AS_PROGRAM, 32, tmmjprd_state )
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AM_RANGE(0x000000, 0x1fffff) AM_ROM
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AM_RANGE(0x200010, 0x200013) AM_READ(randomtmmjprds) // gfx chip status?
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/* check these are used .. */
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// AM_RANGE(0x200010, 0x200013) AM_WRITEONLY AM_BASE_LEGACY(&tmmjprd_viewregs0 )
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// AM_RANGE(0x200010, 0x200013) AM_WRITEONLY AM_SHARE("tmmjprd_viewregs0")
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AM_RANGE(0x200100, 0x200117) AM_WRITEONLY AM_SHARE("tilemap_regs.0" ) // tilemap regs1
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AM_RANGE(0x200120, 0x200137) AM_WRITEONLY AM_SHARE("tilemap_regs.1" ) // tilemap regs2
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AM_RANGE(0x200140, 0x200157) AM_WRITEONLY AM_SHARE("tilemap_regs.2" ) // tilemap regs3
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@ -681,12 +681,12 @@ static ADDRESS_MAP_START( tmmjprd_map, AS_PROGRAM, 32, tmmjprd_state )
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// AM_RANGE(0x200300, 0x200303) AM_WRITE_LEGACY(tmmjprd_rombank_w) // used during rom testing, rombank/area select + something else?
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AM_RANGE(0x20040c, 0x20040f) AM_WRITE(tmmjprd_brt_1_w)
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AM_RANGE(0x200410, 0x200413) AM_WRITE(tmmjprd_brt_2_w)
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// AM_RANGE(0x200500, 0x200503) AM_WRITEONLY AM_BASE_LEGACY(&tmmjprd_viewregs7 )
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// AM_RANGE(0x200700, 0x20070f) AM_WRITE(tmmjprd_blitter_w) AM_BASE_LEGACY(&tmmjprd_blitterregs )
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// AM_RANGE(0x200800, 0x20080f) AM_WRITEONLY AM_BASE_LEGACY(&tmmjprd_viewregs9 ) // never changes?
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// AM_RANGE(0x200500, 0x200503) AM_WRITEONLY AM_SHARE("tmmjprd_viewregs7")
|
||||
// AM_RANGE(0x200700, 0x20070f) AM_WRITE(tmmjprd_blitter_w) AM_SHARE("tmmjprd_blitterregs")
|
||||
// AM_RANGE(0x200800, 0x20080f) AM_WRITEONLY AM_SHARE("tmmjprd_viewregs9") // never changes?
|
||||
AM_RANGE(0x200900, 0x2009ff) AM_DEVREADWRITE16("i5000snd", i5000snd_device, read, write, 0xffffffff)
|
||||
/* hmm */
|
||||
// AM_RANGE(0x279700, 0x279713) AM_WRITEONLY AM_BASE_LEGACY(&tmmjprd_viewregs10 )
|
||||
// AM_RANGE(0x279700, 0x279713) AM_WRITEONLY AM_SHARE("tmmjprd_viewregs10")
|
||||
/* tilemaps */
|
||||
AM_RANGE(0x280000, 0x283fff) AM_READWRITE(tmmjprd_tilemap0_r,tmmjprd_tilemap0_w)
|
||||
AM_RANGE(0x284000, 0x287fff) AM_READWRITE(tmmjprd_tilemap1_r,tmmjprd_tilemap1_w)
|
||||
|
||||
@ -15,6 +15,7 @@ class dc_state : public driver_device
|
||||
dc_framebuffer_ram(*this, "frameram"),
|
||||
dc_texture_ram(*this, "dc_texture_ram"),
|
||||
dc_sound_ram(*this, "dc_sound_ram"),
|
||||
dc_ram(*this, "dc_ram"),
|
||||
pvr2_texture_ram(*this, "textureram2"),
|
||||
pvr2_framebuffer_ram(*this, "frameram2"),
|
||||
elan_ram(*this, "elan_ram") { }
|
||||
@ -23,6 +24,7 @@ class dc_state : public driver_device
|
||||
required_shared_ptr<UINT64> dc_texture_ram; // '64-bit access area'
|
||||
|
||||
required_shared_ptr<UINT32> dc_sound_ram;
|
||||
required_shared_ptr<UINT64> dc_ram;
|
||||
|
||||
/* machine related */
|
||||
UINT32 dc_rtcregister[4];
|
||||
|
||||
@ -8,7 +8,8 @@ public:
|
||||
m_psacram(*this,"psacram"),
|
||||
m_subpaletteram32(*this,"subpaletteram"),
|
||||
m_k053936_0_ctrl(*this,"k053936_0_ctrl",32),
|
||||
m_k053936_0_linectrl(*this,"k053936_0_line",32)
|
||||
m_k053936_0_linectrl(*this,"k053936_0_line",32),
|
||||
m_konamigx_type3_psac2_bank(*this,"psac2_bank")
|
||||
{ }
|
||||
|
||||
required_device<cpu_device> m_maincpu;
|
||||
@ -17,6 +18,7 @@ public:
|
||||
optional_shared_ptr<UINT32> m_subpaletteram32;
|
||||
optional_shared_ptr<UINT16> m_k053936_0_ctrl;
|
||||
optional_shared_ptr<UINT16> m_k053936_0_linectrl;
|
||||
optional_shared_ptr<UINT32> m_konamigx_type3_psac2_bank;
|
||||
DECLARE_WRITE32_MEMBER(esc_w);
|
||||
DECLARE_WRITE32_MEMBER(eeprom_w);
|
||||
DECLARE_WRITE32_MEMBER(control_w);
|
||||
@ -148,11 +150,7 @@ SCREEN_UPDATE_RGB32(konamigx);
|
||||
SCREEN_UPDATE_RGB32(konamigx_left);
|
||||
SCREEN_UPDATE_RGB32(konamigx_right);
|
||||
|
||||
#ifdef UNUSED_FUNCTION
|
||||
#endif
|
||||
|
||||
extern int konamigx_current_frame;
|
||||
extern UINT32* konamigx_type3_psac2_bank;
|
||||
|
||||
|
||||
/*----------- defined in machine/konamigx.c -----------*/
|
||||
|
||||
@ -105,9 +105,11 @@ class md_base_state : public driver_device
|
||||
public:
|
||||
md_base_state(const machine_config &mconfig, device_type type, const char *tag)
|
||||
: driver_device(mconfig, type, tag),
|
||||
m_vdp(*this,"gen_vdp")
|
||||
m_vdp(*this,"gen_vdp"),
|
||||
m_megadrive_ram(*this,"megadrive_ram")
|
||||
{ }
|
||||
required_device<sega_genesis_vdp_device> m_vdp;
|
||||
optional_shared_ptr<UINT16> m_megadrive_ram;
|
||||
|
||||
DECLARE_DRIVER_INIT(megadriv_c2);
|
||||
DECLARE_DRIVER_INIT(megadrie);
|
||||
@ -445,7 +447,10 @@ class segacd_state : public _32x_state // use _32x_state as base to make easier
|
||||
{
|
||||
public:
|
||||
segacd_state(const machine_config &mconfig, device_type type, const char *tag)
|
||||
: _32x_state(mconfig, type, tag) { }
|
||||
: _32x_state(mconfig, type, tag),
|
||||
m_font_bits(*this,"segacd_font") { }
|
||||
|
||||
required_shared_ptr<UINT16> m_font_bits;
|
||||
};
|
||||
|
||||
extern int sega_cd_connected;
|
||||
|
||||
@ -188,6 +188,7 @@ public:
|
||||
m_dpram(*this, "dpram"),
|
||||
m_paletteram(*this, "paletteram"),
|
||||
m_spriteram(*this, "spriteram"),
|
||||
m_serial_comms_ram(*this, "serialram"),
|
||||
m_rozram(*this, "rozram"),
|
||||
m_roz_ctrl(*this, "rozctrl"),
|
||||
m_c45_road(*this, "c45_road")
|
||||
@ -250,6 +251,10 @@ public:
|
||||
DECLARE_WRITE16_MEMBER( rozram_word_w );
|
||||
DECLARE_READ16_MEMBER( gfx_ctrl_r );
|
||||
DECLARE_WRITE16_MEMBER( gfx_ctrl_w );
|
||||
DECLARE_READ16_MEMBER( serial_comms_ram_r );
|
||||
DECLARE_WRITE16_MEMBER( serial_comms_ram_w );
|
||||
DECLARE_READ16_MEMBER( serial_comms_ctrl_r );
|
||||
DECLARE_WRITE16_MEMBER( serial_comms_ctrl_w );
|
||||
|
||||
void draw_sprite_init();
|
||||
void update_palette();
|
||||
@ -264,10 +269,12 @@ public:
|
||||
required_shared_ptr<UINT8> m_dpram; /* 2Kx8 */
|
||||
required_shared_ptr<UINT16> m_paletteram;
|
||||
optional_shared_ptr<UINT16> m_spriteram;
|
||||
optional_shared_ptr<UINT16> m_serial_comms_ram;
|
||||
optional_shared_ptr<UINT16> m_rozram;
|
||||
optional_shared_ptr<UINT16> m_roz_ctrl;
|
||||
tilemap_t *m_tilemap_roz;
|
||||
UINT16 m_gfx_ctrl;
|
||||
UINT16 m_serial_comms_ctrl[0x8];
|
||||
|
||||
optional_device<namco_c45_road_device> m_c45_road;
|
||||
};
|
||||
@ -308,16 +315,6 @@ READ16_HANDLER( namcos2_68k_eeprom_r );
|
||||
/**************************************************************/
|
||||
READ16_HANDLER( namcos2_68k_data_rom_r );
|
||||
|
||||
/**************************************************************/
|
||||
/* Shared serial communications processory (CPU5 ????) */
|
||||
/**************************************************************/
|
||||
READ16_HANDLER( namcos2_68k_serial_comms_ram_r );
|
||||
WRITE16_HANDLER( namcos2_68k_serial_comms_ram_w );
|
||||
READ16_HANDLER( namcos2_68k_serial_comms_ctrl_r );
|
||||
WRITE16_HANDLER( namcos2_68k_serial_comms_ctrl_w );
|
||||
|
||||
extern UINT16 *namcos2_68k_serial_comms_ram;
|
||||
|
||||
/**************************************************************/
|
||||
/* Shared protection/random number generator */
|
||||
/**************************************************************/
|
||||
|
||||
@ -25,8 +25,6 @@ extern void naomi_game_decrypt(running_machine& machine, UINT64 key, UINT8* regi
|
||||
|
||||
|
||||
|
||||
extern UINT64 *naomi_ram64;
|
||||
|
||||
extern int jvsboard_type;
|
||||
extern UINT16 actel_id;
|
||||
|
||||
|
||||
@ -36,11 +36,12 @@ class neogeo_state : public driver_device
|
||||
{
|
||||
public:
|
||||
neogeo_state(const machine_config &mconfig, device_type type, const char *tag)
|
||||
: driver_device(mconfig, type, tag) { }
|
||||
: driver_device(mconfig, type, tag),
|
||||
m_save_ram(*this, "save_ram") { }
|
||||
|
||||
/* memory pointers */
|
||||
// UINT8 *memcard_data; // this currently uses generic handlers
|
||||
// UINT16 *save_ram; // this currently uses generic handlers
|
||||
required_shared_ptr<UINT16> m_save_ram; // this currently uses generic handlers
|
||||
|
||||
/* video-related */
|
||||
UINT8 *m_sprite_gfx;
|
||||
|
||||
@ -16,7 +16,8 @@ public:
|
||||
: driver_device(mconfig, type, tag),
|
||||
m_videoregs(*this, "videoregs"),
|
||||
m_videoram(*this, "videoram"),
|
||||
m_z80_mainram(*this, "z80_mainram")
|
||||
m_z80_mainram(*this, "z80_mainram"),
|
||||
m_mainram(*this, "sram")
|
||||
{
|
||||
m_irq4_disabled = 0;
|
||||
}
|
||||
@ -25,7 +26,7 @@ public:
|
||||
required_shared_ptr<UINT16> m_videoregs;
|
||||
required_shared_ptr<UINT16> m_videoram;
|
||||
required_shared_ptr<UINT8> m_z80_mainram;
|
||||
// UINT16 * m_mainram; // currently this is also used by nvram handler
|
||||
required_shared_ptr<UINT16> m_mainram;
|
||||
UINT16 * m_bg_videoram;
|
||||
UINT16 * m_tx_videoram;
|
||||
UINT16 * m_rowscrollram;
|
||||
@ -299,8 +300,6 @@ public:
|
||||
|
||||
|
||||
|
||||
extern UINT16 *pgm_mainram; // used by nvram handler, we cannot move it to driver data struct
|
||||
|
||||
/*----------- defined in drivers/pgm.c -----------*/
|
||||
|
||||
void pgm_basic_init( running_machine &machine, bool set_bank = true );
|
||||
|
||||
@ -2236,6 +2236,12 @@ void segacd_init_main_cpu( running_machine& machine )
|
||||
{
|
||||
address_space* space = machine.device("maincpu")->memory().space(AS_PROGRAM);
|
||||
|
||||
segacd_font_bits = reinterpret_cast<UINT16 *>(machine.root_device().memshare("segacd_font")->ptr());
|
||||
segacd_backupram = reinterpret_cast<UINT16 *>(machine.root_device().memshare("backupram")->ptr());
|
||||
segacd_dataram = reinterpret_cast<UINT16 *>(machine.root_device().memshare("dataram")->ptr());
|
||||
segacd_dataram2 = reinterpret_cast<UINT16 *>(machine.root_device().memshare("dataram2")->ptr());
|
||||
segacd_4meg_prgram = reinterpret_cast<UINT16 *>(machine.root_device().memshare("segacd_program")->ptr());
|
||||
|
||||
segacd_4meg_prgbank = 0;
|
||||
|
||||
|
||||
@ -3008,12 +3014,12 @@ READ16_HANDLER( segacd_font_converted_r )
|
||||
}
|
||||
|
||||
ADDRESS_MAP_START( segacd_map, AS_PROGRAM, 16, driver_device )
|
||||
AM_RANGE(0x000000, 0x07ffff) AM_RAM AM_BASE_LEGACY(&segacd_4meg_prgram)
|
||||
AM_RANGE(0x000000, 0x07ffff) AM_RAM AM_SHARE("segacd_program")
|
||||
|
||||
AM_RANGE(0x080000, 0x0bffff) AM_READWRITE_LEGACY(segacd_sub_dataram_part1_r, segacd_sub_dataram_part1_w) AM_BASE_LEGACY(&segacd_dataram)
|
||||
AM_RANGE(0x0c0000, 0x0dffff) AM_READWRITE_LEGACY(segacd_sub_dataram_part2_r, segacd_sub_dataram_part2_w) AM_BASE_LEGACY(&segacd_dataram2)
|
||||
AM_RANGE(0x080000, 0x0bffff) AM_READWRITE_LEGACY(segacd_sub_dataram_part1_r, segacd_sub_dataram_part1_w) AM_SHARE("dataram")
|
||||
AM_RANGE(0x0c0000, 0x0dffff) AM_READWRITE_LEGACY(segacd_sub_dataram_part2_r, segacd_sub_dataram_part2_w) AM_SHARE("dataram2")
|
||||
|
||||
AM_RANGE(0xfe0000, 0xfe3fff) AM_READWRITE_LEGACY(segacd_backupram_r,segacd_backupram_w) AM_SHARE("backupram") AM_BASE_LEGACY(&segacd_backupram)// backup RAM, odd bytes only!
|
||||
AM_RANGE(0xfe0000, 0xfe3fff) AM_READWRITE_LEGACY(segacd_backupram_r,segacd_backupram_w) AM_SHARE("backupram") // backup RAM, odd bytes only!
|
||||
|
||||
AM_RANGE(0xff0000, 0xff001f) AM_DEVWRITE8_LEGACY("rfsnd", rf5c68_w, 0x00ff) // PCM, RF5C164
|
||||
AM_RANGE(0xff0020, 0xff003f) AM_DEVREAD8_LEGACY("rfsnd", rf5c68_r, 0x00ff)
|
||||
@ -3038,7 +3044,7 @@ ADDRESS_MAP_START( segacd_map, AS_PROGRAM, 16, driver_device )
|
||||
AM_RANGE(0xff8038, 0xff8041) AM_READ8_LEGACY(segacd_cdd_rx_r,0xffff)
|
||||
AM_RANGE(0xff8042, 0xff804b) AM_WRITE8_LEGACY(segacd_cdd_tx_w,0xffff)
|
||||
AM_RANGE(0xff804c, 0xff804d) AM_READWRITE_LEGACY(segacd_font_color_r, segacd_font_color_w)
|
||||
AM_RANGE(0xff804e, 0xff804f) AM_RAM AM_BASE_LEGACY(&segacd_font_bits)
|
||||
AM_RANGE(0xff804e, 0xff804f) AM_RAM AM_SHARE("segacd_font")
|
||||
AM_RANGE(0xff8050, 0xff8057) AM_READ_LEGACY(segacd_font_converted_r)
|
||||
AM_RANGE(0xff8058, 0xff8059) AM_READWRITE_LEGACY(segacd_stampsize_r, segacd_stampsize_w) // Stamp size
|
||||
AM_RANGE(0xff805a, 0xff805b) AM_READWRITE_LEGACY(segacd_stampmap_base_address_r, segacd_stampmap_base_address_w) // Stamp map base address
|
||||
|
||||
@ -56,7 +56,6 @@ static cpu_device *_genesis_snd_z80_cpu;
|
||||
int genesis_other_hacks = 0; // misc hacks
|
||||
|
||||
timer_device* megadriv_scanline_timer;
|
||||
UINT16* megadrive_ram = NULL;
|
||||
|
||||
struct genesis_z80_vars
|
||||
{
|
||||
@ -577,14 +576,14 @@ static ADDRESS_MAP_START( megadriv_map, AS_PROGRAM, 16, driver_device )
|
||||
AM_RANGE(0xa11200, 0xa11201) AM_WRITE_LEGACY(megadriv_68k_req_z80_reset)
|
||||
|
||||
/* these are fake - remove allocs in VIDEO_START to use these to view ram instead */
|
||||
// AM_RANGE(0xb00000, 0xb0ffff) AM_RAM AM_BASE_LEGACY(&megadrive_vdp_vram)
|
||||
// AM_RANGE(0xb10000, 0xb1007f) AM_RAM AM_BASE_LEGACY(&megadrive_vdp_vsram)
|
||||
// AM_RANGE(0xb10100, 0xb1017f) AM_RAM AM_BASE_LEGACY(&megadrive_vdp_cram)
|
||||
// AM_RANGE(0xb00000, 0xb0ffff) AM_RAM AM_SHARE("megadrive_vdp_vram")
|
||||
// AM_RANGE(0xb10000, 0xb1007f) AM_RAM AM_SHARE("megadrive_vdp_vsram")
|
||||
// AM_RANGE(0xb10100, 0xb1017f) AM_RAM AM_SHARE("megadrive_vdp_cram")
|
||||
|
||||
AM_RANGE(0xc00000, 0xc0001f) AM_DEVREADWRITE("gen_vdp", sega_genesis_vdp_device, megadriv_vdp_r,megadriv_vdp_w)
|
||||
AM_RANGE(0xd00000, 0xd0001f) AM_DEVREADWRITE("gen_vdp", sega_genesis_vdp_device, megadriv_vdp_r,megadriv_vdp_w) // the earth defend
|
||||
|
||||
AM_RANGE(0xe00000, 0xe0ffff) AM_RAM AM_MIRROR(0x1f0000) AM_BASE_LEGACY(&megadrive_ram)
|
||||
AM_RANGE(0xe00000, 0xe0ffff) AM_RAM AM_MIRROR(0x1f0000) AM_SHARE("megadrive_ram")
|
||||
// AM_RANGE(0xff0000, 0xffffff) AM_READONLY
|
||||
/* 0xe00000 - 0xffffff) == MAIN RAM (64kb, Mirrored, most games use ff0000 - ffffff) */
|
||||
ADDRESS_MAP_END
|
||||
@ -883,7 +882,7 @@ static ADDRESS_MAP_START( md_bootleg_map, AS_PROGRAM, 16, driver_device )
|
||||
AM_RANGE(0xc00000, 0xc0001f) AM_DEVREADWRITE("gen_vdp", sega_genesis_vdp_device, megadriv_vdp_r,megadriv_vdp_w)
|
||||
AM_RANGE(0xd00000, 0xd0001f) AM_DEVREADWRITE("gen_vdp", sega_genesis_vdp_device, megadriv_vdp_r,megadriv_vdp_w)
|
||||
|
||||
AM_RANGE(0xe00000, 0xe0ffff) AM_RAM AM_MIRROR(0x1f0000) AM_BASE_LEGACY(&megadrive_ram)
|
||||
AM_RANGE(0xe00000, 0xe0ffff) AM_RAM AM_MIRROR(0x1f0000) AM_SHARE("megadrive_ram")
|
||||
ADDRESS_MAP_END
|
||||
|
||||
MACHINE_CONFIG_DERIVED( md_bootleg, megadriv )
|
||||
@ -1008,8 +1007,8 @@ MACHINE_RESET( megadriv )
|
||||
{
|
||||
// set_refresh_rate(megadriv_framerate);
|
||||
// machine.device("maincpu")->set_clock_scale(0.9950f); /* Fatal Rewind is very fussy... (and doesn't work now anyway, so don't bother with this) */
|
||||
if (megadrive_ram)
|
||||
memset(megadrive_ram,0x00,0x10000);
|
||||
if (state->m_megadrive_ram)
|
||||
memset(state->m_megadrive_ram,0x00,0x10000);
|
||||
}
|
||||
|
||||
megadriv_reset_vdp(machine);
|
||||
|
||||
@ -2404,6 +2404,12 @@ static void n64_machine_stop(running_machine &machine)
|
||||
|
||||
MACHINE_START( n64 )
|
||||
{
|
||||
n64_state *state = machine.driver_data<n64_state>();
|
||||
rdram = reinterpret_cast<UINT32 *>(state->memshare("rdram")->ptr());
|
||||
n64_sram = reinterpret_cast<UINT32 *>(state->memshare("sram")->ptr());
|
||||
rsp_imem = reinterpret_cast<UINT32 *>(state->memshare("rsp_imem")->ptr());
|
||||
rsp_dmem = reinterpret_cast<UINT32 *>(state->memshare("rsp_dmem")->ptr());
|
||||
|
||||
mips3drc_set_options(machine.device("maincpu"), MIPS3DRC_COMPATIBLE_OPTIONS);
|
||||
|
||||
/* configure fast RAM regions for DRC */
|
||||
|
||||
@ -164,20 +164,17 @@ READ16_HANDLER( namcos2_68k_data_rom_r ){
|
||||
/* 68000 Shared serial communications processor (CPU5?) */
|
||||
/**************************************************************/
|
||||
|
||||
static UINT16 namcos2_68k_serial_comms_ctrl[0x8];
|
||||
UINT16 *namcos2_68k_serial_comms_ram;
|
||||
|
||||
READ16_HANDLER( namcos2_68k_serial_comms_ram_r ){
|
||||
return namcos2_68k_serial_comms_ram[offset];
|
||||
READ16_MEMBER( namcos2_state::serial_comms_ram_r ){
|
||||
return m_serial_comms_ram[offset];
|
||||
}
|
||||
|
||||
WRITE16_HANDLER( namcos2_68k_serial_comms_ram_w ){
|
||||
COMBINE_DATA( &namcos2_68k_serial_comms_ram[offset] );
|
||||
WRITE16_MEMBER( namcos2_state::serial_comms_ram_w ){
|
||||
COMBINE_DATA( &m_serial_comms_ram[offset] );
|
||||
}
|
||||
|
||||
READ16_HANDLER( namcos2_68k_serial_comms_ctrl_r )
|
||||
READ16_MEMBER( namcos2_state::serial_comms_ctrl_r )
|
||||
{
|
||||
UINT16 retval = namcos2_68k_serial_comms_ctrl[offset];
|
||||
UINT16 retval = m_serial_comms_ctrl[offset];
|
||||
|
||||
switch(offset){
|
||||
case 0x00:
|
||||
@ -190,9 +187,9 @@ READ16_HANDLER( namcos2_68k_serial_comms_ctrl_r )
|
||||
return retval;
|
||||
}
|
||||
|
||||
WRITE16_HANDLER( namcos2_68k_serial_comms_ctrl_w )
|
||||
WRITE16_MEMBER( namcos2_state::serial_comms_ctrl_w )
|
||||
{
|
||||
COMBINE_DATA( &namcos2_68k_serial_comms_ctrl[offset] );
|
||||
COMBINE_DATA( &m_serial_comms_ctrl[offset] );
|
||||
}
|
||||
|
||||
/*************************************************************/
|
||||
|
||||
@ -22,7 +22,6 @@ hotd2o: bp 0xc0ba1f6, modify work RAM 0xc9c35a8 to be zero, bpclear
|
||||
#include "includes/naomi.h"
|
||||
#include "includes/dc.h"
|
||||
|
||||
UINT64 *naomi_ram64;
|
||||
int jvsboard_type;
|
||||
UINT16 actel_id;
|
||||
|
||||
@ -34,7 +33,7 @@ static READ64_HANDLER( naomi_biose_idle_skip_r )
|
||||
// else
|
||||
// printf("%08x\n", space->device().safe_pc());
|
||||
|
||||
return naomi_ram64[0x2ad238/8];
|
||||
return space->machine().driver_data<dc_state>()->dc_ram[0x2ad238/8];
|
||||
}
|
||||
|
||||
static READ64_HANDLER( naomi_biosh_idle_skip_r )
|
||||
@ -44,7 +43,7 @@ static READ64_HANDLER( naomi_biosh_idle_skip_r )
|
||||
|
||||
// printf("%08x\n", space->device().safe_pc());
|
||||
|
||||
return naomi_ram64[0x2b0600/8];
|
||||
return space->machine().driver_data<dc_state>()->dc_ram[0x2b0600/8];
|
||||
}
|
||||
|
||||
static READ64_HANDLER( naomi2_biose_idle_skip_r )
|
||||
@ -55,7 +54,7 @@ static READ64_HANDLER( naomi2_biose_idle_skip_r )
|
||||
// else
|
||||
// printf("%08x\n", space->device().safe_pc());
|
||||
|
||||
return naomi_ram64[0x2b0600/8];
|
||||
return space->machine().driver_data<dc_state>()->dc_ram[0x2b0600/8];
|
||||
}
|
||||
|
||||
static UINT8 asciihex_to_dec(UINT8 in)
|
||||
@ -246,7 +245,7 @@ static READ64_HANDLER( naomigd_ggxxsla_idle_skip_r )
|
||||
if (space->device().safe_pc()==0x0c0c9adc)
|
||||
space->device().execute().spin_until_time(attotime::from_usec(500));
|
||||
|
||||
return naomi_ram64[0x1aae18/8];
|
||||
return space->machine().driver_data<dc_state>()->dc_ram[0x1aae18/8];
|
||||
}
|
||||
|
||||
DRIVER_INIT_MEMBER(dc_state,ggxxsla)
|
||||
@ -260,7 +259,7 @@ static READ64_HANDLER( naomigd_ggxx_idle_skip_r )
|
||||
if (space->device().safe_pc()==0xc0b5c3c) // or 0xc0bab0c
|
||||
space->device().execute().spin_until_time(attotime::from_usec(500));
|
||||
|
||||
return naomi_ram64[0x1837b8/8];
|
||||
return space->machine().driver_data<dc_state>()->dc_ram[0x1837b8/8];
|
||||
}
|
||||
|
||||
|
||||
@ -277,7 +276,7 @@ static READ64_HANDLER( naomigd_ggxxrl_idle_skip_r )
|
||||
|
||||
//printf("%08x\n", space->device().safe_pc());
|
||||
|
||||
return naomi_ram64[0x18d6c8/8];
|
||||
return space->machine().driver_data<dc_state>()->dc_ram[0x18d6c8/8];
|
||||
}
|
||||
|
||||
DRIVER_INIT_MEMBER(dc_state,ggxxrl)
|
||||
@ -292,7 +291,7 @@ static READ64_HANDLER( naomigd_sfz3ugd_idle_skip_r )
|
||||
if (space->device().safe_pc()==0xc36a2dc)
|
||||
space->device().execute().spin_until_time(attotime::from_usec(500));
|
||||
|
||||
return naomi_ram64[0x5dc900/8];
|
||||
return space->machine().driver_data<dc_state>()->dc_ram[0x5dc900/8];
|
||||
}
|
||||
|
||||
DRIVER_INIT_MEMBER(dc_state,sfz3ugd)
|
||||
@ -340,7 +339,7 @@ static READ64_HANDLER( hotd2_idle_skip_r )
|
||||
// else
|
||||
// printf("%08x\n", space->device().safe_pc());
|
||||
|
||||
return naomi_ram64[0xa25fb8/8];
|
||||
return space->machine().driver_data<dc_state>()->dc_ram[0xa25fb8/8];
|
||||
}
|
||||
|
||||
DRIVER_INIT_MEMBER(dc_state,hotd2)
|
||||
|
||||
@ -280,8 +280,8 @@ static READ32_HANDLER( ddp2_speedup_r )
|
||||
|
||||
static READ16_HANDLER( ddp2_main_speedup_r )
|
||||
{
|
||||
|
||||
UINT16 data = pgm_mainram[0x0ee54/2];
|
||||
pgm_state *state = space->machine().driver_data<pgm_state>();
|
||||
UINT16 data = state->m_mainram[0x0ee54/2];
|
||||
int pc = space->device().safe_pc();
|
||||
|
||||
if (pc == 0x149dce) space->device().execute().spin_until_interrupt();
|
||||
|
||||
@ -277,7 +277,8 @@ static READ32_HANDLER( dmnfrnt_speedup_r )
|
||||
|
||||
static READ16_HANDLER( dmnfrnt_main_speedup_r )
|
||||
{
|
||||
UINT16 data = pgm_mainram[0xa03c/2];
|
||||
pgm_state *state = space->machine().driver_data<pgm_state>();
|
||||
UINT16 data = state->m_mainram[0xa03c/2];
|
||||
int pc = space->device().safe_pc();
|
||||
if (pc == 0x10193a) space->device().execute().spin_until_interrupt();
|
||||
else if (pc == 0x1019a4) space->device().execute().spin_until_interrupt();
|
||||
|
||||
@ -32,7 +32,8 @@ READ16_HANDLER( dw2_d80000_r )
|
||||
// if(dw2reg<0x20) //NOT SURE!!
|
||||
{
|
||||
//The value at 0x80EECE is computed in the routine at 0x107c18
|
||||
UINT16 d = pgm_mainram[0xEECE/2];
|
||||
pgm_state *state = space->machine().driver_data<pgm_state>();
|
||||
UINT16 d = state->m_mainram[0xEECE/2];
|
||||
UINT16 d2 = 0;
|
||||
d = (d >> 8) | (d << 8);
|
||||
DW2BITSWAP(d, d2, 7, 0);
|
||||
|
||||
@ -185,10 +185,11 @@ static WRITE16_HANDLER( olds_w )
|
||||
|
||||
static READ16_HANDLER( olds_prot_swap_r )
|
||||
{
|
||||
pgm_state *state = space->machine().driver_data<pgm_state>();
|
||||
if (space->device().safe_pc() < 0x100000) //bios
|
||||
return pgm_mainram[0x178f4 / 2];
|
||||
return state->m_mainram[0x178f4 / 2];
|
||||
else //game
|
||||
return pgm_mainram[0x178d8 / 2];
|
||||
return state->m_mainram[0x178d8 / 2];
|
||||
|
||||
}
|
||||
|
||||
|
||||
@ -1839,7 +1839,6 @@ TILE_GET_INFO_MEMBER(konamigx_state::get_gx_psac_tile_info)
|
||||
SET_TILE_INFO_MEMBER(0, tileno, colour, TILE_FLIPYX(flip));
|
||||
}
|
||||
|
||||
UINT32* konamigx_type3_psac2_bank;
|
||||
static int konamigx_type3_psac2_actual_bank;
|
||||
//int konamigx_type3_psac2_actual_last_bank = 0;
|
||||
|
||||
@ -1847,8 +1846,8 @@ WRITE32_MEMBER(konamigx_state::konamigx_type3_psac2_bank_w)
|
||||
{
|
||||
// other bits are used for something...
|
||||
|
||||
COMBINE_DATA(&konamigx_type3_psac2_bank[offset]);
|
||||
konamigx_type3_psac2_actual_bank = (konamigx_type3_psac2_bank[0] & 0x10000000) >> 28;
|
||||
COMBINE_DATA(&m_konamigx_type3_psac2_bank[offset]);
|
||||
konamigx_type3_psac2_actual_bank = (m_konamigx_type3_psac2_bank[0] & 0x10000000) >> 28;
|
||||
|
||||
/* handle this by creating 2 roz tilemaps instead, otherwise performance dies completely on dual screen mode
|
||||
if (konamigx_type3_psac2_actual_bank!=konamigx_type3_psac2_actual_last_bank)
|
||||
|
||||
@ -676,6 +676,6 @@ SCREEN_VBLANK( pgm )
|
||||
pgm_state *state = screen.machine().driver_data<pgm_state>();
|
||||
|
||||
/* first 0xa00 of main ram = sprites, seems to be buffered, DMA? */
|
||||
memcpy(state->m_spritebufferram, pgm_mainram, 0xa00);
|
||||
memcpy(state->m_spritebufferram, state->m_mainram, 0xa00);
|
||||
}
|
||||
}
|
||||
|
||||
@ -40,15 +40,13 @@ extern WRITE64_HANDLER( dc_mess_gdrom_w );
|
||||
extern READ64_HANDLER( dc_mess_g1_ctrl_r );
|
||||
extern WRITE64_HANDLER( dc_mess_g1_ctrl_w );
|
||||
|
||||
static UINT64 *dc_ram;
|
||||
|
||||
static READ64_HANDLER( dcus_idle_skip_r )
|
||||
{
|
||||
if (space->device().safe_pc()==0xc0ba52a)
|
||||
space->device().execute().spin_until_time(attotime::from_usec(2500));
|
||||
// device_spinuntil_int(&space->device());
|
||||
|
||||
return dc_ram[0x2303b0/8];
|
||||
return space->machine().driver_data<dc_state>()->dc_ram[0x2303b0/8];
|
||||
}
|
||||
|
||||
static READ64_HANDLER( dcjp_idle_skip_r )
|
||||
@ -57,7 +55,7 @@ static READ64_HANDLER( dcjp_idle_skip_r )
|
||||
space->device().execute().spin_until_time(attotime::from_usec(2500));
|
||||
// device_spinuntil_int(&space->device());
|
||||
|
||||
return dc_ram[0x2302f8/8];
|
||||
return space->machine().driver_data<dc_state>()->dc_ram[0x2302f8/8];
|
||||
}
|
||||
|
||||
DRIVER_INIT_MEMBER(dc_state,dc)
|
||||
@ -179,10 +177,10 @@ static ADDRESS_MAP_START( dc_map, AS_PROGRAM, 64, dc_state )
|
||||
AM_RANGE(0x05000000, 0x05ffffff) AM_RAM AM_SHARE("frameram") // apparently this actually accesses the same memory as the 64-bit texture memory access, but in a different format, keep it apart for now
|
||||
|
||||
/* Area 3 */
|
||||
AM_RANGE(0x0c000000, 0x0cffffff) AM_RAM AM_SHARE("share4") AM_BASE_LEGACY(&dc_ram)
|
||||
AM_RANGE(0x0d000000, 0x0dffffff) AM_RAM AM_SHARE("share4")// extra ram on Naomi (mirror on DC)
|
||||
AM_RANGE(0x0e000000, 0x0effffff) AM_RAM AM_SHARE("share4")// mirror
|
||||
AM_RANGE(0x0f000000, 0x0fffffff) AM_RAM AM_SHARE("share4")// mirror
|
||||
AM_RANGE(0x0c000000, 0x0cffffff) AM_RAM AM_SHARE("dc_ram")
|
||||
AM_RANGE(0x0d000000, 0x0dffffff) AM_RAM AM_SHARE("dc_ram")// extra ram on Naomi (mirror on DC)
|
||||
AM_RANGE(0x0e000000, 0x0effffff) AM_RAM AM_SHARE("dc_ram")// mirror
|
||||
AM_RANGE(0x0f000000, 0x0fffffff) AM_RAM AM_SHARE("dc_ram")// mirror
|
||||
|
||||
/* Area 4 */
|
||||
AM_RANGE(0x10000000, 0x107fffff) AM_WRITE_LEGACY(ta_fifo_poly_w )
|
||||
@ -193,7 +191,7 @@ static ADDRESS_MAP_START( dc_map, AS_PROGRAM, 64, dc_state )
|
||||
AM_RANGE(0x12800000, 0x12ffffff) AM_WRITE_LEGACY(ta_fifo_yuv_w )
|
||||
AM_RANGE(0x13000000, 0x137fffff) AM_WRITE_LEGACY(ta_texture_directpath1_w ) AM_MIRROR(0x00800000) // access to texture / fraembfufer memory (either 32-bit or 64-bit area depending on SB_LMMODE1 register - cannot be written directly, only through dma / store queue
|
||||
|
||||
AM_RANGE(0x8c000000, 0x8cffffff) AM_RAM AM_SHARE("share4") // another RAM mirror
|
||||
AM_RANGE(0x8c000000, 0x8cffffff) AM_RAM AM_SHARE("dc_ram") // another RAM mirror
|
||||
|
||||
AM_RANGE(0xa0000000, 0xa01fffff) AM_ROM AM_REGION("maincpu", 0)
|
||||
ADDRESS_MAP_END
|
||||
|
||||
@ -20,7 +20,7 @@ static READ32_HANDLER( dd_null_r )
|
||||
}
|
||||
|
||||
static ADDRESS_MAP_START( n64_map, AS_PROGRAM, 32, n64_state )
|
||||
AM_RANGE(0x00000000, 0x007fffff) AM_RAM AM_BASE_LEGACY(&rdram) // RDRAM
|
||||
AM_RANGE(0x00000000, 0x007fffff) AM_RAM AM_SHARE("rdram") // RDRAM
|
||||
AM_RANGE(0x03f00000, 0x03f00027) AM_DEVREADWRITE("rcp", n64_periphs, rdram_reg_r, rdram_reg_w)
|
||||
AM_RANGE(0x04000000, 0x04000fff) AM_RAM AM_SHARE("dmem") // RSP DMEM
|
||||
AM_RANGE(0x04001000, 0x04001fff) AM_RAM AM_SHARE("imem") // RSP IMEM
|
||||
@ -33,14 +33,14 @@ static ADDRESS_MAP_START( n64_map, AS_PROGRAM, 32, n64_state )
|
||||
AM_RANGE(0x04700000, 0x047fffff) AM_DEVREADWRITE("rcp", n64_periphs, ri_reg_r, ri_reg_w) // RDRAM Interface
|
||||
AM_RANGE(0x04800000, 0x048fffff) AM_DEVREADWRITE("rcp", n64_periphs, si_reg_r, si_reg_w) // Serial Interface
|
||||
AM_RANGE(0x05000508, 0x0500050b) AM_READ_LEGACY(dd_null_r);
|
||||
AM_RANGE(0x08000000, 0x0801ffff) AM_RAM AM_BASE_LEGACY(&n64_sram) // Cartridge SRAM
|
||||
AM_RANGE(0x08000000, 0x0801ffff) AM_RAM AM_SHARE("sram") // Cartridge SRAM
|
||||
AM_RANGE(0x10000000, 0x13ffffff) AM_ROM AM_REGION("user2", 0) // Cartridge
|
||||
AM_RANGE(0x1fc00000, 0x1fc007bf) AM_ROM AM_REGION("user1", 0) // PIF ROM
|
||||
AM_RANGE(0x1fc007c0, 0x1fc007ff) AM_DEVREADWRITE("rcp", n64_periphs, pif_ram_r, pif_ram_w)
|
||||
ADDRESS_MAP_END
|
||||
|
||||
static ADDRESS_MAP_START( n64dd_map, AS_PROGRAM, 32, n64_state )
|
||||
AM_RANGE(0x00000000, 0x007fffff) AM_RAM AM_BASE_LEGACY(&rdram) // RDRAM
|
||||
AM_RANGE(0x00000000, 0x007fffff) AM_RAM AM_SHARE("rdram") // RDRAM
|
||||
AM_RANGE(0x03f00000, 0x03f00027) AM_DEVREADWRITE("rcp", n64_periphs, rdram_reg_r, rdram_reg_w)
|
||||
AM_RANGE(0x04000000, 0x04000fff) AM_RAM AM_SHARE("dmem") // RSP DMEM
|
||||
AM_RANGE(0x04001000, 0x04001fff) AM_RAM AM_SHARE("imem") // RSP IMEM
|
||||
@ -54,7 +54,7 @@ static ADDRESS_MAP_START( n64dd_map, AS_PROGRAM, 32, n64_state )
|
||||
AM_RANGE(0x04800000, 0x048fffff) AM_DEVREADWRITE("rcp", n64_periphs, si_reg_r, si_reg_w) // Serial Interface
|
||||
AM_RANGE(0x05000000, 0x05ffffff) AM_DEVREADWRITE("rcp", n64_periphs, dd_reg_r, dd_reg_w) // 64DD Interface
|
||||
AM_RANGE(0x06000000, 0x063fffff) AM_ROM AM_REGION("ddipl", 0) // 64DD IPL ROM
|
||||
AM_RANGE(0x08000000, 0x0801ffff) AM_RAM AM_BASE_LEGACY(&n64_sram) // Cartridge SRAM
|
||||
AM_RANGE(0x08000000, 0x0801ffff) AM_RAM AM_SHARE("sram") // Cartridge SRAM
|
||||
AM_RANGE(0x10000000, 0x13ffffff) AM_ROM AM_REGION("user2", 0) // Cartridge
|
||||
AM_RANGE(0x1fc00000, 0x1fc007bf) AM_ROM AM_REGION("user1", 0) // PIF ROM
|
||||
AM_RANGE(0x1fc007c0, 0x1fc007ff) AM_DEVREADWRITE("rcp", n64_periphs, pif_ram_r, pif_ram_w)
|
||||
@ -63,8 +63,8 @@ ADDRESS_MAP_END
|
||||
static ADDRESS_MAP_START( rsp_map, AS_PROGRAM, 32, n64_state )
|
||||
AM_RANGE(0x00000000, 0x00000fff) AM_RAM AM_SHARE("dmem")
|
||||
AM_RANGE(0x00001000, 0x00001fff) AM_RAM AM_SHARE("imem")
|
||||
AM_RANGE(0x04000000, 0x04000fff) AM_RAM AM_BASE_LEGACY(&rsp_dmem) AM_SHARE("dmem")
|
||||
AM_RANGE(0x04001000, 0x04001fff) AM_RAM AM_BASE_LEGACY(&rsp_imem) AM_SHARE("imem")
|
||||
AM_RANGE(0x04000000, 0x04000fff) AM_RAM AM_SHARE("rsp_dmem") AM_SHARE("dmem")
|
||||
AM_RANGE(0x04001000, 0x04001fff) AM_RAM AM_SHARE("rsp_imem") AM_SHARE("imem")
|
||||
ADDRESS_MAP_END
|
||||
|
||||
static INPUT_PORTS_START( n64 )
|
||||
|
||||
@ -110,7 +110,7 @@ public:
|
||||
|
||||
//static UINT16 *save_ram;
|
||||
|
||||
UINT16* neocd_work_ram;
|
||||
//UINT16* neocd_work_ram;
|
||||
|
||||
/*************************************
|
||||
*
|
||||
@ -1310,7 +1310,7 @@ ADDRESS_MAP_END
|
||||
static ADDRESS_MAP_START( neocd_main_map, AS_PROGRAM, 16, ng_aes_state )
|
||||
AM_RANGE(0x000000, 0x00007f) AM_RAMBANK(NEOGEO_BANK_VECTORS)
|
||||
AM_RANGE(0x000080, 0x0fffff) AM_RAM
|
||||
AM_RANGE(0x100000, 0x10ffff) AM_MIRROR(0x0f0000) AM_RAM AM_BASE_LEGACY(&neocd_work_ram)
|
||||
AM_RANGE(0x100000, 0x10ffff) AM_MIRROR(0x0f0000) AM_RAM AM_SHARE("neocd_work_ram")
|
||||
/* some games have protection devices in the 0x200000 region, it appears to map to cart space, not surprising, the ROM is read here too */
|
||||
AM_RANGE(0x200000, 0x2fffff) AM_ROMBANK(NEOGEO_BANK_CARTRIDGE)
|
||||
AM_RANGE(0x2ffff0, 0x2fffff) AM_WRITE(main_cpu_bank_select_w)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user