mirror of
https://github.com/holub/mame
synced 2025-05-25 23:35:26 +03:00
Converted Namco 54xx to a device. The interface now specifies the name
of the target discrete sound object and the base node, rather than making assumptions.
This commit is contained in:
Aaron Giles
parent
44eb499a4a
commit
ca0bee02b5
@ -224,7 +224,7 @@ ADDRESS_MAP_END
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static MACHINE_DRIVER_START( namco_52xx )
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MDRV_CPU_ADD("mcu", MB8842, DERIVED_CLOCK(1,6)) /* parent clock, internally divided by 6 */
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MDRV_CPU_ADD("mcu", MB8842/*MB8852*/, DERIVED_CLOCK(1,6)) /* parent clock, internally divided by 6 */
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MDRV_CPU_PROGRAM_MAP(namco_52xx_map_program)
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MDRV_CPU_DATA_MAP(namco_52xx_map_data)
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MDRV_CPU_IO_MAP(namco_52xx_map_io)
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@ -129,17 +129,17 @@ DISCRETE_SOUND_START(bosco)
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/************************************************
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* Input register mapping
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************************************************/
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DISCRETE_INPUT_DATA(NAMCO_54XX_0_DATA)
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DISCRETE_INPUT_DATA(NAMCO_54XX_1_DATA)
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DISCRETE_INPUT_DATA(NAMCO_54XX_2_DATA)
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DISCRETE_INPUT_DATA(NAMCO_52XX_P_DATA)
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DISCRETE_INPUT_DATA(NAMCO_54XX_0_DATA(NODE_01))
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DISCRETE_INPUT_DATA(NAMCO_54XX_1_DATA(NODE_01))
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DISCRETE_INPUT_DATA(NAMCO_54XX_2_DATA(NODE_01))
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DISCRETE_INPUT_DATA(NAMCO_52XX_P_DATA(NODE_01))
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/************************************************
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* CHANL1 sound
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************************************************/
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DISCRETE_DAC_R1(NODE_20,
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1, /* ENAB */
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NAMCO_54XX_2_DATA,
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NAMCO_54XX_2_DATA(NODE_01),
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4, /* 4V - unmeasured*/
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&bosco_54xx_dac)
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DISCRETE_OP_AMP_FILTER(BOSCO_CHANL1_SND,
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@ -153,7 +153,7 @@ DISCRETE_SOUND_START(bosco)
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************************************************/
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DISCRETE_DAC_R1(NODE_30,
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1, /* ENAB */
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NAMCO_54XX_1_DATA,
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NAMCO_54XX_1_DATA(NODE_01),
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4, /* 4V - unmeasured*/
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&bosco_54xx_dac)
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DISCRETE_OP_AMP_FILTER(BOSCO_CHANL2_SND,
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@ -167,7 +167,7 @@ DISCRETE_SOUND_START(bosco)
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************************************************/
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DISCRETE_DAC_R1(NODE_40,
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1, /* ENAB */
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NAMCO_54XX_0_DATA,
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NAMCO_54XX_0_DATA(NODE_01),
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4, /* 4V - unmeasured*/
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&bosco_54xx_dac)
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DISCRETE_OP_AMP_FILTER(BOSCO_CHANL3_SND,
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@ -183,7 +183,7 @@ DISCRETE_SOUND_START(bosco)
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/* this circuit was simulated in SPICE and an equivalent filter circuit generated */
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DISCRETE_DAC_R1(NODE_50,
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0, /* ENAB */
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NAMCO_52XX_P_DATA,
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NAMCO_52XX_P_DATA(NODE_01),
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4, /* 4V - unmeasured*/
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&bosco_52xx_dac)
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DISCRETE_FILTER2(NODE_51,
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@ -314,16 +314,16 @@ DISCRETE_SOUND_START(galaga)
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/************************************************
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* Input register mapping
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************************************************/
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DISCRETE_INPUT_DATA(NAMCO_54XX_0_DATA)
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DISCRETE_INPUT_DATA(NAMCO_54XX_1_DATA)
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DISCRETE_INPUT_DATA(NAMCO_54XX_2_DATA)
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DISCRETE_INPUT_DATA(NAMCO_54XX_0_DATA(NODE_01))
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DISCRETE_INPUT_DATA(NAMCO_54XX_1_DATA(NODE_01))
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DISCRETE_INPUT_DATA(NAMCO_54XX_2_DATA(NODE_01))
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/************************************************
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* CHANL1 sound
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************************************************/
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DISCRETE_DAC_R1(NODE_20,
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1, /* ENAB */
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NAMCO_54XX_2_DATA,
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NAMCO_54XX_2_DATA(NODE_01),
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4, /* 4V - unmeasured*/
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&galaga_54xx_dac)
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DISCRETE_OP_AMP_FILTER(GALAGA_CHANL1_SND,
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@ -337,7 +337,7 @@ DISCRETE_SOUND_START(galaga)
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************************************************/
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DISCRETE_DAC_R1(NODE_30,
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1, /* ENAB */
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NAMCO_54XX_1_DATA,
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NAMCO_54XX_1_DATA(NODE_01),
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4, /* 4V - unmeasured*/
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&galaga_54xx_dac)
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DISCRETE_OP_AMP_FILTER(GALAGA_CHANL2_SND,
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@ -351,7 +351,7 @@ DISCRETE_SOUND_START(galaga)
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************************************************/
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DISCRETE_DAC_R1(NODE_40,
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1, /* ENAB */
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NAMCO_54XX_0_DATA,
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NAMCO_54XX_0_DATA(NODE_01),
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4, /* 4V - unmeasured*/
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&galaga_54xx_dac)
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DISCRETE_OP_AMP_FILTER(GALAGA_CHANL3_SND,
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@ -52,43 +52,93 @@ The command format is very simple:
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#include "namco54.h"
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#include "cpu/mb88xx/mb88xx.h"
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typedef struct _namco_54xx_state namco_54xx_state;
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struct _namco_54xx_state
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{
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const device_config *cpu;
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const device_config *discrete;
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int basenode;
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UINT8 latched_cmd;
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};
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INLINE namco_54xx_state *get_safe_token(const device_config *device)
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{
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assert(device != NULL);
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assert(device->token != NULL);
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assert(device->type == NAMCO_54XX);
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return (namco_54xx_state *)device->token;
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}
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static UINT8 latched_cmd;
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static TIMER_CALLBACK( namco_54xx_latch_callback )
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{
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latched_cmd = param;
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namco_54xx_state *state = get_safe_token((const device_config *)ptr);
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state->latched_cmd = param;
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}
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static READ8_HANDLER( namco_54xx_K_r )
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{
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return latched_cmd >> 4;
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namco_54xx_state *state = get_safe_token(space->cpu->owner);
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return state->latched_cmd >> 4;
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}
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static READ8_HANDLER( namco_54xx_R0_r )
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{
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return latched_cmd & 0x0f;
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namco_54xx_state *state = get_safe_token(space->cpu->owner);
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return state->latched_cmd & 0x0f;
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}
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static WRITE8_DEVICE_HANDLER( namco_54xx_O_w )
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static WRITE8_HANDLER( namco_54xx_O_w )
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{
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namco_54xx_state *state = get_safe_token(space->cpu->owner);
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UINT8 out = (data & 0x0f);
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if (data & 0x10)
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discrete_sound_w(device, NAMCO_54XX_1_DATA, out);
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discrete_sound_w(state->discrete, NAMCO_54XX_1_DATA(state->basenode), out);
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else
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discrete_sound_w(device, NAMCO_54XX_0_DATA, out);
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discrete_sound_w(state->discrete, NAMCO_54XX_0_DATA(state->basenode), out);
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}
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static WRITE8_DEVICE_HANDLER( namco_54xx_R1_w )
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static WRITE8_HANDLER( namco_54xx_R1_w )
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{
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namco_54xx_state *state = get_safe_token(space->cpu->owner);
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UINT8 out = (data & 0x0f);
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discrete_sound_w(device, NAMCO_54XX_2_DATA, out);
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discrete_sound_w(state->discrete, NAMCO_54XX_2_DATA(state->basenode), out);
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}
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static TIMER_CALLBACK( namco_54xx_irq_clear )
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{
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namco_54xx_state *state = get_safe_token((const device_config *)ptr);
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cpu_set_input_line(state->cpu, 0, CLEAR_LINE);
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}
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void namco_54xx_write(const device_config *device, UINT8 data)
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{
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namco_54xx_state *state = get_safe_token(device);
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timer_call_after_resynch(device->machine, (void *)device, data, namco_54xx_latch_callback);
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cpu_set_input_line(state->cpu, 0, ASSERT_LINE);
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// The execution time of one instruction is ~4us, so we must make sure to
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// give the cpu time to poll the /IRQ input before we clear it.
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// The input clock to the 06XX interface chip is 64H, that is
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// 18432000/6/64 = 48kHz, so it makes sense for the irq line to be
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// asserted for one clock cycle ~= 21us.
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timer_set(device->machine, ATTOTIME_IN_USEC(21), (void *)device, 0, namco_54xx_irq_clear);
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}
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/***************************************************************************
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DEVICE INTERFACE
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***************************************************************************/
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ADDRESS_MAP_START( namco_54xx_map_program, ADDRESS_SPACE_PROGRAM, 8 )
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AM_RANGE(0x000, 0x3ff) AM_ROM
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ADDRESS_MAP_END
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@ -99,35 +149,86 @@ ADDRESS_MAP_END
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ADDRESS_MAP_START( namco_54xx_map_io, ADDRESS_SPACE_IO, 8 )
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AM_RANGE(MB88_PORTK, MB88_PORTK) AM_READ(namco_54xx_K_r)
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AM_RANGE(MB88_PORTO, MB88_PORTO) AM_DEVWRITE("discrete", namco_54xx_O_w)
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AM_RANGE(MB88_PORTO, MB88_PORTO) AM_WRITE(namco_54xx_O_w)
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AM_RANGE(MB88_PORTR0, MB88_PORTR0) AM_READ(namco_54xx_R0_r)
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AM_RANGE(MB88_PORTR1, MB88_PORTR1) AM_DEVWRITE("discrete", namco_54xx_R1_w)
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AM_RANGE(MB88_PORTR1, MB88_PORTR1) AM_WRITE(namco_54xx_R1_w)
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AM_RANGE(MB88_PORTR2, MB88_PORTR2) AM_NOP
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ADDRESS_MAP_END
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static MACHINE_DRIVER_START( namco_54xx )
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MDRV_CPU_ADD("mcu", MB8844, DERIVED_CLOCK(1,6)) /* parent clock, internally divided by 6 */
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MDRV_CPU_PROGRAM_MAP(namco_54xx_map_program)
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MDRV_CPU_DATA_MAP(namco_54xx_map_data)
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MDRV_CPU_IO_MAP(namco_54xx_map_io)
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MACHINE_DRIVER_END
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static TIMER_CALLBACK( namco_54xx_irq_clear )
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ROM_START( namco_54xx )
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ROM_REGION( 0x400, "mcu", 0 )
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ROM_LOAD( "54xx.bin", 0x0000, 0x0400, CRC(ee7357e0) SHA1(01bdf984a49e8d0cc8761b2cc162fd6434d5afbe) )
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ROM_END
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/*-------------------------------------------------
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device start callback
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-------------------------------------------------*/
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static DEVICE_START( namco_54xx )
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{
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const device_config *device = (const device_config *)ptr;
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cpu_set_input_line(device, 0, CLEAR_LINE);
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namco_54xx_config *config = (namco_54xx_config *)device->inline_config;
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namco_54xx_state *state = get_safe_token(device);
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astring *tempstring = astring_alloc();
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/* find our CPU */
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state->cpu = cputag_get_cpu(device->machine, device_build_tag(tempstring, device, "mcu"));
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assert(state->cpu != NULL);
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astring_free(tempstring);
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/* find the attached discrete sound device */
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assert(config->discrete != NULL);
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state->discrete = devtag_get_device(device->machine, config->discrete);
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assert(state->discrete != NULL);
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state->basenode = config->firstnode;
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}
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void namco_54xx_write(running_machine *machine, UINT8 data)
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/*-------------------------------------------------
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device reset callback
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-------------------------------------------------*/
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static DEVICE_RESET( namco_54xx )
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{
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const device_config *device = cputag_get_cpu(machine, CPUTAG_54XX);
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if (device == NULL)
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return;
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timer_call_after_resynch(machine, NULL, data, namco_54xx_latch_callback);
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cpu_set_input_line(device, 0, ASSERT_LINE);
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// The execution time of one instruction is ~4us, so we must make sure to
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// give the cpu time to poll the /IRQ input before we clear it.
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// The input clock to the 06XX interface chip is 64H, that is
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// 18432000/6/64 = 48kHz, so it makes sense for the irq line to be
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// asserted for one clock cycle ~= 21us.
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timer_set(machine, ATTOTIME_IN_USEC(21), (void *)device, 0, namco_54xx_irq_clear);
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// namco_54xx_state *state = get_safe_token(device);
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}
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/*-------------------------------------------------
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device get info callback
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-------------------------------------------------*/
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DEVICE_GET_INFO( namco_54xx )
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{
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switch (state)
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{
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/* --- the following bits of info are returned as 64-bit signed integers --- */
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case DEVINFO_INT_TOKEN_BYTES: info->i = sizeof(namco_54xx_state); break;
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case DEVINFO_INT_INLINE_CONFIG_BYTES: info->i = sizeof(namco_54xx_config); break;
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case DEVINFO_INT_CLASS: info->i = DEVICE_CLASS_PERIPHERAL; break;
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/* --- the following bits of info are returned as pointers --- */
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case DEVINFO_PTR_ROM_REGION: info->romregion = ROM_NAME(namco_54xx); break;
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case DEVINFO_PTR_MACHINE_CONFIG: info->machine_config = MACHINE_DRIVER_NAME(namco_54xx); break;
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/* --- the following bits of info are returned as pointers to data or functions --- */
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case DEVINFO_FCT_START: info->start = DEVICE_START_NAME(namco_54xx); break;
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case DEVINFO_FCT_RESET: info->reset = DEVICE_RESET_NAME(namco_54xx); break;
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/* --- the following bits of info are returned as NULL-terminated strings --- */
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case DEVINFO_STR_NAME: strcpy(info->s, "Namco 54xx"); break;
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case DEVINFO_STR_FAMILY: strcpy(info->s, "Namco I/O"); break;
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case DEVINFO_STR_VERSION: strcpy(info->s, "1.0"); break;
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case DEVINFO_STR_SOURCE_FILE: strcpy(info->s, __FILE__); break;
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case DEVINFO_STR_CREDITS: strcpy(info->s, "Copyright Nicola Salmoria and the MAME Team"); break;
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}
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}
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@ -3,18 +3,36 @@
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#include "sound/discrete.h"
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#define CPUTAG_54XX "54xx"
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ADDRESS_MAP_EXTERN( namco_54xx_map_program, 8 );
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ADDRESS_MAP_EXTERN( namco_54xx_map_data, 8 );
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ADDRESS_MAP_EXTERN( namco_54xx_map_io, 8 );
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typedef struct _namco_54xx_config namco_54xx_config;
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struct _namco_54xx_config
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{
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const char *discrete; /* name of the discrete sound device */
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int firstnode; /* index of the first node */
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};
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void namco_54xx_write(running_machine *machine, UINT8 data);
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#define MDRV_NAMCO_54XX_ADD(_tag, _clock, _discrete, _firstnode) \
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MDRV_DEVICE_ADD(_tag, NAMCO_54XX, _clock) \
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MDRV_DEVICE_CONFIG_DATAPTR(namco_54xx_config, discrete, _discrete) \
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MDRV_DEVICE_CONFIG_DATA32(namco_54xx_config, firstnode, _firstnode)
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#define MDRV_NAMCO_54XX_REMOVE(_tag) \
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MDRV_DEVICE_REMOVE(_tag)
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void namco_54xx_write(const device_config *device, UINT8 data);
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/* device get info callback */
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#define NAMCO_54XX DEVICE_GET_INFO_NAME(namco_54xx)
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DEVICE_GET_INFO( namco_54xx );
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/* discrete nodes */
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#define NAMCO_54XX_0_DATA NODE_01
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#define NAMCO_54XX_1_DATA NODE_02
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#define NAMCO_54XX_2_DATA NODE_03
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#define NAMCO_52XX_P_DATA NODE_04
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#define NAMCO_54XX_0_DATA(base) (NODE_RELATIVE(base, 0))
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#define NAMCO_54XX_1_DATA(base) (NODE_RELATIVE(base, 1))
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#define NAMCO_54XX_2_DATA(base) (NODE_RELATIVE(base, 2))
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#define NAMCO_52XX_P_DATA(base) (NODE_RELATIVE(base, 3))
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#endif /* NAMCO54_H */
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@ -250,17 +250,17 @@ DISCRETE_SOUND_START(polepos)
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/************************************************
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* Input register mapping
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************************************************/
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DISCRETE_INPUT_DATA(NAMCO_54XX_0_DATA)
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DISCRETE_INPUT_DATA(NAMCO_54XX_1_DATA)
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DISCRETE_INPUT_DATA(NAMCO_54XX_2_DATA)
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DISCRETE_INPUT_DATA(NAMCO_52XX_P_DATA)
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DISCRETE_INPUT_DATA(NAMCO_54XX_0_DATA(NODE_01))
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DISCRETE_INPUT_DATA(NAMCO_54XX_1_DATA(NODE_01))
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DISCRETE_INPUT_DATA(NAMCO_54XX_2_DATA(NODE_01))
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DISCRETE_INPUT_DATA(NAMCO_52XX_P_DATA(NODE_01))
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/************************************************
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* CHANL1 sound
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************************************************/
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DISCRETE_DAC_R1(NODE_20,
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1, /* ENAB */
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NAMCO_54XX_2_DATA,
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NAMCO_54XX_2_DATA(NODE_01),
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4, /* 4V - unmeasured*/
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&polepos_54xx_dac)
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DISCRETE_OP_AMP_FILTER(NODE_21,
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@ -278,7 +278,7 @@ DISCRETE_SOUND_START(polepos)
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************************************************/
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DISCRETE_DAC_R1(NODE_30,
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1, /* ENAB */
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NAMCO_54XX_1_DATA,
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NAMCO_54XX_1_DATA(NODE_01),
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4, /* 4V - unmeasured*/
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&polepos_54xx_dac)
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DISCRETE_OP_AMP_FILTER(NODE_31,
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@ -296,7 +296,7 @@ DISCRETE_SOUND_START(polepos)
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************************************************/
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DISCRETE_DAC_R1(NODE_40,
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1, /* ENAB */
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NAMCO_54XX_0_DATA,
|
||||
NAMCO_54XX_0_DATA(NODE_01),
|
||||
4, /* 4V - unmeasured*/
|
||||
&polepos_54xx_dac)
|
||||
DISCRETE_OP_AMP_FILTER(NODE_41,
|
||||
@ -316,7 +316,7 @@ DISCRETE_SOUND_START(polepos)
|
||||
/* this circuit was simulated in SPICE and an equivalent filter circuit generated */
|
||||
DISCRETE_DAC_R1(NODE_50,
|
||||
0, /* ENAB */
|
||||
NAMCO_52XX_P_DATA,
|
||||
NAMCO_52XX_P_DATA(NODE_01),
|
||||
4, /* 4V - unmeasured*/
|
||||
&polepos_52xx_dac)
|
||||
/* fake it so 0 is now vRef */
|
||||
|
||||
@ -846,7 +846,7 @@ static MACHINE_RESET( bosco )
|
||||
NAMCOIO_51XX, &intf0, NULL,
|
||||
NAMCOIO_NONE, NULL, NULL,
|
||||
NAMCOIO_50XX, NULL, "50xx_1",
|
||||
NAMCOIO_54XX, NULL, NULL);
|
||||
NAMCOIO_54XX, NULL, "54xx");
|
||||
|
||||
namco_06xx_init(machine, 1, 1,
|
||||
NAMCOIO_50XX, NULL, "50xx_2",
|
||||
@ -866,7 +866,7 @@ static MACHINE_RESET( galaga )
|
||||
NAMCOIO_51XX, &intf0, NULL,
|
||||
NAMCOIO_NONE, NULL, NULL,
|
||||
NAMCOIO_NONE, NULL, NULL,
|
||||
NAMCOIO_54XX, NULL, NULL);
|
||||
NAMCOIO_54XX, NULL, "54xx");
|
||||
|
||||
timer_adjust_oneshot(cpu3_interrupt_timer, video_screen_get_time_until_pos(machine->primary_screen, 64, 0), 64);
|
||||
}
|
||||
@ -880,7 +880,7 @@ static MACHINE_RESET( xevious )
|
||||
NAMCOIO_51XX, &intf0, NULL,
|
||||
NAMCOIO_NONE, NULL, NULL,
|
||||
NAMCOIO_50XX, NULL, "50xx",
|
||||
NAMCOIO_54XX, NULL, NULL);
|
||||
NAMCOIO_54XX, NULL, "54xx");
|
||||
|
||||
timer_adjust_oneshot(cpu3_interrupt_timer, video_screen_get_time_until_pos(machine->primary_screen, 64, 0), 64);
|
||||
}
|
||||
@ -1635,11 +1635,7 @@ static MACHINE_DRIVER_START( bosco )
|
||||
|
||||
MDRV_NAMCO_50XX_ADD("50xx_1", MASTER_CLOCK/12) /* 1.536 MHz */
|
||||
MDRV_NAMCO_50XX_ADD("50xx_2", MASTER_CLOCK/12) /* 1.536 MHz */
|
||||
|
||||
MDRV_CPU_ADD(CPUTAG_54XX, MB8844, MASTER_CLOCK/12/6) /* 1.536 MHz, internally divided by 6 */
|
||||
MDRV_CPU_PROGRAM_MAP(namco_54xx_map_program)
|
||||
MDRV_CPU_DATA_MAP(namco_54xx_map_data)
|
||||
MDRV_CPU_IO_MAP(namco_54xx_map_io)
|
||||
MDRV_NAMCO_54XX_ADD("54xx", MASTER_CLOCK/12, "discrete", NODE_01) /* 1.536 MHz */
|
||||
|
||||
MDRV_WATCHDOG_VBLANK_INIT(8)
|
||||
MDRV_QUANTUM_TIME(HZ(6000)) /* 100 CPU slices per frame - an high value to ensure proper */
|
||||
@ -1695,10 +1691,7 @@ static MACHINE_DRIVER_START( galaga )
|
||||
MDRV_CPU_ADD("sub2", Z80, MASTER_CLOCK/6) /* 3.072 MHz */
|
||||
MDRV_CPU_PROGRAM_MAP(galaga_map)
|
||||
|
||||
MDRV_CPU_ADD(CPUTAG_54XX, MB8844, MASTER_CLOCK/12/6) /* 1.536 MHz, internally divided by 6 */
|
||||
MDRV_CPU_PROGRAM_MAP(namco_54xx_map_program)
|
||||
MDRV_CPU_DATA_MAP(namco_54xx_map_data)
|
||||
MDRV_CPU_IO_MAP(namco_54xx_map_io)
|
||||
MDRV_NAMCO_54XX_ADD("54xx", MASTER_CLOCK/12, "discrete", NODE_01) /* 1.536 MHz */
|
||||
|
||||
MDRV_WATCHDOG_VBLANK_INIT(8)
|
||||
MDRV_QUANTUM_TIME(HZ(6000)) /* 100 CPU slices per frame - an high value to ensure proper */
|
||||
@ -1740,7 +1733,7 @@ static MACHINE_DRIVER_START( galagab )
|
||||
/* basic machine hardware */
|
||||
MDRV_IMPORT_FROM(galaga)
|
||||
|
||||
MDRV_CPU_REMOVE(CPUTAG_54XX)
|
||||
MDRV_NAMCO_54XX_REMOVE("54xx")
|
||||
|
||||
MDRV_CPU_ADD("sub3", Z80, MASTER_CLOCK/6) /* 3.072 MHz */
|
||||
MDRV_CPU_PROGRAM_MAP(galaga_mem4)
|
||||
@ -1765,11 +1758,7 @@ static MACHINE_DRIVER_START( xevious )
|
||||
MDRV_CPU_PROGRAM_MAP(xevious_map)
|
||||
|
||||
MDRV_NAMCO_50XX_ADD("50xx", MASTER_CLOCK/12) /* 1.536 MHz */
|
||||
|
||||
MDRV_CPU_ADD(CPUTAG_54XX, MB8844, MASTER_CLOCK/12/6) /* 1.536 MHz, internally divided by 6 */
|
||||
MDRV_CPU_PROGRAM_MAP(namco_54xx_map_program)
|
||||
MDRV_CPU_DATA_MAP(namco_54xx_map_data)
|
||||
MDRV_CPU_IO_MAP(namco_54xx_map_io)
|
||||
MDRV_NAMCO_54XX_ADD("54xx", MASTER_CLOCK/12, "discrete", NODE_01) /* 1.536 MHz */
|
||||
|
||||
MDRV_WATCHDOG_VBLANK_INIT(8)
|
||||
MDRV_QUANTUM_TIME(HZ(60000)) /* 1000 CPU slices per frame - an high value to ensure proper */
|
||||
@ -1811,7 +1800,7 @@ static MACHINE_DRIVER_START( battles )
|
||||
MDRV_IMPORT_FROM( xevious )
|
||||
|
||||
MDRV_NAMCO_50XX_REMOVE("50xx")
|
||||
MDRV_CPU_REMOVE(CPUTAG_54XX)
|
||||
MDRV_NAMCO_54XX_REMOVE("54xx")
|
||||
|
||||
MDRV_CPU_ADD("sub3", Z80, MASTER_CLOCK/6) /* 3.072 MHz */
|
||||
MDRV_CPU_PROGRAM_MAP(battles_mem4)
|
||||
@ -1903,7 +1892,6 @@ Namco/Midway, 1981
|
||||
*/
|
||||
|
||||
#define BOSCO_CUSTOMS \
|
||||
ROM_REGION_NAMCO_54XX( CPUTAG_54XX ) \
|
||||
ROM_REGION_NAMCO_51XX( "51xx" ) \
|
||||
|
||||
|
||||
@ -2293,7 +2281,6 @@ Notes:
|
||||
*/
|
||||
|
||||
#define GALAGA_CUSTOMS \
|
||||
ROM_REGION_NAMCO_54XX( CPUTAG_54XX ) \
|
||||
ROM_REGION_NAMCO_51XX( "51xx" ) \
|
||||
|
||||
|
||||
@ -2528,7 +2515,6 @@ ROM_END
|
||||
**********************************************************************************************/
|
||||
|
||||
#define XEVIOUS_CUSTOMS \
|
||||
ROM_REGION_NAMCO_54XX( CPUTAG_54XX ) \
|
||||
ROM_REGION_NAMCO_51XX( "51xx" ) \
|
||||
|
||||
/*
|
||||
|
||||
@ -386,7 +386,7 @@ static MACHINE_RESET( polepos )
|
||||
NAMCOIO_51XX, &intf0, NULL,
|
||||
NAMCOIO_53XX_POLEPOS, &intf1, NULL,
|
||||
NAMCOIO_52XX, NULL, "namco52",
|
||||
NAMCOIO_54XX, NULL, NULL);
|
||||
NAMCOIO_54XX, NULL, "54xx");
|
||||
|
||||
/* set the interrupt vectors (this shouldn't be needed) */
|
||||
cpu_set_input_line_vector(cputag_get_cpu(machine, "sub"), 0, Z8000_NVI);
|
||||
@ -846,10 +846,7 @@ static MACHINE_DRIVER_START( polepos )
|
||||
MDRV_CPU_PROGRAM_MAP(z8002_map)
|
||||
MDRV_CPU_VBLANK_INT("screen", irq0_line_assert)
|
||||
|
||||
MDRV_CPU_ADD(CPUTAG_54XX, MB8844, 18432000/12/6) /* 1.536 MHz, internally divided by 6 */
|
||||
MDRV_CPU_PROGRAM_MAP(namco_54xx_map_program)
|
||||
MDRV_CPU_DATA_MAP(namco_54xx_map_data)
|
||||
MDRV_CPU_IO_MAP(namco_54xx_map_io)
|
||||
MDRV_NAMCO_54XX_ADD("54xx", 18432000/12, "discrete", NODE_01) /* 1.536 MHz */
|
||||
|
||||
MDRV_WATCHDOG_VBLANK_INIT(16) // 128V clocks the same as VBLANK
|
||||
|
||||
@ -905,7 +902,6 @@ MACHINE_DRIVER_END
|
||||
*********************************************************************/
|
||||
|
||||
#define POLEPOS_CUSTOMS \
|
||||
ROM_REGION_NAMCO_54XX( CPUTAG_54XX ) \
|
||||
ROM_REGION_NAMCO_51XX( "51xx" ) \
|
||||
ROM_REGION_NAMCO_53XX( "53xx" ) \
|
||||
|
||||
|
||||
@ -16,7 +16,4 @@
|
||||
ROM_LOAD( "53xx.bin", 0x0000, 0x0400, CRC(b326fecb) SHA1(758d8583d658e4f1df93184009d86c3eb8713899) ) \
|
||||
|
||||
/* the 54XX is an explosion sound generator */
|
||||
#define ROM_REGION_NAMCO_54XX( region ) \
|
||||
ROM_REGION( 0x400, region, 0 ) /* 1k for the 54xx */ \
|
||||
ROM_LOAD( "54xx.bin", 0x0000, 0x0400, CRC(ee7357e0) SHA1(01bdf984a49e8d0cc8761b2cc162fd6434d5afbe) ) \
|
||||
|
||||
|
||||
@ -932,7 +932,7 @@ static void namco_06xx_data_write(running_machine *machine,int chipnum,UINT8 dat
|
||||
case NAMCOIO_50XX: namco_50xx_write(io[chipnum].device, data); break;
|
||||
case NAMCOIO_51XX: namcoio_51XX_write(machine,chipnum,data); break;
|
||||
case NAMCOIO_52XX: namco_52xx_write(io[chipnum].device, data); break;
|
||||
case NAMCOIO_54XX: namco_54xx_write(machine, data); break;
|
||||
case NAMCOIO_54XX: namco_54xx_write(io[chipnum].device, data); break;
|
||||
default:
|
||||
logerror("%s: custom IO type %d unsupported write\n",cpuexec_describe_context(machine),io[chipnum].type);
|
||||
break;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user