From cac7437f8ed1f75927ddbfa944a8eddd832fefbb Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 21 Mar 2014 13:23:00 +0000 Subject: [PATCH] namco to modern device + devcb2 (nw) --- src/mame/audio/namco52.c | 181 ++++++++-------------- src/mame/audio/namco52.h | 62 +++++--- src/mame/audio/namco54.c | 111 ++++---------- src/mame/audio/namco54.h | 33 +++- src/mame/drivers/galaga.c | 217 +++++++++++++------------- src/mame/drivers/gaplus.c | 25 +-- src/mame/drivers/polepos.c | 119 ++++++--------- src/mame/machine/namco06.c | 237 +++++++++-------------------- src/mame/machine/namco06.h | 100 ++++++++++-- src/mame/machine/namco50.c | 138 +++++------------ src/mame/machine/namco50.h | 30 ++-- src/mame/machine/namco51.c | 302 ++++++++++++++----------------------- src/mame/machine/namco51.h | 58 +++++-- src/mame/machine/namco53.c | 134 ++++++---------- src/mame/machine/namco53.h | 58 +++++-- src/mame/machine/namco62.c | 52 ++----- src/mame/machine/namco62.h | 48 ++++-- 17 files changed, 832 insertions(+), 1073 deletions(-) diff --git a/src/mame/audio/namco52.c b/src/mame/audio/namco52.c index bcd3a127eee..56876df85b6 100644 --- a/src/mame/audio/namco52.c +++ b/src/mame/audio/namco52.c @@ -49,104 +49,66 @@ #include "emu.h" #include "namco52.h" -#include "cpu/mb88xx/mb88xx.h" -#include "devlegcy.h" -struct namco_52xx_state +TIMER_CALLBACK_MEMBER( namco_52xx_device::latch_callback ) { - mb88_cpu_device *m_cpu; - device_t *m_discrete; - int m_basenode; - devcb_resolved_read8 m_romread; - devcb_resolved_read8 m_si; - UINT8 m_latched_cmd; - UINT32 m_address; -}; + m_latched_cmd = param; +} -INLINE namco_52xx_state *get_safe_token(device_t *device) +READ8_MEMBER( namco_52xx_device::K_r ) { - assert(device != NULL); - assert(device->type() == NAMCO_52XX); + return m_latched_cmd & 0x0f; +} - return (namco_52xx_state *)downcast(device)->token(); +READ8_MEMBER( namco_52xx_device::SI_r ) +{ + return m_si(0) ? 1 : 0; +} + +READ8_MEMBER( namco_52xx_device::R0_r ) +{ + return m_romread(m_address) & 0x0f; +} + +READ8_MEMBER( namco_52xx_device::R1_r ) +{ + return m_romread(m_address) >> 4; } - -static TIMER_CALLBACK( namco_52xx_latch_callback ) +WRITE8_MEMBER( namco_52xx_device::P_w ) { - namco_52xx_state *state = get_safe_token((device_t *)ptr); - state->m_latched_cmd = param; + discrete_sound_w(m_discrete, space, NAMCO_52XX_P_DATA(m_basenode), data & 0x0f); } -static READ8_HANDLER( namco_52xx_K_r ) +WRITE8_MEMBER( namco_52xx_device::R2_w ) { - namco_52xx_state *state = get_safe_token(space.device().owner()); - return state->m_latched_cmd & 0x0f; + m_address = (m_address & 0xfff0) | ((data & 0xf) << 0); } -static READ8_HANDLER( namco_52xx_SI_r ) +WRITE8_MEMBER( namco_52xx_device::R3_w ) { - namco_52xx_state *state = get_safe_token(space.device().owner()); - return state->m_si(0) ? 1 : 0; + m_address = (m_address & 0xff0f) | ((data & 0xf) << 4); } -static READ8_HANDLER( namco_52xx_R0_r ) +WRITE8_MEMBER( namco_52xx_device::O_w ) { - namco_52xx_state *state = get_safe_token(space.device().owner()); - return state->m_romread(state->m_address) & 0x0f; -} - -static READ8_HANDLER( namco_52xx_R1_r ) -{ - namco_52xx_state *state = get_safe_token(space.device().owner()); - return state->m_romread(state->m_address) >> 4; -} - - -static WRITE8_HANDLER( namco_52xx_P_w ) -{ - namco_52xx_state *state = get_safe_token(space.device().owner()); - discrete_sound_w(state->m_discrete, space, NAMCO_52XX_P_DATA(state->m_basenode), data & 0x0f); -} - -static WRITE8_HANDLER( namco_52xx_R2_w ) -{ - namco_52xx_state *state = get_safe_token(space.device().owner()); - state->m_address = (state->m_address & 0xfff0) | ((data & 0xf) << 0); -} - -static WRITE8_HANDLER( namco_52xx_R3_w ) -{ - namco_52xx_state *state = get_safe_token(space.device().owner()); - state->m_address = (state->m_address & 0xff0f) | ((data & 0xf) << 4); -} - -static WRITE8_HANDLER( namco_52xx_O_w ) -{ - namco_52xx_state *state = get_safe_token(space.device().owner()); if (data & 0x10) - state->m_address = (state->m_address & 0x0fff) | ((data & 0xf) << 12); + m_address = (m_address & 0x0fff) | ((data & 0xf) << 12); else - state->m_address = (state->m_address & 0xf0ff) | ((data & 0xf) << 8); + m_address = (m_address & 0xf0ff) | ((data & 0xf) << 8); } - - - -static TIMER_CALLBACK( namco_52xx_irq_clear ) +TIMER_CALLBACK_MEMBER( namco_52xx_device::irq_clear ) { - namco_52xx_state *state = get_safe_token((device_t *)ptr); - state->m_cpu->set_input_line(0, CLEAR_LINE); + m_cpu->set_input_line(0, CLEAR_LINE); } -WRITE8_DEVICE_HANDLER( namco_52xx_write ) +WRITE8_MEMBER( namco_52xx_device::write ) { - namco_52xx_state *state = get_safe_token(device); + machine().scheduler().synchronize(timer_expired_delegate(FUNC(namco_52xx_device::latch_callback),this), data); - space.machine().scheduler().synchronize(FUNC(namco_52xx_latch_callback), data, (void *)device); - - state->m_cpu->set_input_line(0, ASSERT_LINE); + m_cpu->set_input_line(0, ASSERT_LINE); // The execution time of one instruction is ~4us, so we must make sure to // give the cpu time to poll the /IRQ input before we clear it. @@ -156,15 +118,14 @@ WRITE8_DEVICE_HANDLER( namco_52xx_write ) /* the 52xx uses TSTI to check for an interrupt; it also may be handling a timer interrupt, so we need to ensure the IRQ line is held long enough */ - space.machine().scheduler().timer_set(attotime::from_usec(5*21), FUNC(namco_52xx_irq_clear), 0, (void *)device); + machine().scheduler().timer_set(attotime::from_usec(5*21), timer_expired_delegate(FUNC(namco_52xx_device::irq_clear),this), 0); } -static TIMER_CALLBACK( external_clock_pulse ) +TIMER_CALLBACK_MEMBER( namco_52xx_device::external_clock_pulse ) { - namco_52xx_state *state = get_safe_token((device_t *)ptr); - state->m_cpu->clock_w(ASSERT_LINE); - state->m_cpu->clock_w(CLEAR_LINE); + m_cpu->clock_w(ASSERT_LINE); + m_cpu->clock_w(CLEAR_LINE); } @@ -173,14 +134,14 @@ static TIMER_CALLBACK( external_clock_pulse ) ***************************************************************************/ static ADDRESS_MAP_START( namco_52xx_map_io, AS_IO, 8, namco_52xx_device ) - AM_RANGE(MB88_PORTK, MB88_PORTK) AM_READ_LEGACY(namco_52xx_K_r) - AM_RANGE(MB88_PORTO, MB88_PORTO) AM_WRITE_LEGACY(namco_52xx_O_w) - AM_RANGE(MB88_PORTP, MB88_PORTP) AM_WRITE_LEGACY(namco_52xx_P_w) - AM_RANGE(MB88_PORTSI, MB88_PORTSI) AM_READ_LEGACY(namco_52xx_SI_r) - AM_RANGE(MB88_PORTR0, MB88_PORTR0) AM_READ_LEGACY(namco_52xx_R0_r) - AM_RANGE(MB88_PORTR1, MB88_PORTR1) AM_READ_LEGACY(namco_52xx_R1_r) - AM_RANGE(MB88_PORTR2, MB88_PORTR2) AM_WRITE_LEGACY(namco_52xx_R2_w) - AM_RANGE(MB88_PORTR3, MB88_PORTR3) AM_WRITE_LEGACY(namco_52xx_R3_w) + AM_RANGE(MB88_PORTK, MB88_PORTK) AM_READ(K_r) + AM_RANGE(MB88_PORTO, MB88_PORTO) AM_WRITE(O_w) + AM_RANGE(MB88_PORTP, MB88_PORTP) AM_WRITE(P_w) + AM_RANGE(MB88_PORTSI, MB88_PORTSI) AM_READ(SI_r) + AM_RANGE(MB88_PORTR0, MB88_PORTR0) AM_READ(R0_r) + AM_RANGE(MB88_PORTR1, MB88_PORTR1) AM_READ(R1_r) + AM_RANGE(MB88_PORTR2, MB88_PORTR2) AM_WRITE(R2_w) + AM_RANGE(MB88_PORTR3, MB88_PORTR3) AM_WRITE(R3_w) ADDRESS_MAP_END @@ -196,47 +157,17 @@ ROM_START( namco_52xx ) ROM_END -/*------------------------------------------------- - device start callback --------------------------------------------------*/ - -static DEVICE_START( namco_52xx ) -{ - namco_52xx_interface *intf = (namco_52xx_interface *)device->static_config(); - namco_52xx_state *state = get_safe_token(device); - astring tempstring; - - /* find our CPU */ - state->m_cpu = device->subdevice("mcu"); - assert(state->m_cpu != NULL); - - /* find the attached discrete sound device */ - assert(intf->discrete != NULL); - state->m_discrete = device->machine().device(intf->discrete); - assert(state->m_discrete != NULL); - state->m_basenode = intf->firstnode; - - /* resolve our read/write callbacks */ - state->m_romread.resolve(intf->romread, *device); - state->m_si.resolve(intf->si, *device); - - /* start the external clock */ - if (intf->extclock != 0) - device->machine().scheduler().timer_pulse(attotime(0, intf->extclock), FUNC(external_clock_pulse), 0, device); -} - - const device_type NAMCO_52XX = &device_creator; namco_52xx_device::namco_52xx_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) - : device_t(mconfig, NAMCO_52XX, "Namco 52xx", tag, owner, clock, "namco52", __FILE__) + : device_t(mconfig, NAMCO_52XX, "Namco 52xx", tag, owner, clock, "namco52", __FILE__), + m_cpu(*this, "mcu"), + m_discrete(*this), + m_basenode(0), + m_extclock(0), + m_romread(*this), + m_si(*this) { - m_token = global_alloc_clear(namco_52xx_state); -} - -namco_52xx_device::~namco_52xx_device() -{ - global_free(m_token); } //------------------------------------------------- @@ -245,7 +176,13 @@ namco_52xx_device::~namco_52xx_device() void namco_52xx_device::device_start() { - DEVICE_START_NAME( namco_52xx )(this); + /* resolve our read/write callbacks */ + m_romread.resolve_safe(0); + m_si.resolve_safe(0); + + /* start the external clock */ + if (m_extclock != 0) + machine().scheduler().timer_pulse(attotime(0, m_extclock), timer_expired_delegate(FUNC(namco_52xx_device::external_clock_pulse),this), 0); } //------------------------------------------------- diff --git a/src/mame/audio/namco52.h b/src/mame/audio/namco52.h index 48c00b8262d..50419704c8b 100644 --- a/src/mame/audio/namco52.h +++ b/src/mame/audio/namco52.h @@ -4,42 +4,70 @@ #define NAMCO52_H #include "sound/discrete.h" +#include "cpu/mb88xx/mb88xx.h" +#define MCFG_NAMCO_52XX_ADD(_tag, _clock) \ + MCFG_DEVICE_ADD(_tag, NAMCO_52XX, _clock) -struct namco_52xx_interface -{ - const char * discrete; /* name of the discrete sound device */ - int firstnode; /* index of the first node */ - attoseconds_t extclock; /* external clock period */ - devcb_read8 romread; /* ROM read handler */ - devcb_read8 si; /* SI (pin 6) read handler */ -}; +#define MCFG_NAMCO_52XX_DICRETE(_tag) \ + namco_52xx_device::set_discrete(*device, "^" _tag); +#define MCFG_NAMCO_52XX_BASENODE(_node) \ + namco_52xx_device::set_basenote(*device, _node); -#define MCFG_NAMCO_52XX_ADD(_tag, _clock, _interface) \ - MCFG_DEVICE_ADD(_tag, NAMCO_52XX, _clock) \ - MCFG_DEVICE_CONFIG(_interface) +#define MCFG_NAMCO_52XX_EXT_CLOCK(_clock) \ + namco_52xx_device::set_extclock(*device, _clock); +#define MCFG_NAMCO_52XX_ROMREAD_CB(_devcb) \ + devcb = &namco_52xx_device::set_romread_callback(*device, DEVCB2_##_devcb); -DECLARE_WRITE8_DEVICE_HANDLER( namco_52xx_write ); - +#define MCFG_NAMCO_52XX_SI_CB(_devcb) \ + devcb = &namco_52xx_device::set_si_callback(*device, DEVCB2_##_devcb); + class namco_52xx_device : public device_t { public: namco_52xx_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); - ~namco_52xx_device(); - // access to legacy token - struct namco_52xx_state *token() const { assert(m_token != NULL); return m_token; } + static void set_discrete(device_t &device, const char *tag) { downcast(device).m_discrete.set_tag(tag); } + static void set_basenote(device_t &device, int node) { downcast(device).m_basenode = node; } + static void set_extclock(device_t &device, attoseconds_t clk) { downcast(device).m_extclock = clk; } + template static devcb2_base &set_romread_callback(device_t &device, _Object object) { return downcast(device).m_romread.set_callback(object); } + template static devcb2_base &set_si_callback(device_t &device, _Object object) { return downcast(device).m_si.set_callback(object); } + + DECLARE_WRITE8_MEMBER(write); + + DECLARE_READ8_MEMBER( K_r ); + DECLARE_READ8_MEMBER( SI_r ); + DECLARE_READ8_MEMBER( R0_r ); + DECLARE_READ8_MEMBER( R1_r ); + DECLARE_WRITE8_MEMBER( P_w ); + DECLARE_WRITE8_MEMBER( R2_w ); + DECLARE_WRITE8_MEMBER( R3_w ); + DECLARE_WRITE8_MEMBER( O_w ); + protected: // device-level overrides virtual void device_start(); virtual const rom_entry *device_rom_region() const; virtual machine_config_constructor device_mconfig_additions() const; + + TIMER_CALLBACK_MEMBER( latch_callback ); + TIMER_CALLBACK_MEMBER( irq_clear ); + TIMER_CALLBACK_MEMBER( external_clock_pulse ); private: // internal state - struct namco_52xx_state *m_token; + required_device m_cpu; + required_device m_discrete; + + int m_basenode; + attoseconds_t m_extclock; + devcb2_read8 m_romread; + devcb2_read8 m_si; + + UINT8 m_latched_cmd; + UINT32 m_address; }; extern const device_type NAMCO_52XX; diff --git a/src/mame/audio/namco54.c b/src/mame/audio/namco54.c index e14d9b3cb6e..23359fa6f1f 100644 --- a/src/mame/audio/namco54.c +++ b/src/mame/audio/namco54.c @@ -51,87 +51,56 @@ #include "emu.h" #include "namco54.h" -#include "cpu/mb88xx/mb88xx.h" -#include "devlegcy.h" -struct namco_54xx_state +TIMER_CALLBACK_MEMBER( namco_54xx_device::latch_callback ) { - device_t *m_cpu; - device_t *m_discrete; - int m_basenode; - UINT8 m_latched_cmd; -}; - -INLINE namco_54xx_state *get_safe_token(device_t *device) -{ - assert(device != NULL); - assert(device->type() == NAMCO_54XX); - - return (namco_54xx_state *)downcast(device)->token(); + m_latched_cmd = param; } - - -static TIMER_CALLBACK( namco_54xx_latch_callback ) -{ - namco_54xx_state *state = get_safe_token((device_t *)ptr); - state->m_latched_cmd = param; +READ8_MEMBER( namco_54xx_device::K_r ) +{ + return m_latched_cmd >> 4; } -static READ8_HANDLER( namco_54xx_K_r ) +READ8_MEMBER( namco_54xx_device::R0_r ) { - namco_54xx_state *state = get_safe_token(space.device().owner()); - return state->m_latched_cmd >> 4; + return m_latched_cmd & 0x0f; } -static READ8_HANDLER( namco_54xx_R0_r ) +WRITE8_MEMBER( namco_54xx_device::O_w ) { - namco_54xx_state *state = get_safe_token(space.device().owner()); - return state->m_latched_cmd & 0x0f; -} - - -static WRITE8_HANDLER( namco_54xx_O_w ) -{ - namco_54xx_state *state = get_safe_token(space.device().owner()); UINT8 out = (data & 0x0f); if (data & 0x10) - discrete_sound_w(state->m_discrete, space, NAMCO_54XX_1_DATA(state->m_basenode), out); + discrete_sound_w(m_discrete, space, NAMCO_54XX_1_DATA(m_basenode), out); else - discrete_sound_w(state->m_discrete, space, NAMCO_54XX_0_DATA(state->m_basenode), out); + discrete_sound_w(m_discrete, space, NAMCO_54XX_0_DATA(m_basenode), out); } -static WRITE8_HANDLER( namco_54xx_R1_w ) +WRITE8_MEMBER( namco_54xx_device::R1_w ) { - namco_54xx_state *state = get_safe_token(space.device().owner()); UINT8 out = (data & 0x0f); - discrete_sound_w(state->m_discrete, space, NAMCO_54XX_2_DATA(state->m_basenode), out); + discrete_sound_w(m_discrete, space, NAMCO_54XX_2_DATA(m_basenode), out); } - - -static TIMER_CALLBACK( namco_54xx_irq_clear ) +TIMER_CALLBACK_MEMBER( namco_54xx_device::irq_clear ) { - namco_54xx_state *state = get_safe_token((device_t *)ptr); - state->m_cpu->execute().set_input_line(0, CLEAR_LINE); + m_cpu->set_input_line(0, CLEAR_LINE); } -WRITE8_DEVICE_HANDLER( namco_54xx_write ) +WRITE8_MEMBER( namco_54xx_device::write ) { - namco_54xx_state *state = get_safe_token(device); + machine().scheduler().synchronize(timer_expired_delegate(FUNC(namco_54xx_device::latch_callback),this), data); - space.machine().scheduler().synchronize(FUNC(namco_54xx_latch_callback), data, (void *)device); - - state->m_cpu->execute().set_input_line(0, ASSERT_LINE); + m_cpu->set_input_line(0, ASSERT_LINE); // The execution time of one instruction is ~4us, so we must make sure to // give the cpu time to poll the /IRQ input before we clear it. // The input clock to the 06XX interface chip is 64H, that is // 18432000/6/64 = 48kHz, so it makes sense for the irq line to be // asserted for one clock cycle ~= 21us. - space.machine().scheduler().timer_set(attotime::from_usec(21), FUNC(namco_54xx_irq_clear), 0, (void *)device); + machine().scheduler().timer_set(attotime::from_usec(21), timer_expired_delegate(FUNC(namco_54xx_device::irq_clear),this), 0); } @@ -140,10 +109,10 @@ WRITE8_DEVICE_HANDLER( namco_54xx_write ) ***************************************************************************/ static ADDRESS_MAP_START( namco_54xx_map_io, AS_IO, 8, namco_54xx_device ) - AM_RANGE(MB88_PORTK, MB88_PORTK) AM_READ_LEGACY(namco_54xx_K_r) - AM_RANGE(MB88_PORTO, MB88_PORTO) AM_WRITE_LEGACY(namco_54xx_O_w) - AM_RANGE(MB88_PORTR0, MB88_PORTR0) AM_READ_LEGACY(namco_54xx_R0_r) - AM_RANGE(MB88_PORTR1, MB88_PORTR1) AM_WRITE_LEGACY(namco_54xx_R1_w) + AM_RANGE(MB88_PORTK, MB88_PORTK) AM_READ(K_r) + AM_RANGE(MB88_PORTO, MB88_PORTO) AM_WRITE(O_w) + AM_RANGE(MB88_PORTR0, MB88_PORTR0) AM_READ(R0_r) + AM_RANGE(MB88_PORTR1, MB88_PORTR1) AM_WRITE(R1_w) AM_RANGE(MB88_PORTR2, MB88_PORTR2) AM_NOP ADDRESS_MAP_END @@ -159,49 +128,21 @@ ROM_START( namco_54xx ) ROM_LOAD( "54xx.bin", 0x0000, 0x0400, CRC(ee7357e0) SHA1(01bdf984a49e8d0cc8761b2cc162fd6434d5afbe) ) ROM_END - -/*------------------------------------------------- - device start callback --------------------------------------------------*/ - -static DEVICE_START( namco_54xx ) -{ - namco_54xx_config *config = (namco_54xx_config *)device->static_config(); - namco_54xx_state *state = get_safe_token(device); - astring tempstring; - - /* find our CPU */ - state->m_cpu = device->subdevice("mcu"); - assert(state->m_cpu != NULL); - - /* find the attached discrete sound device */ - assert(config->discrete != NULL); - state->m_discrete = device->machine().device(config->discrete); - assert(state->m_discrete != NULL); - state->m_basenode = config->firstnode; -} - - const device_type NAMCO_54XX = &device_creator; namco_54xx_device::namco_54xx_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) - : device_t(mconfig, NAMCO_54XX, "Namco 54xx", tag, owner, clock, "namco54", __FILE__) + : device_t(mconfig, NAMCO_54XX, "Namco 54xx", tag, owner, clock, "namco54", __FILE__), + m_cpu(*this, "mcu"), + m_discrete(*this), + m_basenode(0) { - m_token = global_alloc_clear(namco_54xx_state); } - -namco_54xx_device::~namco_54xx_device() -{ - global_free(m_token); -} - //------------------------------------------------- // device_start - device-specific startup //------------------------------------------------- void namco_54xx_device::device_start() { - DEVICE_START_NAME( namco_54xx )(this); } //------------------------------------------------- diff --git a/src/mame/audio/namco54.h b/src/mame/audio/namco54.h index 3dd9c61d58c..08d06144e36 100644 --- a/src/mame/audio/namco54.h +++ b/src/mame/audio/namco54.h @@ -4,6 +4,7 @@ #define NAMCO54_H #include "sound/discrete.h" +#include "cpu/mb88xx/mb88xx.h" struct namco_54xx_config @@ -13,9 +14,14 @@ struct namco_54xx_config }; -#define MCFG_NAMCO_54XX_ADD(_tag, _clock, _config) \ - MCFG_DEVICE_ADD(_tag, NAMCO_54XX, _clock) \ - MCFG_DEVICE_CONFIG(_config) +#define MCFG_NAMCO_54XX_ADD(_tag, _clock) \ + MCFG_DEVICE_ADD(_tag, NAMCO_54XX, _clock) + +#define MCFG_NAMCO_54XX_DICRETE(_tag) \ + namco_54xx_device::set_discrete(*device, "^" _tag); + +#define MCFG_NAMCO_54XX_BASENODE(_node) \ + namco_54xx_device::set_basenote(*device, _node); DECLARE_WRITE8_DEVICE_HANDLER( namco_54xx_write ); @@ -25,18 +31,31 @@ class namco_54xx_device : public device_t { public: namco_54xx_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); - ~namco_54xx_device(); - // access to legacy token - struct namco_54xx_state *token() const { assert(m_token != NULL); return m_token; } + static void set_discrete(device_t &device, const char *tag) { downcast(device).m_discrete.set_tag(tag); } + static void set_basenote(device_t &device, int node) { downcast(device).m_basenode = node; } + + DECLARE_READ8_MEMBER( K_r ); + DECLARE_READ8_MEMBER( R0_r ); + DECLARE_WRITE8_MEMBER( O_w ); + DECLARE_WRITE8_MEMBER( R1_w ); + + DECLARE_WRITE8_MEMBER( write ); protected: // device-level overrides virtual void device_start(); virtual const rom_entry *device_rom_region() const; virtual machine_config_constructor device_mconfig_additions() const; + + TIMER_CALLBACK_MEMBER( latch_callback ); + TIMER_CALLBACK_MEMBER( irq_clear ); private: // internal state - struct namco_54xx_state *m_token; + required_device m_cpu; + required_device m_discrete; + + int m_basenode; + UINT8 m_latched_cmd; }; extern const device_type NAMCO_54XX; diff --git a/src/mame/drivers/galaga.c b/src/mame/drivers/galaga.c index d03d8b9dacb..3a6a4454a55 100644 --- a/src/mame/drivers/galaga.c +++ b/src/mame/drivers/galaga.c @@ -792,21 +792,6 @@ WRITE8_MEMBER(galaga_state::out_1) coin_lockout_global_w(machine(), data & 1); } -static const namco_51xx_interface namco_51xx_intf = -{ - { /* port read handlers */ - DEVCB_INPUT_PORT("IN0L"), - DEVCB_INPUT_PORT("IN0H"), - DEVCB_INPUT_PORT("IN1L"), - DEVCB_INPUT_PORT("IN1H") - }, - { /* port write handlers */ - DEVCB_DRIVER_MEMBER(galaga_state,out_0), - DEVCB_DRIVER_MEMBER(galaga_state,out_1) - } -}; - - READ8_MEMBER(galaga_state::namco_52xx_rom_r) { UINT32 length = memregion("52xx")->bytes(); @@ -828,35 +813,12 @@ READ8_MEMBER(galaga_state::namco_52xx_si_r) return 0; } -static const namco_52xx_interface namco_52xx_intf = -{ - "discrete", /* name of the discrete sound device */ - NODE_04, /* index of the first node */ - ATTOSECONDS_IN_NSEC(PERIOD_OF_555_ASTABLE_NSEC(RES_K(33), RES_K(10), CAP_U(0.0047))), /* external clock rate */ - DEVCB_DRIVER_MEMBER(galaga_state,namco_52xx_rom_r), /* ROM read handler */ - DEVCB_DRIVER_MEMBER(galaga_state,namco_52xx_si_r) /* SI (pin 6) read handler */ -}; - - READ8_MEMBER(galaga_state::custom_mod_r) { /* MOD0-2 is connected to K1-3; K0 is left unconnected */ return m_custom_mod << 1; } -static const namco_53xx_interface namco_53xx_intf = -{ - DEVCB_DRIVER_MEMBER(galaga_state,custom_mod_r), /* K port */ - { - DEVCB_INPUT_PORT("DSWA"), /* R0 port */ - DEVCB_INPUT_PORT("DSWA_HI"), /* R1 port */ - DEVCB_INPUT_PORT("DSWB"), /* R2 port */ - DEVCB_INPUT_PORT("DSWB_HI") /* R3 port */ - }, - DEVCB_NULL /* P port */ -}; - - TIMER_CALLBACK_MEMBER(galaga_state::cpu3_interrupt_callback) { int scanline = param; @@ -916,12 +878,12 @@ static ADDRESS_MAP_START( bosco_map, AS_PROGRAM, 8, bosco_state ) AM_RANGE(0x6800, 0x681f) AM_DEVWRITE("namco", namco_device, pacman_sound_w) AM_RANGE(0x6820, 0x6827) AM_WRITE(bosco_latch_w) /* misc latches */ AM_RANGE(0x6830, 0x6830) AM_WRITE(watchdog_reset_w) - AM_RANGE(0x7000, 0x70ff) AM_DEVREADWRITE_LEGACY("06xx_0", namco_06xx_data_r, namco_06xx_data_w) - AM_RANGE(0x7100, 0x7100) AM_DEVREADWRITE_LEGACY("06xx_0", namco_06xx_ctrl_r, namco_06xx_ctrl_w) + AM_RANGE(0x7000, 0x70ff) AM_DEVREADWRITE("06xx_0", namco_06xx_device, data_r, data_w) + AM_RANGE(0x7100, 0x7100) AM_DEVREADWRITE("06xx_0", namco_06xx_device, ctrl_r, ctrl_w) AM_RANGE(0x7800, 0x7fff) AM_RAM AM_SHARE("share1") AM_RANGE(0x8000, 0x8fff) AM_RAM_WRITE(bosco_videoram_w) AM_SHARE("videoram")/* + sprite registers */ - AM_RANGE(0x9000, 0x90ff) AM_DEVREADWRITE_LEGACY("06xx_1", namco_06xx_data_r, namco_06xx_data_w) - AM_RANGE(0x9100, 0x9100) AM_DEVREADWRITE_LEGACY("06xx_1", namco_06xx_ctrl_r, namco_06xx_ctrl_w) + AM_RANGE(0x9000, 0x90ff) AM_DEVREADWRITE("06xx_1", namco_06xx_device, data_r, data_w) + AM_RANGE(0x9100, 0x9100) AM_DEVREADWRITE("06xx_1", namco_06xx_device, ctrl_r, ctrl_w) AM_RANGE(0x9800, 0x980f) AM_WRITEONLY AM_SHARE("bosco_radarattr") AM_RANGE(0x9810, 0x9810) AM_WRITE(bosco_scrollx_w) AM_RANGE(0x9820, 0x9820) AM_WRITE(bosco_scrolly_w) @@ -938,8 +900,8 @@ static ADDRESS_MAP_START( galaga_map, AS_PROGRAM, 8, galaga_state ) AM_RANGE(0x6800, 0x681f) AM_DEVWRITE("namco", namco_device, pacman_sound_w) AM_RANGE(0x6820, 0x6827) AM_WRITE(bosco_latch_w) /* misc latches */ AM_RANGE(0x6830, 0x6830) AM_WRITE(watchdog_reset_w) - AM_RANGE(0x7000, 0x70ff) AM_DEVREADWRITE_LEGACY("06xx", namco_06xx_data_r, namco_06xx_data_w) - AM_RANGE(0x7100, 0x7100) AM_DEVREADWRITE_LEGACY("06xx", namco_06xx_ctrl_r, namco_06xx_ctrl_w) + AM_RANGE(0x7000, 0x70ff) AM_DEVREADWRITE("06xx", namco_06xx_device, data_r, data_w) + AM_RANGE(0x7100, 0x7100) AM_DEVREADWRITE("06xx", namco_06xx_device, ctrl_r, ctrl_w) AM_RANGE(0x8000, 0x87ff) AM_RAM_WRITE(galaga_videoram_w) AM_SHARE("videoram") AM_RANGE(0x8800, 0x8bff) AM_RAM AM_SHARE("galaga_ram1") AM_RANGE(0x9000, 0x93ff) AM_RAM AM_SHARE("galaga_ram2") @@ -955,8 +917,8 @@ static ADDRESS_MAP_START( xevious_map, AS_PROGRAM, 8, xevious_state ) AM_RANGE(0x6800, 0x681f) AM_DEVWRITE("namco", namco_device, pacman_sound_w) AM_RANGE(0x6820, 0x6827) AM_WRITE(bosco_latch_w) /* misc latches */ AM_RANGE(0x6830, 0x6830) AM_WRITE(watchdog_reset_w) - AM_RANGE(0x7000, 0x70ff) AM_DEVREADWRITE_LEGACY("06xx", namco_06xx_data_r, namco_06xx_data_w) - AM_RANGE(0x7100, 0x7100) AM_DEVREADWRITE_LEGACY("06xx", namco_06xx_ctrl_r, namco_06xx_ctrl_w) + AM_RANGE(0x7000, 0x70ff) AM_DEVREADWRITE("06xx", namco_06xx_device, data_r, data_w) + AM_RANGE(0x7100, 0x7100) AM_DEVREADWRITE("06xx", namco_06xx_device, ctrl_r, ctrl_w) AM_RANGE(0x7800, 0x7fff) AM_RAM AM_SHARE("share1") /* work RAM */ AM_RANGE(0x8000, 0x87ff) AM_RAM AM_SHARE("xevious_sr1") /* work RAM + sprite registers */ AM_RANGE(0x9000, 0x97ff) AM_RAM AM_SHARE("xevious_sr2") /* work RAM + sprite registers */ @@ -975,8 +937,8 @@ static ADDRESS_MAP_START( digdug_map, AS_PROGRAM, 8, digdug_state ) AM_RANGE(0x6800, 0x681f) AM_DEVWRITE("namco", namco_device, pacman_sound_w) AM_RANGE(0x6820, 0x6827) AM_WRITE(bosco_latch_w) /* misc latches */ AM_RANGE(0x6830, 0x6830) AM_WRITE(watchdog_reset_w) - AM_RANGE(0x7000, 0x70ff) AM_DEVREADWRITE_LEGACY("06xx", namco_06xx_data_r, namco_06xx_data_w) - AM_RANGE(0x7100, 0x7100) AM_DEVREADWRITE_LEGACY("06xx", namco_06xx_ctrl_r, namco_06xx_ctrl_w) + AM_RANGE(0x7000, 0x70ff) AM_DEVREADWRITE("06xx", namco_06xx_device, data_r, data_w) + AM_RANGE(0x7100, 0x7100) AM_DEVREADWRITE("06xx", namco_06xx_device, ctrl_r, ctrl_w) AM_RANGE(0x8000, 0x83ff) AM_RAM_WRITE(digdug_videoram_w) AM_SHARE("videoram") /* tilemap RAM (bottom half of RAM 0 */ AM_RANGE(0x8400, 0x87ff) AM_RAM AM_SHARE("share1") /* work RAM (top half for RAM 0 */ AM_RANGE(0x8800, 0x8bff) AM_RAM AM_SHARE("digdug_objram") /* work RAM + sprite registers */ @@ -1645,21 +1607,6 @@ INTERRUPT_GEN_MEMBER(galaga_state::sub_vblank_irq) device.execute().set_input_line(0, ASSERT_LINE); } -const namco_06xx_config bosco_namco_06xx_0_intf = -{ - "maincpu", "51xx", NULL, "50xx_1", "54xx" -}; - -const namco_06xx_config bosco_namco_06xx_1_intf = -{ - "sub", "50xx_2", "52xx", NULL, NULL -}; - -const namco_54xx_config namco_54xx_intf = -{ - "discrete", NODE_01 -}; - static MACHINE_CONFIG_START( bosco, bosco_state ) /* basic machine hardware */ @@ -1676,12 +1623,41 @@ static MACHINE_CONFIG_START( bosco, bosco_state ) MCFG_NAMCO_50XX_ADD("50xx_1", MASTER_CLOCK/6/2) /* 1.536 MHz */ MCFG_NAMCO_50XX_ADD("50xx_2", MASTER_CLOCK/6/2) /* 1.536 MHz */ - MCFG_NAMCO_51XX_ADD("51xx", MASTER_CLOCK/6/2, namco_51xx_intf) /* 1.536 MHz */ - MCFG_NAMCO_52XX_ADD("52xx", MASTER_CLOCK/6/2, namco_52xx_intf) /* 1.536 MHz */ - MCFG_NAMCO_54XX_ADD("54xx", MASTER_CLOCK/6/2, namco_54xx_intf) /* 1.536 MHz */ + MCFG_NAMCO_51XX_ADD("51xx", MASTER_CLOCK/6/2) /* 1.536 MHz */ + MCFG_NAMCO_51XX_INPUT_0_CB(IOPORT("IN0L")) + MCFG_NAMCO_51XX_INPUT_1_CB(IOPORT("IN0H")) + MCFG_NAMCO_51XX_INPUT_2_CB(IOPORT("IN1L")) + MCFG_NAMCO_51XX_INPUT_3_CB(IOPORT("IN1H")) + MCFG_NAMCO_51XX_OUTPUT_0_CB(WRITE8(galaga_state,out_0)) + MCFG_NAMCO_51XX_OUTPUT_1_CB(WRITE8(galaga_state,out_1)) + + + MCFG_NAMCO_52XX_ADD("52xx", MASTER_CLOCK/6/2) /* 1.536 MHz */ + MCFG_NAMCO_52XX_DICRETE("discrete") + MCFG_NAMCO_52XX_BASENODE(NODE_04) + MCFG_NAMCO_52XX_EXT_CLOCK(ATTOSECONDS_IN_NSEC(PERIOD_OF_555_ASTABLE_NSEC(RES_K(33), RES_K(10), CAP_U(0.0047)))) + MCFG_NAMCO_52XX_ROMREAD_CB(READ8(galaga_state,namco_52xx_rom_r)) + MCFG_NAMCO_52XX_SI_CB(READ8(galaga_state,namco_52xx_si_r)) - MCFG_NAMCO_06XX_ADD("06xx_0", MASTER_CLOCK/6/64, bosco_namco_06xx_0_intf) - MCFG_NAMCO_06XX_ADD("06xx_1", MASTER_CLOCK/6/64, bosco_namco_06xx_1_intf) + MCFG_NAMCO_54XX_ADD("54xx", MASTER_CLOCK/6/2) /* 1.536 MHz */ + MCFG_NAMCO_54XX_DICRETE("discrete") + MCFG_NAMCO_54XX_BASENODE(NODE_01) + + MCFG_NAMCO_06XX_ADD("06xx_0", MASTER_CLOCK/6/64) + MCFG_NAMCO_06XX_MAINCPU("maincpu") + MCFG_NAMCO_06XX_READ_0_CB(DEVREAD8("51xx", namco_51xx_device, read)) + MCFG_NAMCO_06XX_WRITE_0_CB(DEVWRITE8("51xx", namco_51xx_device, write)) + MCFG_NAMCO_06XX_READ_2_CB(DEVREAD8("50xx_1", namco_50xx_device, read)) + MCFG_NAMCO_06XX_READ_REQUEST_2_CB(DEVWRITELINE("50xx_1", namco_50xx_device, read_request)) + MCFG_NAMCO_06XX_WRITE_2_CB(DEVWRITE8("50xx_1", namco_50xx_device, write)) + MCFG_NAMCO_06XX_WRITE_3_CB(DEVWRITE8("54xx", namco_54xx_device, write)) + + MCFG_NAMCO_06XX_ADD("06xx_1", MASTER_CLOCK/6/64) + MCFG_NAMCO_06XX_MAINCPU("sub") + MCFG_NAMCO_06XX_READ_0_CB(DEVREAD8("50xx_2", namco_50xx_device, read)) + MCFG_NAMCO_06XX_READ_REQUEST_0_CB(DEVWRITELINE("50xx_2", namco_50xx_device, read_request)) + MCFG_NAMCO_06XX_WRITE_0_CB(DEVWRITE8("50xx_2", namco_50xx_device, write)) + MCFG_NAMCO_06XX_WRITE_1_CB(DEVWRITE8("52xx", namco_52xx_device, write)) MCFG_WATCHDOG_VBLANK_INIT(8) MCFG_QUANTUM_TIME(attotime::from_hz(6000)) /* 100 CPU slices per frame - an high value to ensure proper */ @@ -1715,12 +1691,6 @@ static MACHINE_CONFIG_START( bosco, bosco_state ) MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.90) MACHINE_CONFIG_END - -const namco_06xx_config galaga_namco_06xx_intf = -{ - "maincpu", "51xx", NULL, NULL, "54xx" -}; - static MACHINE_CONFIG_START( galaga, galaga_state ) /* basic machine hardware */ @@ -1735,11 +1705,24 @@ static MACHINE_CONFIG_START( galaga, galaga_state ) MCFG_CPU_ADD("sub2", Z80, MASTER_CLOCK/6) /* 3.072 MHz */ MCFG_CPU_PROGRAM_MAP(galaga_map) - MCFG_NAMCO_51XX_ADD("51xx", MASTER_CLOCK/6/2, namco_51xx_intf) /* 1.536 MHz */ - MCFG_NAMCO_54XX_ADD("54xx", MASTER_CLOCK/6/2, namco_54xx_intf) /* 1.536 MHz */ - - MCFG_NAMCO_06XX_ADD("06xx", MASTER_CLOCK/6/64, galaga_namco_06xx_intf) + MCFG_NAMCO_51XX_ADD("51xx", MASTER_CLOCK/6/2) /* 1.536 MHz */ + MCFG_NAMCO_51XX_INPUT_0_CB(IOPORT("IN0L")) + MCFG_NAMCO_51XX_INPUT_1_CB(IOPORT("IN0H")) + MCFG_NAMCO_51XX_INPUT_2_CB(IOPORT("IN1L")) + MCFG_NAMCO_51XX_INPUT_3_CB(IOPORT("IN1H")) + MCFG_NAMCO_51XX_OUTPUT_0_CB(WRITE8(galaga_state,out_0)) + MCFG_NAMCO_51XX_OUTPUT_1_CB(WRITE8(galaga_state,out_1)) + + MCFG_NAMCO_54XX_ADD("54xx", MASTER_CLOCK/6/2) /* 1.536 MHz */ + MCFG_NAMCO_54XX_DICRETE("discrete") + MCFG_NAMCO_54XX_BASENODE(NODE_01) + MCFG_NAMCO_06XX_ADD("06xx", MASTER_CLOCK/6/64) + MCFG_NAMCO_06XX_MAINCPU("maincpu") + MCFG_NAMCO_06XX_READ_0_CB(DEVREAD8("51xx", namco_51xx_device, read)) + MCFG_NAMCO_06XX_WRITE_0_CB(DEVWRITE8("51xx", namco_51xx_device, write)) + MCFG_NAMCO_06XX_WRITE_3_CB(DEVWRITE8("54xx", namco_54xx_device, write)) + MCFG_WATCHDOG_VBLANK_INIT(8) MCFG_QUANTUM_TIME(attotime::from_hz(6000)) /* 100 CPU slices per frame - an high value to ensure proper */ /* synchronization of the CPUs */ @@ -1772,11 +1755,6 @@ static MACHINE_CONFIG_START( galaga, galaga_state ) MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.90) MACHINE_CONFIG_END -const namco_06xx_config galagab_namco_06xx_intf = -{ - "maincpu", "51xx", NULL, NULL, NULL -}; - static MACHINE_CONFIG_DERIVED( galagab, galaga ) /* basic machine hardware */ @@ -1785,8 +1763,11 @@ static MACHINE_CONFIG_DERIVED( galagab, galaga ) MCFG_DEVICE_REMOVE("06xx") /* FIXME: bootlegs should not have any Namco custom chip. However, this workaround is needed atm */ - MCFG_NAMCO_06XX_ADD("06xx", MASTER_CLOCK/6/64, galagab_namco_06xx_intf) - + MCFG_NAMCO_06XX_ADD("06xx", MASTER_CLOCK/6/64) + MCFG_NAMCO_06XX_MAINCPU("maincpu") + MCFG_NAMCO_06XX_READ_0_CB(DEVREAD8("51xx", namco_51xx_device, read)) + MCFG_NAMCO_06XX_WRITE_0_CB(DEVWRITE8("51xx", namco_51xx_device, write)) + MCFG_CPU_ADD("sub3", Z80, MASTER_CLOCK/6) /* 3.072 MHz */ MCFG_CPU_PROGRAM_MAP(galaga_mem4) @@ -1794,11 +1775,6 @@ static MACHINE_CONFIG_DERIVED( galagab, galaga ) MCFG_DEVICE_REMOVE("discrete") MACHINE_CONFIG_END -const namco_06xx_config xevious_namco_06xx_intf = -{ - "maincpu", "51xx", NULL, "50xx", "54xx" -}; - static MACHINE_CONFIG_START( xevious, xevious_state ) /* basic machine hardware */ @@ -1814,10 +1790,27 @@ static MACHINE_CONFIG_START( xevious, xevious_state ) MCFG_CPU_PROGRAM_MAP(xevious_map) MCFG_NAMCO_50XX_ADD("50xx", MASTER_CLOCK/6/2) /* 1.536 MHz */ - MCFG_NAMCO_51XX_ADD("51xx", MASTER_CLOCK/6/2, namco_51xx_intf) /* 1.536 MHz */ - MCFG_NAMCO_54XX_ADD("54xx", MASTER_CLOCK/6/2, namco_54xx_intf) /* 1.536 MHz */ - MCFG_NAMCO_06XX_ADD("06xx", MASTER_CLOCK/6/64, xevious_namco_06xx_intf) + MCFG_NAMCO_51XX_ADD("51xx", MASTER_CLOCK/6/2) /* 1.536 MHz */ + MCFG_NAMCO_51XX_INPUT_0_CB(IOPORT("IN0L")) + MCFG_NAMCO_51XX_INPUT_1_CB(IOPORT("IN0H")) + MCFG_NAMCO_51XX_INPUT_2_CB(IOPORT("IN1L")) + MCFG_NAMCO_51XX_INPUT_3_CB(IOPORT("IN1H")) + MCFG_NAMCO_51XX_OUTPUT_0_CB(WRITE8(galaga_state,out_0)) + MCFG_NAMCO_51XX_OUTPUT_1_CB(WRITE8(galaga_state,out_1)) + + MCFG_NAMCO_54XX_ADD("54xx", MASTER_CLOCK/6/2) /* 1.536 MHz */ + MCFG_NAMCO_54XX_DICRETE("discrete") + MCFG_NAMCO_54XX_BASENODE(NODE_01) + + MCFG_NAMCO_06XX_ADD("06xx", MASTER_CLOCK/6/64) + MCFG_NAMCO_06XX_MAINCPU("maincpu") + MCFG_NAMCO_06XX_READ_0_CB(DEVREAD8("51xx", namco_51xx_device, read)) + MCFG_NAMCO_06XX_WRITE_0_CB(DEVWRITE8("51xx", namco_51xx_device, write)) + MCFG_NAMCO_06XX_READ_2_CB(DEVREAD8("50xx", namco_50xx_device, read)) + MCFG_NAMCO_06XX_READ_REQUEST_2_CB(DEVWRITELINE("50xx", namco_50xx_device, read_request)) + MCFG_NAMCO_06XX_WRITE_2_CB(DEVWRITE8("50xx", namco_50xx_device, write)) + MCFG_NAMCO_06XX_WRITE_3_CB(DEVWRITE8("54xx", namco_54xx_device, write)) MCFG_WATCHDOG_VBLANK_INIT(8) MCFG_QUANTUM_TIME(attotime::from_hz(60000)) /* 1000 CPU slices per frame - an high value to ensure proper */ @@ -1850,11 +1843,6 @@ static MACHINE_CONFIG_START( xevious, xevious_state ) MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.90) MACHINE_CONFIG_END -const namco_06xx_config battles_namco_06xx_intf = -{ - "maincpu", "51xx", NULL, NULL, NULL -}; - static MACHINE_CONFIG_DERIVED( battles, xevious ) /* basic machine hardware */ @@ -1864,7 +1852,10 @@ static MACHINE_CONFIG_DERIVED( battles, xevious ) MCFG_DEVICE_REMOVE("06xx") /* FIXME: bootlegs should not have any Namco custom chip. However, this workaround is needed atm */ - MCFG_NAMCO_06XX_ADD("06xx", MASTER_CLOCK/6/64, battles_namco_06xx_intf) + MCFG_NAMCO_06XX_ADD("06xx", MASTER_CLOCK/6/64) + MCFG_NAMCO_06XX_MAINCPU("maincpu") + MCFG_NAMCO_06XX_READ_0_CB(DEVREAD8("51xx", namco_51xx_device, read)) + MCFG_NAMCO_06XX_WRITE_0_CB(DEVWRITE8("51xx", namco_51xx_device, write)) MCFG_CPU_ADD("sub3", Z80, MASTER_CLOCK/6) /* 3.072 MHz */ MCFG_CPU_PROGRAM_MAP(battles_mem4) @@ -1885,11 +1876,6 @@ static MACHINE_CONFIG_DERIVED( battles, xevious ) MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.80) MACHINE_CONFIG_END -const namco_06xx_config digdug_namco_06xx_intf = -{ - "maincpu", "51xx", "53xx", NULL, NULL -}; - static MACHINE_CONFIG_START( digdug, digdug_state ) /* basic machine hardware */ @@ -1904,10 +1890,27 @@ static MACHINE_CONFIG_START( digdug, digdug_state ) MCFG_CPU_ADD("sub2", Z80, MASTER_CLOCK/6) /* 3.072 MHz */ MCFG_CPU_PROGRAM_MAP(digdug_map) - MCFG_NAMCO_51XX_ADD("51xx", MASTER_CLOCK/6/2, namco_51xx_intf) /* 1.536 MHz */ - MCFG_NAMCO_53XX_ADD("53xx", MASTER_CLOCK/6/2, namco_53xx_intf) /* 1.536 MHz */ + MCFG_NAMCO_51XX_ADD("51xx", MASTER_CLOCK/6/2) /* 1.536 MHz */ + MCFG_NAMCO_51XX_INPUT_0_CB(IOPORT("IN0L")) + MCFG_NAMCO_51XX_INPUT_1_CB(IOPORT("IN0H")) + MCFG_NAMCO_51XX_INPUT_2_CB(IOPORT("IN1L")) + MCFG_NAMCO_51XX_INPUT_3_CB(IOPORT("IN1H")) + MCFG_NAMCO_51XX_OUTPUT_0_CB(WRITE8(galaga_state,out_0)) + MCFG_NAMCO_51XX_OUTPUT_1_CB(WRITE8(galaga_state,out_1)) + + MCFG_NAMCO_53XX_ADD("53xx", MASTER_CLOCK/6/2) /* 1.536 MHz */ + MCFG_NAMCO_53XX_K_CB(READ8(galaga_state,custom_mod_r)) + MCFG_NAMCO_53XX_INPUT_0_CB(IOPORT("DSWA")) + MCFG_NAMCO_53XX_INPUT_1_CB(IOPORT("DSWA_HI")) + MCFG_NAMCO_53XX_INPUT_2_CB(IOPORT("DSWB")) + MCFG_NAMCO_53XX_INPUT_3_CB(IOPORT("DSWB_HI")) - MCFG_NAMCO_06XX_ADD("06xx", MASTER_CLOCK/6/64, digdug_namco_06xx_intf) + MCFG_NAMCO_06XX_ADD("06xx", MASTER_CLOCK/6/64) + MCFG_NAMCO_06XX_MAINCPU("maincpu") + MCFG_NAMCO_06XX_READ_0_CB(DEVREAD8("51xx", namco_51xx_device, read)) + MCFG_NAMCO_06XX_WRITE_0_CB(DEVWRITE8("51xx", namco_51xx_device, write)) + MCFG_NAMCO_06XX_READ_1_CB(DEVREAD8("53xx", namco_53xx_device, read)) + MCFG_NAMCO_06XX_READ_REQUEST_1_CB(DEVWRITELINE("53xx", namco_53xx_device, read_request)) MCFG_QUANTUM_TIME(attotime::from_hz(6000)) /* 100 CPU slices per frame - an high value to ensure proper */ /* synchronization of the CPUs */ diff --git a/src/mame/drivers/gaplus.c b/src/mame/drivers/gaplus.c index a5e75ce1ff6..20637242e45 100644 --- a/src/mame/drivers/gaplus.c +++ b/src/mame/drivers/gaplus.c @@ -208,21 +208,6 @@ WRITE8_MEMBER(gaplus_state::gaplus_freset_w) m_namco56xx->set_reset_line(bit ? CLEAR_LINE : ASSERT_LINE); } -static const namco_62xx_interface namco_62xx_intf = -{ - { /* port read handlers */ - DEVCB_NULL, //DEVCB_INPUT_PORT("IN0L"), - DEVCB_NULL, //DEVCB_INPUT_PORT("IN0H"), - DEVCB_NULL, //DEVCB_INPUT_PORT("IN1L"), - DEVCB_NULL //DEVCB_INPUT_PORT("IN1H") - }, - { /* port write handlers */ - DEVCB_NULL, //DEVCB_DRIVER_MEMBER(out_0), - DEVCB_NULL //DEVCB_DRIVER_MEMBER(out_1) - } -}; - - void gaplus_state::machine_reset() { /* on reset, VINTON is reset, while the other flags don't seem to be affected */ @@ -584,8 +569,14 @@ static MACHINE_CONFIG_START( gaplus, gaplus_state ) MCFG_NAMCO56XX_ADD("namcoio_1", intf0_lamps) MCFG_NAMCO58XX_ADD("namcoio_2", intf1) - MCFG_NAMCO_62XX_ADD("62xx", 24576000/6/2, namco_62xx_intf) /* totally made up - TODO: fix */ - + MCFG_NAMCO_62XX_ADD("62xx", 24576000/6/2) /* totally made up - TODO: fix */ + //MCFG_NAMCO_62XX_INPUT_0_CB(IOPORT("IN0L")) + //MCFG_NAMCO_62XX_INPUT_1_CB(IOPORT("IN0H")) + //MCFG_NAMCO_62XX_INPUT_2_CB(IOPORT("IN1L")) + //MCFG_NAMCO_62XX_INPUT_3_CB(IOPORT("IN1H")) + //MCFG_NAMCO_62XX_OUTPUT_0_CB(WRITE8(gaplus_state,out_0)) + //MCFG_NAMCO_62XX_OUTPUT_1_CB(WRITE8(gaplus_state,out_1)) + /* video hardware */ MCFG_SCREEN_ADD("screen", RASTER) MCFG_SCREEN_REFRESH_RATE(60.606060) diff --git a/src/mame/drivers/polepos.c b/src/mame/drivers/polepos.c index f6f0879b019..054f76d98b6 100644 --- a/src/mame/drivers/polepos.c +++ b/src/mame/drivers/polepos.c @@ -360,21 +360,6 @@ WRITE8_MEMBER(polepos_state::out_1) coin_lockout_global_w(machine(), data & 1); } -static const namco_51xx_interface namco_51xx_intf = -{ - { /* port read handlers */ - DEVCB_INPUT_PORT("IN0L"), - DEVCB_INPUT_PORT("IN0H"), - DEVCB_INPUT_PORT("DSWB"), - DEVCB_INPUT_PORT("DSWB_HI") - }, - { /* port write handlers */ - DEVCB_DRIVER_MEMBER(polepos_state,out_0), - DEVCB_DRIVER_MEMBER(polepos_state,out_1) - } -}; - - READ8_MEMBER(polepos_state::namco_52xx_rom_r) { UINT32 length = memregion("52xx")->bytes(); @@ -388,16 +373,6 @@ READ8_MEMBER(polepos_state::namco_52xx_si_r) return 1; } -static const namco_52xx_interface namco_52xx_intf = -{ - "discrete", /* name of the discrete sound device */ - NODE_04, /* index of the first node */ - 0, /* external clock rate */ - DEVCB_DRIVER_MEMBER(polepos_state,namco_52xx_rom_r), /* ROM read handler */ - DEVCB_DRIVER_MEMBER(polepos_state,namco_52xx_si_r) /* SI (pin 6) read handler */ -}; - - READ8_MEMBER(polepos_state::namco_53xx_k_r) { /* hardwired to 0 */ @@ -431,19 +406,6 @@ READ8_MEMBER(polepos_state::steering_delta_r) return m_steer_delta; } -static const namco_53xx_interface namco_53xx_intf = -{ - DEVCB_DRIVER_MEMBER(polepos_state,namco_53xx_k_r), /* K port */ - { - DEVCB_DRIVER_MEMBER(polepos_state,steering_changed_r), /* R0 port */ - DEVCB_DRIVER_MEMBER(polepos_state,steering_delta_r), /* R1 port */ - DEVCB_INPUT_PORT("DSWA"), /* R2 port */ - DEVCB_INPUT_PORT("DSWA_HI") /* R3 port */ - }, - DEVCB_NULL /* P port (connected to test socket) */ -}; - - TIMER_DEVICE_CALLBACK_MEMBER(polepos_state::polepos_scanline) { int scanline = param; @@ -490,8 +452,8 @@ static ADDRESS_MAP_START( z80_map, AS_PROGRAM, 8, polepos_state ) AM_RANGE(0x8000, 0x83bf) AM_MIRROR(0x0c00) AM_RAM /* Sound Memory */ AM_RANGE(0x83c0, 0x83ff) AM_MIRROR(0x0c00) AM_DEVREADWRITE("namco", namco_device, polepos_sound_r, polepos_sound_w) /* Sound data */ - AM_RANGE(0x9000, 0x9000) AM_MIRROR(0x0eff) AM_DEVREADWRITE_LEGACY("06xx", namco_06xx_data_r, namco_06xx_data_w) - AM_RANGE(0x9100, 0x9100) AM_MIRROR(0x0eff) AM_DEVREADWRITE_LEGACY("06xx", namco_06xx_ctrl_r, namco_06xx_ctrl_w) + AM_RANGE(0x9000, 0x9000) AM_MIRROR(0x0eff) AM_DEVREADWRITE("06xx", namco_06xx_device, data_r, data_w) + AM_RANGE(0x9100, 0x9100) AM_MIRROR(0x0eff) AM_DEVREADWRITE("06xx", namco_06xx_device, ctrl_r, ctrl_w) AM_RANGE(0xa000, 0xa000) AM_MIRROR(0x0cff) AM_READ(polepos_ready_r) /* READY */ AM_RANGE(0xa000, 0xa007) AM_MIRROR(0x0cf8) AM_WRITE(polepos_latch_w) /* misc latches */ AM_RANGE(0xa100, 0xa100) AM_MIRROR(0x0cff) AM_WRITE(watchdog_reset_w) /* Watchdog */ @@ -870,15 +832,6 @@ static const namco_interface namco_config = 1 /* stereo */ }; -const namco_06xx_config polepos_namco_06xx_intf = -{ - "maincpu", "51xx", "53xx", "52xx", "54xx" -}; - -const namco_54xx_config polepos_namco_54xx_intf = -{ - "discrete", NODE_01 -}; /********************************************************************* * Machine driver @@ -897,12 +850,39 @@ static MACHINE_CONFIG_START( polepos, polepos_state ) MCFG_CPU_ADD("sub2", Z8002, MASTER_CLOCK/8) /* 3.072 MHz */ MCFG_CPU_PROGRAM_MAP(z8002_map) - MCFG_NAMCO_51XX_ADD("51xx", MASTER_CLOCK/8/2, namco_51xx_intf) /* 1.536 MHz */ - MCFG_NAMCO_52XX_ADD("52xx", MASTER_CLOCK/8/2, namco_52xx_intf) /* 1.536 MHz */ - MCFG_NAMCO_53XX_ADD("53xx", MASTER_CLOCK/8/2, namco_53xx_intf) /* 1.536 MHz */ - MCFG_NAMCO_54XX_ADD("54xx", MASTER_CLOCK/8/2, polepos_namco_54xx_intf) /* 1.536 MHz */ + MCFG_NAMCO_51XX_ADD("51xx", MASTER_CLOCK/8/2) /* 1.536 MHz */ + MCFG_NAMCO_51XX_INPUT_0_CB(IOPORT("IN0L")) + MCFG_NAMCO_51XX_INPUT_1_CB(IOPORT("IN0H")) + MCFG_NAMCO_51XX_INPUT_2_CB(IOPORT("DSWB")) + MCFG_NAMCO_51XX_INPUT_3_CB(IOPORT("DSWB_HI")) + MCFG_NAMCO_51XX_OUTPUT_0_CB(WRITE8(polepos_state,out_0)) + MCFG_NAMCO_51XX_OUTPUT_1_CB(WRITE8(polepos_state,out_1)) - MCFG_NAMCO_06XX_ADD("06xx", MASTER_CLOCK/8/64, polepos_namco_06xx_intf) + MCFG_NAMCO_52XX_ADD("52xx", MASTER_CLOCK/8/2) /* 1.536 MHz */ + MCFG_NAMCO_52XX_DICRETE("discrete") + MCFG_NAMCO_52XX_BASENODE(NODE_04) + MCFG_NAMCO_52XX_ROMREAD_CB(READ8(polepos_state,namco_52xx_rom_r)) + MCFG_NAMCO_52XX_SI_CB(READ8(polepos_state,namco_52xx_si_r)) + + MCFG_NAMCO_53XX_ADD("53xx", MASTER_CLOCK/8/2) /* 1.536 MHz */ + MCFG_NAMCO_53XX_K_CB(READ8(polepos_state,namco_53xx_k_r)) + MCFG_NAMCO_53XX_INPUT_0_CB(READ8(polepos_state,steering_changed_r)) + MCFG_NAMCO_53XX_INPUT_1_CB(READ8(polepos_state,steering_delta_r)) + MCFG_NAMCO_53XX_INPUT_2_CB(IOPORT("DSWA")) + MCFG_NAMCO_53XX_INPUT_3_CB(IOPORT("DSWA_HI")) + + MCFG_NAMCO_54XX_ADD("54xx", MASTER_CLOCK/8/2) /* 1.536 MHz */ + MCFG_NAMCO_54XX_DICRETE("discrete") + MCFG_NAMCO_54XX_BASENODE(NODE_01) + + MCFG_NAMCO_06XX_ADD("06xx", MASTER_CLOCK/8/64) + MCFG_NAMCO_06XX_MAINCPU("maincpu") + MCFG_NAMCO_06XX_READ_0_CB(DEVREAD8("51xx", namco_51xx_device, read)) + MCFG_NAMCO_06XX_WRITE_0_CB(DEVWRITE8("51xx", namco_51xx_device, write)) + MCFG_NAMCO_06XX_READ_1_CB(DEVREAD8("53xx", namco_53xx_device, read)) + MCFG_NAMCO_06XX_READ_REQUEST_1_CB(DEVWRITELINE("53xx", namco_53xx_device, read_request)) + MCFG_NAMCO_06XX_WRITE_2_CB(DEVWRITE8("52xx", namco_52xx_device, write)) + MCFG_NAMCO_06XX_WRITE_3_CB(DEVWRITE8("54xx", namco_54xx_device, write)) MCFG_WATCHDOG_VBLANK_INIT(16) // 128V clocks the same as VBLANK @@ -947,26 +927,6 @@ static MACHINE_CONFIG_START( polepos, polepos_state ) MCFG_SOUND_ROUTE(ALL_OUTPUTS, "rspeaker", 0.90 * 0.77) MACHINE_CONFIG_END -/* doesn't exist on the bootleg, but required for now or the game only boots in test mode! - - they probably simulate some of the logic */ -static const namco_51xx_interface namco_51xx_bl_intf = -{ - { /* port read handlers */ - DEVCB_NULL, - DEVCB_INPUT_PORT("IN0H"), - DEVCB_NULL, - DEVCB_NULL - }, - { /* port write handlers */ - DEVCB_NULL, - DEVCB_NULL - } -}; - -const namco_06xx_config topracern_namco_06xx_intf = -{ - "maincpu", "51xx", NULL, NULL, NULL -}; static MACHINE_CONFIG_START( topracern, polepos_state ) @@ -982,8 +942,15 @@ static MACHINE_CONFIG_START( topracern, polepos_state ) MCFG_CPU_PROGRAM_MAP(z8002_map) /* todo, remove these devices too, this bootleg doesn't have them, but the emulation doesn't boot without them.. */ - MCFG_NAMCO_51XX_ADD("51xx", MASTER_CLOCK/8/2, namco_51xx_bl_intf) /* 1.536 MHz */ - MCFG_NAMCO_06XX_ADD("06xx", MASTER_CLOCK/8/64, topracern_namco_06xx_intf) + /* doesn't exist on the bootleg, but required for now or the game only boots in test mode! + they probably simulate some of the logic */ + MCFG_NAMCO_51XX_ADD("51xx", MASTER_CLOCK/8/2) /* 1.536 MHz */ + MCFG_NAMCO_51XX_INPUT_1_CB(IOPORT("IN0H")) + + MCFG_NAMCO_06XX_ADD("06xx", MASTER_CLOCK/8/64) + MCFG_NAMCO_06XX_MAINCPU("maincpu") + MCFG_NAMCO_06XX_READ_0_CB(DEVREAD8("51xx", namco_51xx_device, read)) + MCFG_NAMCO_06XX_WRITE_0_CB(DEVWRITE8("51xx", namco_51xx_device, write)) MCFG_WATCHDOG_VBLANK_INIT(16) // 128V clocks the same as VBLANK diff --git a/src/mame/machine/namco06.c b/src/mame/machine/namco06.c index 8ec1f857af3..fa09d7cb188 100644 --- a/src/mame/machine/namco06.c +++ b/src/mame/machine/namco06.c @@ -83,116 +83,76 @@ #include "emu.h" #include "machine/namco06.h" -#include "machine/namco50.h" -#include "machine/namco51.h" -#include "machine/namco53.h" -#include "audio/namco52.h" -#include "audio/namco54.h" -#include "devlegcy.h" - #define VERBOSE 0 #define LOG(x) do { if (VERBOSE) logerror x; } while (0) - -struct namco_06xx_state +TIMER_CALLBACK_MEMBER( namco_06xx_device::nmi_generate ) { - UINT8 m_control; - emu_timer *m_nmi_timer; - cpu_device *m_nmicpu; - device_t *m_device[4]; - read8_device_func m_read[4]; - void (*m_readreq[4])(device_t *device); - write8_device_func m_write[4]; -}; - -INLINE namco_06xx_state *get_safe_token(device_t *device) -{ - assert(device != NULL); - assert(device->type() == NAMCO_06XX); - - return (namco_06xx_state *)downcast(device)->token(); -} - - - -static TIMER_CALLBACK( nmi_generate ) -{ - namco_06xx_state *state = get_safe_token((device_t *)ptr); - - if (!state->m_nmicpu->suspended(SUSPEND_REASON_HALT | SUSPEND_REASON_RESET | SUSPEND_REASON_DISABLE)) + if (!m_nmicpu->suspended(SUSPEND_REASON_HALT | SUSPEND_REASON_RESET | SUSPEND_REASON_DISABLE)) { - LOG(("NMI cpu '%s'\n",state->m_nmicpu->tag())); - - state->m_nmicpu->set_input_line(INPUT_LINE_NMI, PULSE_LINE); + LOG(("NMI cpu '%s'\n",m_nmicpu->tag())); + m_nmicpu->set_input_line(INPUT_LINE_NMI, PULSE_LINE); } else - LOG(("NMI not generated because cpu '%s' is suspended\n",state->m_nmicpu->tag())); + LOG(("NMI not generated because cpu '%s' is suspended\n",m_nmicpu->tag())); } -READ8_DEVICE_HANDLER( namco_06xx_data_r ) -{ - namco_06xx_state *state = get_safe_token(device); +READ8_MEMBER( namco_06xx_device::data_r ) +{ UINT8 result = 0xff; - int devnum; - LOG(("%s: 06XX '%s' read offset %d\n",space.machine().describe_context(),device->tag(),offset)); + LOG(("%s: 06XX '%s' read offset %d\n",machine().describe_context(),tag(),offset)); - if (!(state->m_control & 0x10)) + if (!(m_control & 0x10)) { - logerror("%s: 06XX '%s' read in write mode %02x\n",space.machine().describe_context(),device->tag(),state->m_control); + logerror("%s: 06XX '%s' read in write mode %02x\n",machine().describe_context(),tag(),m_control); return 0; } - for (devnum = 0; devnum < 4; devnum++) - if ((state->m_control & (1 << devnum)) && state->m_read[devnum] != NULL) - result &= (*state->m_read[devnum])(state->m_device[devnum], space, 0, 0xff); + if ((m_control & (1 << 0)) && !m_read_0.isnull()) result &= m_read_0(space, 0); + if ((m_control & (1 << 1)) && !m_read_1.isnull()) result &= m_read_1(space, 0); + if ((m_control & (1 << 2)) && !m_read_2.isnull()) result &= m_read_2(space, 0); + if ((m_control & (1 << 3)) && !m_read_3.isnull()) result &= m_read_3(space, 0); return result; } -WRITE8_DEVICE_HANDLER( namco_06xx_data_w ) -{ - namco_06xx_state *state = get_safe_token(device); - int devnum; +WRITE8_MEMBER( namco_06xx_device::data_w ) +{ + LOG(("%s: 06XX '%s' write offset %d = %02x\n",machine().describe_context(),tag(),offset,data)); - LOG(("%s: 06XX '%s' write offset %d = %02x\n",space.machine().describe_context(),device->tag(),offset,data)); - - if (state->m_control & 0x10) + if (m_control & 0x10) { - logerror("%s: 06XX '%s' write in read mode %02x\n",space.machine().describe_context(),device->tag(),state->m_control); + logerror("%s: 06XX '%s' write in read mode %02x\n",machine().describe_context(),tag(),m_control); return; } - - for (devnum = 0; devnum < 4; devnum++) - if ((state->m_control & (1 << devnum)) && state->m_write[devnum] != NULL) - (*state->m_write[devnum])(state->m_device[devnum], space, 0, data, 0xff); + if ((m_control & (1 << 0)) && !m_write_0.isnull()) m_write_0(space, 0, data); + if ((m_control & (1 << 1)) && !m_write_1.isnull()) m_write_1(space, 0, data); + if ((m_control & (1 << 2)) && !m_write_2.isnull()) m_write_2(space, 0, data); + if ((m_control & (1 << 3)) && !m_write_3.isnull()) m_write_3(space, 0, data); } -READ8_DEVICE_HANDLER( namco_06xx_ctrl_r ) -{ - namco_06xx_state *state = get_safe_token(device); - LOG(("%s: 06XX '%s' ctrl_r\n",space.machine().describe_context(),device->tag())); - return state->m_control; +READ8_MEMBER( namco_06xx_device::ctrl_r ) +{ + LOG(("%s: 06XX '%s' ctrl_r\n",machine().describe_context(),tag())); + return m_control; } -WRITE8_DEVICE_HANDLER( namco_06xx_ctrl_w ) -{ - namco_06xx_state *state = get_safe_token(device); - int devnum; +WRITE8_MEMBER( namco_06xx_device::ctrl_w ) +{ + LOG(("%s: 06XX '%s' control %02x\n",space.machine().describe_context(),tag(),data)); - LOG(("%s: 06XX '%s' control %02x\n",space.machine().describe_context(),device->tag(),data)); + m_control = data; - state->m_control = data; - - if ((state->m_control & 0x0f) == 0) + if ((m_control & 0x0f) == 0) { LOG(("disabling nmi generate timer\n")); - state->m_nmi_timer->adjust(attotime::never); + m_nmi_timer->adjust(attotime::never); } else { @@ -202,105 +162,37 @@ WRITE8_DEVICE_HANDLER( namco_06xx_ctrl_w ) // inputs if a transfer terminates at the wrong time. // On the other hand, the time cannot be too short otherwise the 54XX will // not have enough time to process the incoming controls. - state->m_nmi_timer->adjust(attotime::from_usec(200), 0, attotime::from_usec(200)); + m_nmi_timer->adjust(attotime::from_usec(200), 0, attotime::from_usec(200)); - if (state->m_control & 0x10) - for (devnum = 0; devnum < 4; devnum++) - if ((state->m_control & (1 << devnum)) && state->m_readreq[devnum] != NULL) - (*state->m_readreq[devnum])(state->m_device[devnum]); - } -} - - -/*************************************************************************** - DEVICE INTERFACE -***************************************************************************/ - -/*------------------------------------------------- - device start callback --------------------------------------------------*/ - -static DEVICE_START( namco_06xx ) -{ - const namco_06xx_config *config = (const namco_06xx_config *)device->static_config(); - namco_06xx_state *state = get_safe_token(device); - int devnum; - - assert(config != NULL); - - /* resolve our CPU */ - state->m_nmicpu = device->machine().device(config->nmicpu); - assert(state->m_nmicpu != NULL); - - /* resolve our devices */ - state->m_device[0] = (config->chip0 != NULL) ? device->machine().device(config->chip0) : NULL; - assert(state->m_device[0] != NULL || config->chip0 == NULL); - state->m_device[1] = (config->chip1 != NULL) ? device->machine().device(config->chip1) : NULL; - assert(state->m_device[1] != NULL || config->chip1 == NULL); - state->m_device[2] = (config->chip2 != NULL) ? device->machine().device(config->chip2) : NULL; - assert(state->m_device[2] != NULL || config->chip2 == NULL); - state->m_device[3] = (config->chip3 != NULL) ? device->machine().device(config->chip3) : NULL; - assert(state->m_device[3] != NULL || config->chip3 == NULL); - - /* loop over devices and set their read/write handlers */ - for (devnum = 0; devnum < 4; devnum++) - if (state->m_device[devnum] != NULL) - { - device_type type = state->m_device[devnum]->type(); - - if (type == NAMCO_50XX) - { - state->m_read[devnum] = namco_50xx_read; - state->m_readreq[devnum] = namco_50xx_read_request; - state->m_write[devnum] = namco_50xx_write; - } - else if (type == NAMCO_51XX) - { - state->m_read[devnum] = namco_51xx_read; - state->m_write[devnum] = namco_51xx_write; - } - else if (type == NAMCO_52XX) - state->m_write[devnum] = namco_52xx_write; - else if (type == NAMCO_53XX) - { - state->m_read[devnum] = namco_53xx_read; - state->m_readreq[devnum] = namco_53xx_read_request; - } - else if (type == NAMCO_54XX) - state->m_write[devnum] = namco_54xx_write; - else - fatalerror("Unknown device type %s connected to Namco 06xx\n", state->m_device[devnum]->name()); + if (m_control & 0x10) { + if ((m_control & (1 << 0)) && !m_readreq_0.isnull()) m_readreq_0(space, 0); + if ((m_control & (1 << 1)) && !m_readreq_1.isnull()) m_readreq_1(space, 0); + if ((m_control & (1 << 2)) && !m_readreq_2.isnull()) m_readreq_2(space, 0); + if ((m_control & (1 << 3)) && !m_readreq_3.isnull()) m_readreq_3(space, 0); } - - /* allocate a timer */ - state->m_nmi_timer = device->machine().scheduler().timer_alloc(FUNC(nmi_generate), (void *)device); - - device->save_item(NAME(state->m_control)); -} - - -/*------------------------------------------------- - device reset callback --------------------------------------------------*/ - -static DEVICE_RESET( namco_06xx ) -{ - namco_06xx_state *state = get_safe_token(device); - state->m_control = 0; + } } const device_type NAMCO_06XX = &device_creator; namco_06xx_device::namco_06xx_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) - : device_t(mconfig, NAMCO_06XX, "Namco 06xx", tag, owner, clock, "namco06xx", __FILE__) + : device_t(mconfig, NAMCO_06XX, "Namco 06xx", tag, owner, clock, "namco06xx", __FILE__), + m_control(0), + m_nmicpu(*this), + m_read_0(*this), + m_read_1(*this), + m_read_2(*this), + m_read_3(*this), + m_readreq_0(*this), + m_readreq_1(*this), + m_readreq_2(*this), + m_readreq_3(*this), + m_write_0(*this), + m_write_1(*this), + m_write_2(*this), + m_write_3(*this) { - m_token = global_alloc_clear(namco_06xx_state); -} - -namco_06xx_device::~namco_06xx_device() -{ - global_free(m_token); } //------------------------------------------------- @@ -309,7 +201,22 @@ namco_06xx_device::~namco_06xx_device() void namco_06xx_device::device_start() { - DEVICE_START_NAME( namco_06xx )(this); + m_read_0.resolve(); + m_read_1.resolve(); + m_read_2.resolve(); + m_read_3.resolve(); + m_readreq_0.resolve(); + m_readreq_1.resolve(); + m_readreq_2.resolve(); + m_readreq_3.resolve(); + m_write_0.resolve(); + m_write_1.resolve(); + m_write_2.resolve(); + m_write_3.resolve(); + /* allocate a timer */ + m_nmi_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(namco_06xx_device::nmi_generate),this)); + + save_item(NAME(m_control)); } //------------------------------------------------- @@ -318,5 +225,5 @@ void namco_06xx_device::device_start() void namco_06xx_device::device_reset() { - DEVICE_RESET_NAME( namco_06xx )(this); + m_control = 0; } diff --git a/src/mame/machine/namco06.h b/src/mame/machine/namco06.h index 32f547fbda7..94be8bfac2c 100644 --- a/src/mame/machine/namco06.h +++ b/src/mame/machine/namco06.h @@ -4,7 +4,6 @@ #define NAMCO06_H - struct namco_06xx_config { const char *nmicpu; @@ -15,33 +14,108 @@ struct namco_06xx_config }; -#define MCFG_NAMCO_06XX_ADD(_tag, _clock, _config) \ - MCFG_DEVICE_ADD(_tag, NAMCO_06XX, _clock) \ - MCFG_DEVICE_CONFIG(_config) +#define MCFG_NAMCO_06XX_ADD(_tag, _clock) \ + MCFG_DEVICE_ADD(_tag, NAMCO_06XX, _clock) + +#define MCFG_NAMCO_06XX_MAINCPU(_tag) \ + namco_06xx_device::set_maincpu(*device, "^" _tag); + +#define MCFG_NAMCO_06XX_READ_0_CB(_devcb) \ + devcb = &namco_06xx_device::set_read_0_callback(*device, DEVCB2_##_devcb); + +#define MCFG_NAMCO_06XX_READ_1_CB(_devcb) \ + devcb = &namco_06xx_device::set_read_1_callback(*device, DEVCB2_##_devcb); + +#define MCFG_NAMCO_06XX_READ_2_CB(_devcb) \ + devcb = &namco_06xx_device::set_read_2_callback(*device, DEVCB2_##_devcb); + +#define MCFG_NAMCO_06XX_READ_3_CB(_devcb) \ + devcb = &namco_06xx_device::set_read_3_callback(*device, DEVCB2_##_devcb); -DECLARE_READ8_DEVICE_HANDLER( namco_06xx_data_r ); -DECLARE_WRITE8_DEVICE_HANDLER( namco_06xx_data_w ); -DECLARE_READ8_DEVICE_HANDLER( namco_06xx_ctrl_r ); -DECLARE_WRITE8_DEVICE_HANDLER( namco_06xx_ctrl_w ); +#define MCFG_NAMCO_06XX_READ_REQUEST_0_CB(_devcb) \ + devcb = &namco_06xx_device::set_read_request_0_callback(*device, DEVCB2_##_devcb); +#define MCFG_NAMCO_06XX_READ_REQUEST_1_CB(_devcb) \ + devcb = &namco_06xx_device::set_read_request_1_callback(*device, DEVCB2_##_devcb); + +#define MCFG_NAMCO_06XX_READ_REQUEST_2_CB(_devcb) \ + devcb = &namco_06xx_device::set_read_request_2_callback(*device, DEVCB2_##_devcb); + +#define MCFG_NAMCO_06XX_READ_REQUEST_3_CB(_devcb) \ + devcb = &namco_06xx_device::set_read_request_3_callback(*device, DEVCB2_##_devcb); + + +#define MCFG_NAMCO_06XX_WRITE_0_CB(_devcb) \ + devcb = &namco_06xx_device::set_write_0_callback(*device, DEVCB2_##_devcb); + +#define MCFG_NAMCO_06XX_WRITE_1_CB(_devcb) \ + devcb = &namco_06xx_device::set_write_1_callback(*device, DEVCB2_##_devcb); + +#define MCFG_NAMCO_06XX_WRITE_2_CB(_devcb) \ + devcb = &namco_06xx_device::set_write_2_callback(*device, DEVCB2_##_devcb); + +#define MCFG_NAMCO_06XX_WRITE_3_CB(_devcb) \ + devcb = &namco_06xx_device::set_write_3_callback(*device, DEVCB2_##_devcb); + /* device get info callback */ class namco_06xx_device : public device_t { public: namco_06xx_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); - ~namco_06xx_device(); - // access to legacy token - struct namco_06xx_state *token() const { assert(m_token != NULL); return m_token; } + static void set_maincpu(device_t &device, const char *tag) { downcast(device).m_nmicpu.set_tag(tag); } + + template static devcb2_base &set_read_0_callback(device_t &device, _Object object) { return downcast(device).m_read_0.set_callback(object); } + template static devcb2_base &set_read_1_callback(device_t &device, _Object object) { return downcast(device).m_read_1.set_callback(object); } + template static devcb2_base &set_read_2_callback(device_t &device, _Object object) { return downcast(device).m_read_2.set_callback(object); } + template static devcb2_base &set_read_3_callback(device_t &device, _Object object) { return downcast(device).m_read_3.set_callback(object); } + + template static devcb2_base &set_read_request_0_callback(device_t &device, _Object object) { return downcast(device).m_readreq_0.set_callback(object); } + template static devcb2_base &set_read_request_1_callback(device_t &device, _Object object) { return downcast(device).m_readreq_1.set_callback(object); } + template static devcb2_base &set_read_request_2_callback(device_t &device, _Object object) { return downcast(device).m_readreq_2.set_callback(object); } + template static devcb2_base &set_read_request_3_callback(device_t &device, _Object object) { return downcast(device).m_readreq_3.set_callback(object); } + + + template static devcb2_base &set_write_0_callback(device_t &device, _Object object) { return downcast(device).m_write_0.set_callback(object); } + template static devcb2_base &set_write_1_callback(device_t &device, _Object object) { return downcast(device).m_write_1.set_callback(object); } + template static devcb2_base &set_write_2_callback(device_t &device, _Object object) { return downcast(device).m_write_2.set_callback(object); } + template static devcb2_base &set_write_3_callback(device_t &device, _Object object) { return downcast(device).m_write_3.set_callback(object); } + + DECLARE_READ8_MEMBER( data_r ); + DECLARE_WRITE8_MEMBER( data_w ); + DECLARE_READ8_MEMBER( ctrl_r ); + DECLARE_WRITE8_MEMBER( ctrl_w ); + protected: // device-level overrides virtual void device_start(); virtual void device_reset(); private: - // internal state - struct namco_06xx_state *m_token; + + TIMER_CALLBACK_MEMBER( nmi_generate ); + + // internal state + UINT8 m_control; + emu_timer *m_nmi_timer; + + required_device m_nmicpu; + + devcb2_read8 m_read_0; + devcb2_read8 m_read_1; + devcb2_read8 m_read_2; + devcb2_read8 m_read_3; + + devcb2_write_line m_readreq_0; + devcb2_write_line m_readreq_1; + devcb2_write_line m_readreq_2; + devcb2_write_line m_readreq_3; + + devcb2_write8 m_write_0; + devcb2_write8 m_write_1; + devcb2_write8 m_write_2; + devcb2_write8 m_write_3; }; extern const device_type NAMCO_06XX; diff --git a/src/mame/machine/namco50.c b/src/mame/machine/namco50.c index 6d71800eccd..ce1de7be109 100644 --- a/src/mame/machine/namco50.c +++ b/src/mame/machine/namco50.c @@ -134,118 +134,80 @@ Flags: 80=high score, 40=first bonus, 20=interval bonus, 10=? #include "emu.h" #include "namco50.h" -#include "cpu/mb88xx/mb88xx.h" -#include "devlegcy.h" - -struct namco_50xx_state +TIMER_CALLBACK_MEMBER( namco_50xx_device::latch_callback ) { - device_t * m_cpu; - UINT8 m_latched_cmd; - UINT8 m_latched_rw; - UINT8 m_portO; -}; - -INLINE namco_50xx_state *get_safe_token(device_t *device) -{ - assert(device != NULL); - assert(device->type() == NAMCO_50XX); - - return (namco_50xx_state *)downcast(device)->token(); + m_latched_cmd = param; + m_latched_rw = 0; } - - -static TIMER_CALLBACK( namco_50xx_latch_callback ) +TIMER_CALLBACK_MEMBER( namco_50xx_device::readrequest_callback ) { - namco_50xx_state *state = get_safe_token((device_t *)ptr); - state->m_latched_cmd = param; - state->m_latched_rw = 0; + m_latched_rw = 1; } - -static TIMER_CALLBACK( namco_50xx_readrequest_callback ) +READ8_MEMBER( namco_50xx_device::K_r ) { - namco_50xx_state *state = get_safe_token((device_t *)ptr); - state->m_latched_rw = 1; + return m_latched_cmd >> 4; } - -static READ8_HANDLER( namco_50xx_K_r ) +READ8_MEMBER( namco_50xx_device::R0_r ) { - namco_50xx_state *state = get_safe_token(space.device().owner()); - return state->m_latched_cmd >> 4; + return m_latched_cmd & 0x0f; } -static READ8_HANDLER( namco_50xx_R0_r ) +READ8_MEMBER( namco_50xx_device::R2_r ) { - namco_50xx_state *state = get_safe_token(space.device().owner()); - return state->m_latched_cmd & 0x0f; + return m_latched_rw & 1; } -static READ8_HANDLER( namco_50xx_R2_r ) +WRITE8_MEMBER( namco_50xx_device::O_w ) { - namco_50xx_state *state = get_safe_token(space.device().owner()); - return state->m_latched_rw & 1; -} - - - -static WRITE8_HANDLER( namco_50xx_O_w ) -{ - namco_50xx_state *state = get_safe_token(space.device().owner()); UINT8 out = (data & 0x0f); if (data & 0x10) - state->m_portO = (state->m_portO & 0x0f) | (out << 4); + m_portO = (m_portO & 0x0f) | (out << 4); else - state->m_portO = (state->m_portO & 0xf0) | (out); + m_portO = (m_portO & 0xf0) | (out); } - - - -static TIMER_CALLBACK( namco_50xx_irq_clear ) +TIMER_CALLBACK_MEMBER( namco_50xx_device::irq_clear ) { - namco_50xx_state *state = get_safe_token((device_t *)ptr); - state->m_cpu->execute().set_input_line(0, CLEAR_LINE); + m_cpu->set_input_line(0, CLEAR_LINE); } -static void namco_50xx_irq_set(device_t *device) -{ - namco_50xx_state *state = get_safe_token(device); - - state->m_cpu->execute().set_input_line(0, ASSERT_LINE); +void namco_50xx_device::irq_set() +{ + m_cpu->set_input_line(0, ASSERT_LINE); // The execution time of one instruction is ~4us, so we must make sure to // give the cpu time to poll the /IRQ input before we clear it. // The input clock to the 06XX interface chip is 64H, that is // 18432000/6/64 = 48kHz, so it makes sense for the irq line to be // asserted for one clock cycle ~= 21us. - device->machine().scheduler().timer_set(attotime::from_usec(21), FUNC(namco_50xx_irq_clear), 0, (void *)device); + machine().scheduler().timer_set(attotime::from_usec(21), timer_expired_delegate(FUNC(namco_50xx_device::irq_clear),this), 0); } -WRITE8_DEVICE_HANDLER( namco_50xx_write ) +WRITE8_MEMBER( namco_50xx_device::write ) { - space.machine().scheduler().synchronize(FUNC(namco_50xx_latch_callback), data, (void *)device); + machine().scheduler().synchronize(timer_expired_delegate(FUNC(namco_50xx_device::latch_callback),this), data); - namco_50xx_irq_set(device); + irq_set(); } -void namco_50xx_read_request(device_t *device) +WRITE_LINE_MEMBER(namco_50xx_device::read_request) { - device->machine().scheduler().synchronize(FUNC(namco_50xx_readrequest_callback), 0, (void *)device); + machine().scheduler().synchronize(timer_expired_delegate(FUNC(namco_50xx_device::readrequest_callback),this), 0); - namco_50xx_irq_set(device); + irq_set(); } -READ8_DEVICE_HANDLER( namco_50xx_read ) +READ8_MEMBER( namco_50xx_device::read ) { - namco_50xx_state *state = get_safe_token(device); - UINT8 res = state->m_portO; + UINT8 res = m_portO; - namco_50xx_read_request(device); + read_request(0); return res; } @@ -256,10 +218,10 @@ READ8_DEVICE_HANDLER( namco_50xx_read ) ***************************************************************************/ static ADDRESS_MAP_START( namco_50xx_map_io, AS_IO, 8, namco_50xx_device ) - AM_RANGE(MB88_PORTK, MB88_PORTK) AM_READ_LEGACY(namco_50xx_K_r) - AM_RANGE(MB88_PORTO, MB88_PORTO) AM_WRITE_LEGACY(namco_50xx_O_w) - AM_RANGE(MB88_PORTR0, MB88_PORTR0) AM_READ_LEGACY(namco_50xx_R0_r) - AM_RANGE(MB88_PORTR2, MB88_PORTR2) AM_READ_LEGACY(namco_50xx_R2_r) + AM_RANGE(MB88_PORTK, MB88_PORTK) AM_READ(K_r) + AM_RANGE(MB88_PORTO, MB88_PORTO) AM_WRITE(O_w) + AM_RANGE(MB88_PORTR0, MB88_PORTR0) AM_READ(R0_r) + AM_RANGE(MB88_PORTR2, MB88_PORTR2) AM_READ(R2_r) ADDRESS_MAP_END @@ -275,37 +237,17 @@ ROM_START( namco_50xx ) ROM_END -/*------------------------------------------------- - device start callback --------------------------------------------------*/ - -static DEVICE_START( namco_50xx ) -{ - namco_50xx_state *state = get_safe_token(device); - astring tempstring; - - /* find our CPU */ - state->m_cpu = device->subdevice("mcu"); - assert(state->m_cpu != NULL); - - device->save_item(NAME(state->m_latched_cmd)); - device->save_item(NAME(state->m_latched_rw)); - device->save_item(NAME(state->m_portO)); -} - - const device_type NAMCO_50XX = &device_creator; namco_50xx_device::namco_50xx_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) - : device_t(mconfig, NAMCO_50XX, "Namco 50xx", tag, owner, clock, "namco50", __FILE__) + : device_t(mconfig, NAMCO_50XX, "Namco 50xx", tag, owner, clock, "namco50", __FILE__), + m_cpu(*this, "mcu"), + m_latched_cmd(0), + m_latched_rw(0), + m_portO(0) { - m_token = global_alloc_clear(namco_50xx_state); } -namco_50xx_device::~namco_50xx_device() -{ - global_free(m_token); -} //------------------------------------------------- // device_start - device-specific startup @@ -313,7 +255,9 @@ namco_50xx_device::~namco_50xx_device() void namco_50xx_device::device_start() { - DEVICE_START_NAME( namco_50xx )(this); + save_item(NAME(m_latched_cmd)); + save_item(NAME(m_latched_rw)); + save_item(NAME(m_portO)); } //------------------------------------------------- diff --git a/src/mame/machine/namco50.h b/src/mame/machine/namco50.h index 2de8b8a7983..3d981bdd3e3 100644 --- a/src/mame/machine/namco50.h +++ b/src/mame/machine/namco50.h @@ -3,37 +3,45 @@ #ifndef NAMCO50_H #define NAMCO50_H - +#include "cpu/mb88xx/mb88xx.h" #define MCFG_NAMCO_50XX_ADD(_tag, _clock) \ MCFG_DEVICE_ADD(_tag, NAMCO_50XX, _clock) -DECLARE_READ8_DEVICE_HANDLER( namco_50xx_read ); -void namco_50xx_read_request(device_t *device); -DECLARE_WRITE8_DEVICE_HANDLER( namco_50xx_write ); - /* device get info callback */ class namco_50xx_device : public device_t { public: namco_50xx_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); - ~namco_50xx_device(); + + WRITE8_MEMBER( write ); + WRITE_LINE_MEMBER(read_request); + READ8_MEMBER( read ); + + READ8_MEMBER( K_r ); + READ8_MEMBER( R0_r ); + READ8_MEMBER( R2_r ); + WRITE8_MEMBER( O_w ); - // access to legacy token - struct namco_50xx_state *token() const { assert(m_token != NULL); return m_token; } protected: // device-level overrides virtual void device_start(); virtual const rom_entry *device_rom_region() const; virtual machine_config_constructor device_mconfig_additions() const; + + TIMER_CALLBACK_MEMBER( latch_callback ); + TIMER_CALLBACK_MEMBER( readrequest_callback ); + TIMER_CALLBACK_MEMBER( irq_clear ); + void irq_set(); private: // internal state - struct namco_50xx_state *m_token; + required_device m_cpu; + UINT8 m_latched_cmd; + UINT8 m_latched_rw; + UINT8 m_portO; }; extern const device_type NAMCO_50XX; - - #endif /* NAMCO50_H */ diff --git a/src/mame/machine/namco51.c b/src/mame/machine/namco51.c index fc733ec1f18..c7bf6f894b7 100644 --- a/src/mame/machine/namco51.c +++ b/src/mame/machine/namco51.c @@ -58,61 +58,29 @@ #include "emu.h" #include "namco51.h" -#include "cpu/mb88xx/mb88xx.h" -#include "devlegcy.h" #define VERBOSE 0 #define LOG(x) do { if (VERBOSE) logerror x; } while (0) -#define READ_PORT(st,num) (st)->m_in[num](0) -#define WRITE_PORT(st,num,data) (st)->m_out[num](0, data) +#define READ_PORT(num) m_in_##num(space, 0) +#define WRITE_PORT(num,data) m_out_##num(space, 0, data) - -struct namco_51xx_state +WRITE8_MEMBER( namco_51xx_device::write ) { - device_t * m_cpu; - devcb_resolved_read8 m_in[4]; - devcb_resolved_write8 m_out[2]; - INT32 m_lastcoins; - INT32 m_lastbuttons; - INT32 m_credits; - INT32 m_coins[2]; - INT32 m_coins_per_cred[2]; - INT32 m_creds_per_coin[2]; - INT32 m_in_count; - INT32 m_mode; - INT32 m_coincred_mode; - INT32 m_remap_joy; -}; - -INLINE namco_51xx_state *get_safe_token(device_t *device) -{ - assert(device != NULL); - assert(device->type() == NAMCO_51XX); - - return (namco_51xx_state *)downcast(device)->token(); -} - - - -WRITE8_DEVICE_HANDLER( namco_51xx_write ) -{ - namco_51xx_state *state = get_safe_token(device); - data &= 0x07; - LOG(("%s: custom 51XX write %02x\n",space.machine().describe_context(),data)); + LOG(("%s: custom 51XX write %02x\n",machine().describe_context(),data)); - if (state->m_coincred_mode) + if (m_coincred_mode) { - switch (state->m_coincred_mode--) + switch (m_coincred_mode--) { - case 4: state->m_coins_per_cred[0] = data; break; - case 3: state->m_creds_per_coin[0] = data; break; - case 2: state->m_coins_per_cred[1] = data; break; - case 1: state->m_creds_per_coin[1] = data; break; + case 4: m_coins_per_cred[0] = data; break; + case 3: m_creds_per_coin[0] = data; break; + case 2: m_coins_per_cred[1] = data; break; + case 1: m_creds_per_coin[1] = data; break; } } else @@ -123,9 +91,9 @@ WRITE8_DEVICE_HANDLER( namco_51xx_write ) break; case 1: // set coinage - state->m_coincred_mode = 4; + m_coincred_mode = 4; /* this is a good time to reset the credits counter */ - state->m_credits = 0; + m_credits = 0; { /* kludge for a possible bug in Xevious */ @@ -133,9 +101,9 @@ WRITE8_DEVICE_HANDLER( namco_51xx_write ) static int namcoio_51XX_kludge = 0; /* Only compute namcoio_51XX_kludge when gamedrv changes */ - if (namcoio_51XX_driver != &space.machine().system()) + if (namcoio_51XX_driver != &machine().system()) { - namcoio_51XX_driver = &space.machine().system(); + namcoio_51XX_driver = &machine().system(); if (strcmp(namcoio_51XX_driver->name, "xevious") == 0 || strcmp(namcoio_51XX_driver->parent, "xevious") == 0) namcoio_51XX_kludge = 1; @@ -145,28 +113,28 @@ WRITE8_DEVICE_HANDLER( namco_51xx_write ) if (namcoio_51XX_kludge) { - state->m_coincred_mode = 6; - state->m_remap_joy = 1; + m_coincred_mode = 6; + m_remap_joy = 1; } } break; case 2: // go in "credits" mode and enable start buttons - state->m_mode = 1; - state->m_in_count = 0; + m_mode = 1; + m_in_count = 0; break; case 3: // disable joystick remapping - state->m_remap_joy = 0; + m_remap_joy = 0; break; case 4: // enable joystick remapping - state->m_remap_joy = 1; + m_remap_joy = 1; break; case 5: // go in "switch" mode - state->m_mode = 0; - state->m_in_count = 0; + m_mode = 0; + m_in_count = 0; break; default: @@ -197,125 +165,123 @@ static const int joy_map[16] = { 0xf, 0xe, 0xd, 0x5, 0xc, 0x9, 0x7, 0x6, 0xb, 0x3, 0xa, 0x4, 0x1, 0x2, 0x0, 0x8 }; -READ8_DEVICE_HANDLER( namco_51xx_read ) +READ8_MEMBER( namco_51xx_device::read ) { - namco_51xx_state *state = get_safe_token(device); + LOG(("%s: custom 51XX read\n",machine().describe_context())); - LOG(("%s: custom 51XX read\n",space.machine().describe_context())); - - if (state->m_mode == 0) /* switch mode */ + if (m_mode == 0) /* switch mode */ { - switch ((state->m_in_count++) % 3) + switch ((m_in_count++) % 3) { default: - case 0: return READ_PORT(state,0) | (READ_PORT(state,1) << 4); - case 1: return READ_PORT(state,2) | (READ_PORT(state,3) << 4); + case 0: return READ_PORT(0) | (READ_PORT(1) << 4); + case 1: return READ_PORT(2) | (READ_PORT(3) << 4); case 2: return 0; // nothing? } } else /* credits mode */ { - switch ((state->m_in_count++) % 3) + switch ((m_in_count++) % 3) { default: case 0: // number of credits in BCD format { int in,toggle; - in = ~(READ_PORT(state,0) | (READ_PORT(state,1) << 4)); - toggle = in ^ state->m_lastcoins; - state->m_lastcoins = in; + in = ~(READ_PORT(0) | (READ_PORT(1) << 4)); + toggle = in ^ m_lastcoins; + m_lastcoins = in; - if (state->m_coins_per_cred[0] > 0) + if (m_coins_per_cred[0] > 0) { - if (state->m_credits >= 99) + if (m_credits >= 99) { - WRITE_PORT(state,1,1); // coin lockout + WRITE_PORT(1,1); // coin lockout } else { - WRITE_PORT(state,1,0); // coin lockout + WRITE_PORT(1,0); // coin lockout /* check if the user inserted a coin */ if (toggle & in & 0x10) { - state->m_coins[0]++; - WRITE_PORT(state,0,0x04); // coin counter - WRITE_PORT(state,0,0x0c); - if (state->m_coins[0] >= state->m_coins_per_cred[0]) + m_coins[0]++; + WRITE_PORT(0,0x04); // coin counter + WRITE_PORT(0,0x0c); + if (m_coins[0] >= m_coins_per_cred[0]) { - state->m_credits += state->m_creds_per_coin[0]; - state->m_coins[0] -= state->m_coins_per_cred[0]; + m_credits += m_creds_per_coin[0]; + m_coins[0] -= m_coins_per_cred[0]; } } if (toggle & in & 0x20) { - state->m_coins[1]++; - WRITE_PORT(state,0,0x08); // coin counter - WRITE_PORT(state,0,0x0c); - if (state->m_coins[1] >= state->m_coins_per_cred[1]) + m_coins[1]++; + WRITE_PORT(0,0x08); // coin counter + WRITE_PORT(0,0x0c); + if (m_coins[1] >= m_coins_per_cred[1]) { - state->m_credits += state->m_creds_per_coin[1]; - state->m_coins[1] -= state->m_coins_per_cred[1]; + m_credits += m_creds_per_coin[1]; + m_coins[1] -= m_coins_per_cred[1]; } } if (toggle & in & 0x40) { - state->m_credits++; + m_credits++; } } } - else state->m_credits = 100; // free play + else m_credits = 100; // free play - if (state->m_mode == 1) + if (m_mode == 1) { - int on = (device->machine().first_screen()->frame_number() & 0x10) >> 4; + int on = (machine().first_screen()->frame_number() & 0x10) >> 4; - if (state->m_credits >= 2) - WRITE_PORT(state,0,0x0c | 3*on); // lamps - else if (state->m_credits >= 1) - WRITE_PORT(state,0,0x0c | 2*on); // lamps + if (m_credits >= 2) + WRITE_PORT(0,0x0c | 3*on); // lamps + else if (m_credits >= 1) + WRITE_PORT(0,0x0c | 2*on); // lamps else - WRITE_PORT(state,0,0x0c); // lamps off + WRITE_PORT(0,0x0c); // lamps off /* check for 1 player start button */ if (toggle & in & 0x04) { - if (state->m_credits >= 1) + if (m_credits >= 1) { - state->m_credits--; - state->m_mode = 2; - WRITE_PORT(state,0,0x0c); // lamps off + m_credits--; + m_mode = 2; + WRITE_PORT(0,0x0c); // lamps off } } /* check for 2 players start button */ else if (toggle & in & 0x08) { - if (state->m_credits >= 2) + if (m_credits >= 2) { - state->m_credits -= 2; - state->m_mode = 2; - WRITE_PORT(state, 0,0x0c); // lamps off + m_credits -= 2; + m_mode = 2; + WRITE_PORT( 0,0x0c); // lamps off } } } } - if (~READ_PORT(state, 1) & 0x08) /* check test mode switch */ + if (~READ_PORT( 1) & 0x08) /* check test mode switch */ return 0xbb; - return (state->m_credits / 10) * 16 + state->m_credits % 10; + return (m_credits / 10) * 16 + m_credits % 10; case 1: { - int joy = READ_PORT(state,2) & 0x0f; + int joy = READ_PORT(2) & 0x0f; int in,toggle; - in = ~READ_PORT(state,0); - toggle = in ^ state->m_lastbuttons; - state->m_lastbuttons = (state->m_lastbuttons & 2) | (in & 1); + in = ~READ_PORT(0); + toggle = in ^ m_lastbuttons; + m_lastbuttons = (m_lastbuttons & 2) | (in & 1); /* remap joystick */ - if (state->m_remap_joy) joy = joy_map[joy]; + if (m_remap_joy) joy = joy_map[joy]; /* fire */ joy |= ((toggle & in & 0x01)^1) << 4; @@ -326,15 +292,15 @@ READ8_DEVICE_HANDLER( namco_51xx_read ) case 2: { - int joy = READ_PORT(state,3) & 0x0f; + int joy = READ_PORT(3) & 0x0f; int in,toggle; - in = ~READ_PORT(state,0); - toggle = in ^ state->m_lastbuttons; - state->m_lastbuttons = (state->m_lastbuttons & 1) | (in & 2); + in = ~READ_PORT(0); + toggle = in ^ m_lastbuttons; + m_lastbuttons = (m_lastbuttons & 1) | (in & 2); /* remap joystick */ - if (state->m_remap_joy) joy = joy_map[joy]; + if (m_remap_joy) joy = joy_map[joy]; /* fire */ joy |= ((toggle & in & 0x02)^2) << 3; @@ -374,85 +340,18 @@ ROM_START( namco_51xx ) ROM_LOAD( "51xx.bin", 0x0000, 0x0400, CRC(c2f57ef8) SHA1(50de79e0d6a76bda95ffb02fcce369a79e6abfec) ) ROM_END - -/*------------------------------------------------- - device start callback --------------------------------------------------*/ - -static DEVICE_START( namco_51xx ) -{ - const namco_51xx_interface *config = (const namco_51xx_interface *)device->static_config(); - namco_51xx_state *state = get_safe_token(device); - astring tempstring; - - assert(config != NULL); - - /* find our CPU */ - state->m_cpu = device->subdevice("mcu"); - assert(state->m_cpu != NULL); - - /* resolve our read callbacks */ - state->m_in[0].resolve(config->in[0], *device); - state->m_in[1].resolve(config->in[1], *device); - state->m_in[2].resolve(config->in[2], *device); - state->m_in[3].resolve(config->in[3], *device); - - /* resolve our write callbacks */ - state->m_out[0].resolve(config->out[0], *device); - state->m_out[1].resolve(config->out[1], *device); -#if 0 - INT32 lastcoins,lastbuttons; - INT32 credits; - INT32 coins[2]; - INT32 coins_per_cred[2]; - INT32 creds_per_coin[2]; - INT32 in_count; - INT32 mode,coincred_mode,remap_joy; -#endif - device->save_item(NAME(state->m_lastcoins)); - device->save_item(NAME(state->m_lastbuttons)); - device->save_item(NAME(state->m_credits)); - device->save_item(NAME(state->m_coins)); - device->save_item(NAME(state->m_coins_per_cred)); - device->save_item(NAME(state->m_creds_per_coin)); - device->save_item(NAME(state->m_in_count)); - device->save_item(NAME(state->m_mode)); - device->save_item(NAME(state->m_coincred_mode)); - device->save_item(NAME(state->m_remap_joy)); -} - - -/*------------------------------------------------- - device reset callback --------------------------------------------------*/ - -static DEVICE_RESET( namco_51xx ) -{ - namco_51xx_state *state = get_safe_token(device); - - /* reset internal registers */ - state->m_credits = 0; - state->m_coins[0] = 0; - state->m_coins_per_cred[0] = 1; - state->m_creds_per_coin[0] = 1; - state->m_coins[1] = 0; - state->m_coins_per_cred[1] = 1; - state->m_creds_per_coin[1] = 1; - state->m_in_count = 0; -} - - const device_type NAMCO_51XX = &device_creator; namco_51xx_device::namco_51xx_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) - : device_t(mconfig, NAMCO_51XX, "Namco 51xx", tag, owner, clock, "namco51", __FILE__) + : device_t(mconfig, NAMCO_51XX, "Namco 51xx", tag, owner, clock, "namco51", __FILE__), + m_cpu(*this, "mcu"), + m_in_0(*this), + m_in_1(*this), + m_in_2(*this), + m_in_3(*this), + m_out_0(*this), + m_out_1(*this) { - m_token = global_alloc_clear(namco_51xx_state); -} - -namco_51xx_device::~namco_51xx_device() -{ - global_free(m_token); } //------------------------------------------------- @@ -461,7 +360,26 @@ namco_51xx_device::~namco_51xx_device() void namco_51xx_device::device_start() { - DEVICE_START_NAME( namco_51xx )(this); + /* resolve our read callbacks */ + m_in_0.resolve_safe(0); + m_in_1.resolve_safe(0); + m_in_2.resolve_safe(0); + m_in_3.resolve_safe(0); + + /* resolve our write callbacks */ + m_out_0.resolve_safe(); + m_out_1.resolve_safe(); + + save_item(NAME(m_lastcoins)); + save_item(NAME(m_lastbuttons)); + save_item(NAME(m_credits)); + save_item(NAME(m_coins)); + save_item(NAME(m_coins_per_cred)); + save_item(NAME(m_creds_per_coin)); + save_item(NAME(m_in_count)); + save_item(NAME(m_mode)); + save_item(NAME(m_coincred_mode)); + save_item(NAME(m_remap_joy)); } //------------------------------------------------- @@ -470,7 +388,15 @@ void namco_51xx_device::device_start() void namco_51xx_device::device_reset() { - DEVICE_RESET_NAME( namco_51xx )(this); + /* reset internal registers */ + m_credits = 0; + m_coins[0] = 0; + m_coins_per_cred[0] = 1; + m_creds_per_coin[0] = 1; + m_coins[1] = 0; + m_coins_per_cred[1] = 1; + m_creds_per_coin[1] = 1; + m_in_count = 0; } //------------------------------------------------- diff --git a/src/mame/machine/namco51.h b/src/mame/machine/namco51.h index 40ac6c723c4..1e5533df222 100644 --- a/src/mame/machine/namco51.h +++ b/src/mame/machine/namco51.h @@ -3,32 +3,46 @@ #ifndef NAMCO51_H #define NAMCO51_H +#include "cpu/mb88xx/mb88xx.h" -struct namco_51xx_interface -{ - devcb_read8 in[4]; /* read handlers for ports A-D */ - devcb_write8 out[2]; /* write handlers for ports A-B */ -}; +#define MCFG_NAMCO_51XX_ADD(_tag, _clock) \ + MCFG_DEVICE_ADD(_tag, NAMCO_51XX, _clock) +#define MCFG_NAMCO_51XX_INPUT_0_CB(_devcb) \ + devcb = &namco_51xx_device::set_input_0_callback(*device, DEVCB2_##_devcb); -#define MCFG_NAMCO_51XX_ADD(_tag, _clock, _interface) \ - MCFG_DEVICE_ADD(_tag, NAMCO_51XX, _clock) \ - MCFG_DEVICE_CONFIG(_interface) +#define MCFG_NAMCO_51XX_INPUT_1_CB(_devcb) \ + devcb = &namco_51xx_device::set_input_1_callback(*device, DEVCB2_##_devcb); +#define MCFG_NAMCO_51XX_INPUT_2_CB(_devcb) \ + devcb = &namco_51xx_device::set_input_2_callback(*device, DEVCB2_##_devcb); -DECLARE_READ8_DEVICE_HANDLER( namco_51xx_read ); -DECLARE_WRITE8_DEVICE_HANDLER( namco_51xx_write ); +#define MCFG_NAMCO_51XX_INPUT_3_CB(_devcb) \ + devcb = &namco_51xx_device::set_input_3_callback(*device, DEVCB2_##_devcb); +#define MCFG_NAMCO_51XX_OUTPUT_0_CB(_devcb) \ + devcb = &namco_51xx_device::set_output_0_callback(*device, DEVCB2_##_devcb); + +#define MCFG_NAMCO_51XX_OUTPUT_1_CB(_devcb) \ + devcb = &namco_51xx_device::set_output_1_callback(*device, DEVCB2_##_devcb); class namco_51xx_device : public device_t { public: namco_51xx_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); - ~namco_51xx_device(); - // access to legacy token - struct namco_51xx_state *token() const { assert(m_token != NULL); return m_token; } + template static devcb2_base &set_input_0_callback(device_t &device, _Object object) { return downcast(device).m_in_0.set_callback(object); } + template static devcb2_base &set_input_1_callback(device_t &device, _Object object) { return downcast(device).m_in_1.set_callback(object); } + template static devcb2_base &set_input_2_callback(device_t &device, _Object object) { return downcast(device).m_in_2.set_callback(object); } + template static devcb2_base &set_input_3_callback(device_t &device, _Object object) { return downcast(device).m_in_3.set_callback(object); } + + template static devcb2_base &set_output_0_callback(device_t &device, _Object object) { return downcast(device).m_out_0.set_callback(object); } + template static devcb2_base &set_output_1_callback(device_t &device, _Object object) { return downcast(device).m_out_1.set_callback(object); } + + DECLARE_WRITE8_MEMBER( write ); + DECLARE_READ8_MEMBER( read ); + protected: // device-level overrides virtual void device_start(); @@ -37,7 +51,23 @@ protected: virtual machine_config_constructor device_mconfig_additions() const; private: // internal state - struct namco_51xx_state *m_token; + required_device m_cpu; + devcb2_read8 m_in_0; + devcb2_read8 m_in_1; + devcb2_read8 m_in_2; + devcb2_read8 m_in_3; + devcb2_write8 m_out_0; + devcb2_write8 m_out_1; + INT32 m_lastcoins; + INT32 m_lastbuttons; + INT32 m_credits; + INT32 m_coins[2]; + INT32 m_coins_per_cred[2]; + INT32 m_creds_per_coin[2]; + INT32 m_in_count; + INT32 m_mode; + INT32 m_coincred_mode; + INT32 m_remap_joy; }; extern const device_type NAMCO_51XX; diff --git a/src/mame/machine/namco53.c b/src/mame/machine/namco53.c index ccd6a17bc14..fbfa9083f29 100644 --- a/src/mame/machine/namco53.c +++ b/src/mame/machine/namco53.c @@ -56,87 +56,65 @@ #include "emu.h" #include "namco53.h" -#include "cpu/mb88xx/mb88xx.h" -#include "devlegcy.h" #define VERBOSE 0 #define LOG(x) do { if (VERBOSE) logerror x; } while (0) - -struct namco_53xx_state +READ8_MEMBER( namco_53xx_device::K_r ) { - device_t * m_cpu; - UINT8 m_portO; - devcb_resolved_read8 m_k; - devcb_resolved_read8 m_in[4]; - devcb_resolved_write8 m_p; -}; - -INLINE namco_53xx_state *get_safe_token(device_t *device) -{ - assert(device != NULL); - assert(device->type() == NAMCO_53XX); - - return (namco_53xx_state *)downcast(device)->token(); + return m_k(0); } - - -static READ8_HANDLER( namco_53xx_K_r ) +READ8_MEMBER( namco_53xx_device::Rx_r ) { - namco_53xx_state *state = get_safe_token(space.device().owner()); - return state->m_k(0); + switch(offset) { + case 0 : return m_in_0(0); + case 1 : return m_in_1(0); + case 2 : return m_in_2(0); + case 3 : return m_in_3(0); + default : return 0xff; + } + } -static READ8_HANDLER( namco_53xx_Rx_r ) +WRITE8_MEMBER( namco_53xx_device::O_w ) { - namco_53xx_state *state = get_safe_token(space.device().owner()); - return state->m_in[offset](0); -} - -static WRITE8_HANDLER( namco_53xx_O_w ) -{ - namco_53xx_state *state = get_safe_token(space.device().owner()); UINT8 out = (data & 0x0f); if (data & 0x10) - state->m_portO = (state->m_portO & 0x0f) | (out << 4); + m_portO = (m_portO & 0x0f) | (out << 4); else - state->m_portO = (state->m_portO & 0xf0) | (out); + m_portO = (m_portO & 0xf0) | (out); } -static WRITE8_HANDLER( namco_53xx_P_w ) +WRITE8_MEMBER( namco_53xx_device::P_w ) { - namco_53xx_state *state = get_safe_token(space.device().owner()); - state->m_p(0, data); + m_p(space, 0, data); } -static TIMER_CALLBACK( namco_53xx_irq_clear ) +TIMER_CALLBACK_MEMBER( namco_53xx_device::irq_clear ) { - namco_53xx_state *state = get_safe_token((device_t *)ptr); - state->m_cpu->execute().set_input_line(0, CLEAR_LINE); + m_cpu->set_input_line(0, CLEAR_LINE); } -void namco_53xx_read_request(device_t *device) +WRITE_LINE_MEMBER(namco_53xx_device::read_request) { - namco_53xx_state *state = get_safe_token(device); - state->m_cpu->execute().set_input_line(0, ASSERT_LINE); + m_cpu->set_input_line(0, ASSERT_LINE); // The execution time of one instruction is ~4us, so we must make sure to // give the cpu time to poll the /IRQ input before we clear it. // The input clock to the 06XX interface chip is 64H, that is // 18432000/6/64 = 48kHz, so it makes sense for the irq line to be // asserted for one clock cycle ~= 21us. - device->machine().scheduler().timer_set(attotime::from_usec(21), FUNC(namco_53xx_irq_clear), 0, (void *)device); + machine().scheduler().timer_set(attotime::from_usec(21), timer_expired_delegate(FUNC(namco_53xx_device::irq_clear),this), 0); } -READ8_DEVICE_HANDLER( namco_53xx_read ) +READ8_MEMBER( namco_53xx_device::read ) { - namco_53xx_state *state = get_safe_token(device); - UINT8 res = state->m_portO; + UINT8 res = m_portO; - namco_53xx_read_request(device); + read_request(0); return res; } @@ -147,10 +125,10 @@ READ8_DEVICE_HANDLER( namco_53xx_read ) ***************************************************************************/ static ADDRESS_MAP_START( namco_53xx_map_io, AS_IO, 8,namco_53xx_device ) - AM_RANGE(MB88_PORTK, MB88_PORTK) AM_READ_LEGACY(namco_53xx_K_r) - AM_RANGE(MB88_PORTO, MB88_PORTO) AM_WRITE_LEGACY(namco_53xx_O_w) - AM_RANGE(MB88_PORTP, MB88_PORTP) AM_WRITE_LEGACY(namco_53xx_P_w) - AM_RANGE(MB88_PORTR0, MB88_PORTR3) AM_READ_LEGACY(namco_53xx_Rx_r) + AM_RANGE(MB88_PORTK, MB88_PORTK) AM_READ(K_r) + AM_RANGE(MB88_PORTO, MB88_PORTO) AM_WRITE(O_w) + AM_RANGE(MB88_PORTP, MB88_PORTP) AM_WRITE(P_w) + AM_RANGE(MB88_PORTR0, MB88_PORTR3) AM_READ(Rx_r) ADDRESS_MAP_END @@ -165,55 +143,35 @@ ROM_START( namco_53xx ) ROM_LOAD( "53xx.bin", 0x0000, 0x0400, CRC(b326fecb) SHA1(758d8583d658e4f1df93184009d86c3eb8713899) ) ROM_END - -/*------------------------------------------------- - device start callback --------------------------------------------------*/ - -static DEVICE_START( namco_53xx ) -{ - const namco_53xx_interface *config = (const namco_53xx_interface *)device->static_config(); - namco_53xx_state *state = get_safe_token(device); - astring tempstring; - - assert(config != NULL); - - /* find our CPU */ - state->m_cpu = device->subdevice("mcu"); - assert(state->m_cpu != NULL); - - /* resolve our read/write callbacks */ - state->m_k.resolve(config->k, *device); - state->m_in[0].resolve(config->in[0], *device); - state->m_in[1].resolve(config->in[1], *device); - state->m_in[2].resolve(config->in[2], *device); - state->m_in[3].resolve(config->in[3], *device); - state->m_p.resolve(config->p, *device); - - device->save_item(NAME(state->m_portO)); -} - - const device_type NAMCO_53XX = &device_creator; namco_53xx_device::namco_53xx_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) - : device_t(mconfig, NAMCO_53XX, "Namco 53xx", tag, owner, clock, "namco53", __FILE__) + : device_t(mconfig, NAMCO_53XX, "Namco 53xx", tag, owner, clock, "namco53", __FILE__), + m_cpu(*this, "mcu"), + m_portO(0), + m_k(*this), + m_in_0(*this), + m_in_1(*this), + m_in_2(*this), + m_in_3(*this), + m_p(*this) { - m_token = global_alloc_clear(namco_53xx_state); } - -namco_53xx_device::~namco_53xx_device() -{ - global_free(m_token); -} - //------------------------------------------------- // device_start - device-specific startup //------------------------------------------------- void namco_53xx_device::device_start() { - DEVICE_START_NAME( namco_53xx )(this); + /* resolve our read/write callbacks */ + m_k.resolve_safe(0); + m_in_0.resolve_safe(0); + m_in_1.resolve_safe(0); + m_in_2.resolve_safe(0); + m_in_3.resolve_safe(0); + m_p.resolve_safe(); + + save_item(NAME(m_portO)); } //------------------------------------------------- diff --git a/src/mame/machine/namco53.h b/src/mame/machine/namco53.h index ed82684e7a7..3c6eb0807c4 100644 --- a/src/mame/machine/namco53.h +++ b/src/mame/machine/namco53.h @@ -3,41 +3,69 @@ #ifndef NAMCO53_H #define NAMCO53_H +#include "cpu/mb88xx/mb88xx.h" +#define MCFG_NAMCO_53XX_ADD(_tag, _clock) \ + MCFG_DEVICE_ADD(_tag, NAMCO_53XX, _clock) -struct namco_53xx_interface -{ - devcb_read8 k; /* read handlers for K port */ - devcb_read8 in[4]; /* read handlers for ports A-D */ - devcb_write8 p; /* write handler for P port */ -}; +#define MCFG_NAMCO_53XX_K_CB(_devcb) \ + devcb = &namco_53xx_device::set_k_port_callback(*device, DEVCB2_##_devcb); +#define MCFG_NAMCO_53XX_INPUT_0_CB(_devcb) \ + devcb = &namco_53xx_device::set_input_0_callback(*device, DEVCB2_##_devcb); -#define MCFG_NAMCO_53XX_ADD(_tag, _clock, _interface) \ - MCFG_DEVICE_ADD(_tag, NAMCO_53XX, _clock) \ - MCFG_DEVICE_CONFIG(_interface) +#define MCFG_NAMCO_53XX_INPUT_1_CB(_devcb) \ + devcb = &namco_53xx_device::set_input_1_callback(*device, DEVCB2_##_devcb); +#define MCFG_NAMCO_53XX_INPUT_2_CB(_devcb) \ + devcb = &namco_53xx_device::set_input_2_callback(*device, DEVCB2_##_devcb); -void namco_53xx_read_request(device_t *device); -DECLARE_READ8_DEVICE_HANDLER( namco_53xx_read ); +#define MCFG_NAMCO_53XX_INPUT_3_CB(_devcb) \ + devcb = &namco_53xx_device::set_input_3_callback(*device, DEVCB2_##_devcb); +#define MCFG_NAMCO_53XX_P_CB(_devcb) \ + devcb = &namco_53xx_device::set_p_port_callback(*device, DEVCB2_##_devcb); + class namco_53xx_device : public device_t { public: namco_53xx_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); - ~namco_53xx_device(); - // access to legacy token - struct namco_53xx_state *token() const { assert(m_token != NULL); return m_token; } + template static devcb2_base &set_input_0_callback(device_t &device, _Object object) { return downcast(device).m_in_0.set_callback(object); } + template static devcb2_base &set_input_1_callback(device_t &device, _Object object) { return downcast(device).m_in_1.set_callback(object); } + template static devcb2_base &set_input_2_callback(device_t &device, _Object object) { return downcast(device).m_in_2.set_callback(object); } + template static devcb2_base &set_input_3_callback(device_t &device, _Object object) { return downcast(device).m_in_3.set_callback(object); } + + template static devcb2_base &set_k_port_callback(device_t &device, _Object object) { return downcast(device).m_k.set_callback(object); } + template static devcb2_base &set_p_port_callback(device_t &device, _Object object) { return downcast(device).m_p.set_callback(object); } + + DECLARE_READ8_MEMBER( K_r ); + DECLARE_READ8_MEMBER( Rx_r ); + DECLARE_WRITE8_MEMBER( O_w ); + DECLARE_WRITE8_MEMBER( P_w ); + + DECLARE_WRITE_LINE_MEMBER(read_request); + DECLARE_READ8_MEMBER( read ); + protected: // device-level overrides virtual void device_start(); virtual const rom_entry *device_rom_region() const; virtual machine_config_constructor device_mconfig_additions() const; + + TIMER_CALLBACK_MEMBER( irq_clear ); private: // internal state - struct namco_53xx_state *m_token; + required_device m_cpu; + UINT8 m_portO; + devcb2_read8 m_k; + devcb2_read8 m_in_0; + devcb2_read8 m_in_1; + devcb2_read8 m_in_2; + devcb2_read8 m_in_3; + devcb2_write8 m_p; + }; extern const device_type NAMCO_53XX; diff --git a/src/mame/machine/namco62.c b/src/mame/machine/namco62.c index 03e8a35057d..de31253c472 100644 --- a/src/mame/machine/namco62.c +++ b/src/mame/machine/namco62.c @@ -11,8 +11,6 @@ #include "emu.h" #include "machine/namco62.h" -#include "cpu/mb88xx/mb88xx.h" - #define VERBOSE 0 #define LOG(x) do { if (VERBOSE) logerror x; } while (0) @@ -45,54 +43,32 @@ ROM_END const device_type NAMCO_62XX = &device_creator; namco_62xx_device::namco_62xx_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) - : device_t(mconfig, NAMCO_62XX, "Namco 62xx", tag, owner, clock, "namco62", __FILE__) + : device_t(mconfig, NAMCO_62XX, "Namco 62xx", tag, owner, clock, "namco62", __FILE__), + m_cpu(*this, "mcu"), + m_in_0(*this), + m_in_1(*this), + m_in_2(*this), + m_in_3(*this), + m_out_0(*this), + m_out_1(*this) { } -//------------------------------------------------- -// device_config_complete - perform any -// operations now that the configuration is -// complete -//------------------------------------------------- - -void namco_62xx_device::device_config_complete() -{ - // inherit a copy of the static data - const namco_62xx_interface *intf = reinterpret_cast(static_config()); - if (intf != NULL) - *static_cast(this) = *intf; - - // or initialize to defaults if none provided - else - { - memset(&m_in[0], 0, sizeof(m_in[0])); - memset(&m_in[1], 0, sizeof(m_in[1])); - memset(&m_in[2], 0, sizeof(m_in[2])); - memset(&m_in[3], 0, sizeof(m_in[3])); - memset(&m_out[0], 0, sizeof(m_out[0])); - memset(&m_out[1], 0, sizeof(m_out[1])); - } -} - //------------------------------------------------- // device_start - device-specific startup //------------------------------------------------- void namco_62xx_device::device_start() { - /* find our CPU */ - m_cpu = subdevice("mcu"); - assert(m_cpu != NULL); - /* resolve our read callbacks */ - m_in_func[0].resolve(m_in[0], *this); - m_in_func[1].resolve(m_in[1], *this); - m_in_func[2].resolve(m_in[2], *this); - m_in_func[3].resolve(m_in[3], *this); + m_in_0.resolve_safe(0); + m_in_1.resolve_safe(0); + m_in_2.resolve_safe(0); + m_in_3.resolve_safe(0); /* resolve our write callbacks */ - m_out_func[0].resolve(m_out[0], *this); - m_out_func[1].resolve(m_out[1], *this); + m_out_0.resolve_safe(); + m_out_1.resolve_safe(); } //------------------------------------------------- diff --git a/src/mame/machine/namco62.h b/src/mame/machine/namco62.h index 8b058555635..e2358e1fe1b 100644 --- a/src/mame/machine/namco62.h +++ b/src/mame/machine/namco62.h @@ -1,21 +1,43 @@ #ifndef NAMCO62_H #define NAMCO62_H +#include "cpu/mb88xx/mb88xx.h" +#define MCFG_NAMCO_62XX_ADD(_tag, _clock) \ + MCFG_DEVICE_ADD(_tag, NAMCO_62XX, _clock) -struct namco_62xx_interface -{ - devcb_read8 m_in[4]; /* read handlers for ports A-D */ - devcb_write8 m_out[2]; /* write handlers for ports A-B */ -}; +#define MCFG_NAMCO_62XX_INPUT_0_CB(_devcb) \ + devcb = &namco_62xx_device::set_input_0_callback(*device, DEVCB2_##_devcb); +#define MCFG_NAMCO_62XX_INPUT_1_CB(_devcb) \ + devcb = &namco_62xx_device::set_input_1_callback(*device, DEVCB2_##_devcb); + +#define MCFG_NAMCO_62XX_INPUT_2_CB(_devcb) \ + devcb = &namco_62xx_device::set_input_2_callback(*device, DEVCB2_##_devcb); + +#define MCFG_NAMCO_62XX_INPUT_3_CB(_devcb) \ + devcb = &namco_62xx_device::set_input_3_callback(*device, DEVCB2_##_devcb); + +#define MCFG_NAMCO_62XX_OUTPUT_0_CB(_devcb) \ + devcb = &namco_62xx_device::set_output_0_callback(*device, DEVCB2_##_devcb); + +#define MCFG_NAMCO_62XX_OUTPUT_1_CB(_devcb) \ + devcb = &namco_62xx_device::set_output_1_callback(*device, DEVCB2_##_devcb); + class namco_62xx_device : public device_t, public namco_62xx_interface { public: namco_62xx_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); - ~namco_62xx_device() {} + template static devcb2_base &set_input_0_callback(device_t &device, _Object object) { return downcast(device).m_in_0.set_callback(object); } + template static devcb2_base &set_input_1_callback(device_t &device, _Object object) { return downcast(device).m_in_1.set_callback(object); } + template static devcb2_base &set_input_2_callback(device_t &device, _Object object) { return downcast(device).m_in_2.set_callback(object); } + template static devcb2_base &set_input_3_callback(device_t &device, _Object object) { return downcast(device).m_in_3.set_callback(object); } + + template static devcb2_base &set_output_0_callback(device_t &device, _Object object) { return downcast(device).m_out_0.set_callback(object); } + template static devcb2_base &set_output_1_callback(device_t &device, _Object object) { return downcast(device).m_out_1.set_callback(object); } + DECLARE_READ8_MEMBER( read ); DECLARE_WRITE8_MEMBER( write ); @@ -28,15 +50,15 @@ protected: private: // internal state - device_t* m_cpu; - devcb_resolved_read8 m_in_func[4]; - devcb_resolved_write8 m_out_func[2]; + required_device m_cpu; + devcb2_read8 m_in_0; + devcb2_read8 m_in_1; + devcb2_read8 m_in_2; + devcb2_read8 m_in_3; + devcb2_write8 m_out_0; + devcb2_write8 m_out_1; }; extern const device_type NAMCO_62XX; -#define MCFG_NAMCO_62XX_ADD(_tag, _clock, _interface) \ - MCFG_DEVICE_ADD(_tag, NAMCO_62XX, _clock) \ - MCFG_DEVICE_CONFIG(_interface) - #endif /* NAMCO62_H */