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https://github.com/holub/mame
synced 2025-04-25 09:50:04 +03:00
qvt70: More work (nw)
This commit is contained in:
Dirk Best
parent
e44c470f0f
commit
cae02668fa
@ -26,18 +26,21 @@
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#include "emu.h"
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#include "cpu/z80/z80.h"
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#include "machine/bankdev.h"
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#include "machine/z80dart.h"
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#include "bus/centronics/ctronics.h"
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#include "bus/rs232/rs232.h"
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#include "emupal.h"
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#include "screen.h"
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class qvt70_state : public driver_device
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{
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public:
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qvt70_state(const machine_config &mconfig, device_type type, const char *tag)
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: driver_device(mconfig, type, tag)
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, m_maincpu(*this, "maincpu")
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, m_bank(*this, "bank")
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: driver_device(mconfig, type, tag),
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m_maincpu(*this, "maincpu"),
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m_rombank(*this, "rom"),
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m_rambank(*this, "ram%d", 0U),
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m_gfxdecode(*this, "gfxdecode")
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{ }
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void qvt70(machine_config &config);
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@ -48,50 +51,287 @@ protected:
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private:
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required_device<cpu_device> m_maincpu;
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required_device<address_map_bank_device> m_bank;
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required_memory_bank m_rombank;
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required_memory_bank_array<2> m_rambank;
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required_device<gfxdecode_device> m_gfxdecode;
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void mem_map(address_map &map);
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void bank_map(address_map &map);
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void io_map(address_map &map);
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void bankswitch_w(uint8_t data);
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uint32_t screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
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void vblank_w(int state);
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void rombank_w(uint8_t data);
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// gate array
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void voffset_lsb_w(uint8_t data);
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void voffset_msb_w(uint8_t data);
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uint8_t unk_1d_r();
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void unk_1d_w(uint8_t data);
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uint8_t unk_1e_r();
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void unk_1e_w(uint8_t data);
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void unk_1f_w(uint8_t data);
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uint8_t unk_32_r();
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void unk_42_w(uint8_t data);
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void unk_60_w(uint8_t data);
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std::unique_ptr<uint8_t[]> m_ram;
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uint8_t m_1d, m_1e, m_1f;
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bool m_nmi_enable;
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uint16_t m_voffset;
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};
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void qvt70_state::mem_map(address_map &map)
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{
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map(0x0000, 0x7fff).m(m_bank, FUNC(address_map_bank_device::amap8));
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map(0x8000, 0x8000).w(FUNC(qvt70_state::bankswitch_w));
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map(0x0000, 0x7fff).bankr("rom");
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map(0x8000, 0x8000).w(FUNC(qvt70_state::rombank_w));
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map(0xa000, 0xbfff).ram();
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map(0xc000, 0xdfff).ram();
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map(0xe000, 0xffff).ram();
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}
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void qvt70_state::bank_map(address_map &map)
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{
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map(0x00000, 0x07fff).rom().region("maincpu", 0x00000);
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map(0x08000, 0x0ffff).rom().region("maincpu", 0x08000);
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map(0x10000, 0x17fff).rom().region("maincpu", 0x10000);
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map(0x18000, 0x1ffff).rom().region("maincpu", 0x18000);
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map(0x20000, 0x27fff).rom().region("maincpu", 0x20000);
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map(0x28000, 0x2ffff).rom().region("maincpu", 0x28000);
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map(0x30000, 0x37fff).ram();
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// map(0x38000, 0x3ffff)
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map(0xc000, 0xdfff).bankrw("ram0");
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map(0xe000, 0xffff).bankrw("ram1");
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}
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void qvt70_state::io_map(address_map &map)
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{
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map.global_mask(0xff);
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// 07-54
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// 60-6f
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// map(0x07, 0x07) // ? (set to 0x5d)
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// map(0x08, 0x08) // ? (set to 0x00)
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// map(0x09, 0x09) // ? (set to 0x00)
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map(0x0a, 0x0a).w(FUNC(qvt70_state::voffset_lsb_w));
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map(0x0b, 0x0b).w(FUNC(qvt70_state::voffset_msb_w));
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// map(0x0c, 0x0c) // ? (set to 0x5e then 0x67)
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// map(0x0d, 0x0d) // ? (set to 0x0c then 0x04)
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// map(0x0e, 0x0e) // ? (set to 0x0f then 0x07)
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// map(0x0f, 0x0f) // ? (set to 0x06 then 0x07)
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// map(0x10, 0x10) // columns? (set to 0x50 = 80)
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// map(0x11, 0x11) // columns? (set to 0x84 = 132)
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// map(0x12, 0x12) // ? (set to 0x31 = 49)
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// map(0x13, 0x13) // rows? (set to 0x19 = 25)
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// map(0x14, 0x14) // ? (set to 0x39 = 57)
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// map(0x15, 0x15) // ? (set to 0x60 = 96)
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// map(0x16, 0x16) // ? (set to 0x39 = 57)
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// map(0x17, 0x17) // debug output? (used during memtest)
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// map(0x18, 0x18) // ? (set to 0x20 = 32)
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// map(0x19, 0x19) // ? (set to 0x0f = 15)
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// map(0x1a, 0x1a) // ? (set to 0x00 then 0xff)
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// map(0x1b, 0x1b) // ? (set to 0x20 = 32)
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// map(0x1c, 0x1c) // ? (set to 0x50 then 0xff)
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map(0x1d, 0x1d).rw(FUNC(qvt70_state::unk_1d_r), FUNC(qvt70_state::unk_1d_w)); // ram banking? status?
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map(0x1e, 0x1e).rw(FUNC(qvt70_state::unk_1e_r), FUNC(qvt70_state::unk_1e_w)); // ram banking?
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map(0x1f, 0x1f).w(FUNC(qvt70_state::unk_1f_w));
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// map(0x20, 0x20) // ? (set to 0x00)
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// map(0x21, 0x21) // ? (set to 0x00)
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// map(0x22, 0x22) // ? (set to 0x00)
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// map(0x23, 0x23) // ? (set to 0x00)
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// map(0x24, 0x24) // ? (set to 0x00)
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// map(0x25, 0x25) // ? (set to 0xa0)
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// map(0x26, 0x26) // ? (set to 0xff)
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// map(0x27, 0x27) // ? (set to 0x80)
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// map(0x28, 0x28) // ? (set to 0x9f)
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// 29-31
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map(0x32, 0x32).r(FUNC(qvt70_state::unk_32_r)); // keyboard data?
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// 33-41
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map(0x42, 0x42).w(FUNC(qvt70_state::unk_42_w)); // nmi enable?
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// 43-54
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map(0x60, 0x60).w(FUNC(qvt70_state::unk_60_w)); // nmi enable?
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// 61-6f
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map(0x80, 0x83).rw("dart", FUNC(z80dart_device::ba_cd_r), FUNC(z80dart_device::ba_cd_w));
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}
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static INPUT_PORTS_START( qvt70 )
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PORT_START("1d")
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PORT_DIPUNKNOWN_DIPLOC(0x01, 0x00, "1d:1")
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PORT_DIPUNKNOWN_DIPLOC(0x02, 0x02, "1d:2")
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PORT_DIPUNKNOWN_DIPLOC(0x04, 0x00, "1d:3")
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PORT_DIPUNKNOWN_DIPLOC(0x08, 0x00, "1d:4")
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PORT_DIPUNKNOWN_DIPLOC(0x10, 0x00, "1d:5")
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PORT_DIPUNKNOWN_DIPLOC(0x20, 0x00, "1d:6")
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PORT_DIPUNKNOWN_DIPLOC(0x40, 0x00, "1d:7")
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PORT_DIPUNKNOWN_DIPLOC(0x80, 0x00, "1d:8")
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PORT_START("1e")
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PORT_DIPUNKNOWN_DIPLOC(0x01, 0x00, "1e:1")
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PORT_DIPUNKNOWN_DIPLOC(0x02, 0x00, "1e:2")
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PORT_DIPUNKNOWN_DIPLOC(0x04, 0x00, "1e:3")
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PORT_DIPUNKNOWN_DIPLOC(0x08, 0x00, "1e:4")
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PORT_DIPUNKNOWN_DIPLOC(0x10, 0x00, "1e:5")
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PORT_DIPUNKNOWN_DIPLOC(0x20, 0x00, "1e:6")
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PORT_DIPUNKNOWN_DIPLOC(0x40, 0x00, "1e:7")
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PORT_DIPUNKNOWN_DIPLOC(0x80, 0x00, "1e:8")
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PORT_START("32")
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PORT_DIPUNKNOWN_DIPLOC(0x01, 0x00, "32:1")
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PORT_DIPUNKNOWN_DIPLOC(0x02, 0x00, "32:2")
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PORT_DIPUNKNOWN_DIPLOC(0x04, 0x00, "32:3")
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PORT_DIPUNKNOWN_DIPLOC(0x08, 0x00, "32:4")
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PORT_DIPUNKNOWN_DIPLOC(0x10, 0x00, "32:5")
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PORT_DIPUNKNOWN_DIPLOC(0x20, 0x00, "32:6")
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PORT_DIPUNKNOWN_DIPLOC(0x40, 0x00, "32:7")
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PORT_DIPUNKNOWN_DIPLOC(0x80, 0x00, "32:8")
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INPUT_PORTS_END
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void qvt70_state::bankswitch_w(uint8_t data)
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static const gfx_layout char_layout_8x16 =
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{
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logerror("bankswitch_w: %02x\n", data);
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8, 16,
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256,
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1,
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{ 0 },
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{ STEP8(0, 1) },
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{ STEP16(0, 8) },
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8*16
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};
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static const gfx_layout char_layout_8x9 =
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{
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8, 9,
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256,
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1,
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{ 0 },
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{ STEP8(0, 1) },
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{ 0*8, 1*8, 2*8, 3*8, 4*8, 5*8, 6*8, 7*8, 8*8 },
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8*16
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};
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static GFXDECODE_START(chars)
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GFXDECODE_RAM(nullptr, 0, char_layout_8x16, 0, 1)
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GFXDECODE_RAM(nullptr, 0, char_layout_8x9, 0, 1)
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GFXDECODE_END
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uint32_t qvt70_state::screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect)
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{
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if (m_voffset == 0)
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return 0;
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for (int y = 0; y < 27; y++)
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{
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for (int x = 0; x < 132; x++)
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{
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uint8_t code = m_maincpu->space(AS_PROGRAM).read_byte(m_voffset + (y * 132) + x);
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// draw 16 lines
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for (int i = 0; i < 16; i++)
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{
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uint8_t data = m_ram[0x2000 * 7 | ((code << 4) + i)];
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// 8 pixels of the character
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for (int p = 0; p < 8; p++)
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bitmap.pix32(y * 16 + i, x * 8 + p) = BIT(data, 7 - p) ? rgb_t::white() : rgb_t::black();
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}
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}
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}
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return 0;
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}
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void qvt70_state::vblank_w(int state)
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{
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if (state == 1 && m_nmi_enable)
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m_maincpu->pulse_input_line(INPUT_LINE_NMI, attotime::zero);
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}
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void qvt70_state::voffset_lsb_w(uint8_t data)
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{
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m_voffset = (m_voffset & 0xff00) | data;
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}
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void qvt70_state::voffset_msb_w(uint8_t data)
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{
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m_voffset = (data << 8) | (m_voffset & 0x00ff);
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logerror("voffset = %04x\n", m_voffset);
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}
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uint8_t qvt70_state::unk_1d_r()
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{
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// 7654---- unknown
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// ----3--- data available on io port 32
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// -----210 unknown
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uint8_t val = 0;
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val = ioport("1d")->read();
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// val = machine().rand();
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logerror("1d read: %02x\n", val);
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return val;
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}
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void qvt70_state::unk_1d_w(uint8_t data)
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{
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logerror("1d = %02x\n", data);
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m_1d = data;
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// banking is likely wrong
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// the vram test sets 1d = 04 and wants c000-dfff and e000-ffff to
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// point to the same area
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// c000-dfff
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switch (data & 0x0c)
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{
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case 0x00: m_rambank[0]->set_entry(0); break;
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case 0x04: m_rambank[0]->set_entry(1); break;
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case 0x08: m_rambank[0]->set_entry(2); break;
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case 0x0c: m_rambank[0]->set_entry(3); break;
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}
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// e000-ffff
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switch (data & 0xc0)
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{
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case 0x00: m_rambank[1]->set_entry(1); break;
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case 0x40: m_rambank[1]->set_entry(4 + BIT(m_1e, 3)); break;
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case 0x80: m_rambank[1]->set_entry(6 + BIT(m_1e, 2)); break;
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case 0xc0: m_rambank[1]->set_entry(8); break;
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}
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}
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uint8_t qvt70_state::unk_1e_r()
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{
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uint8_t val = 0;
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val = ioport("1e")->read();
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// val = machine().rand();
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logerror("1e read: %02x\n", val);
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return val;
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}
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void qvt70_state::unk_1e_w(uint8_t data)
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{
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logerror("1e = %02x\n", data);
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m_1e = data;
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}
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void qvt70_state::unk_1f_w(uint8_t data)
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{
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logerror("1f = %02x\n", data);
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m_1f = data;
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}
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uint8_t qvt70_state::unk_32_r()
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{
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uint8_t val = 0;
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val = ioport("32")->read();
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// val = machine().rand();
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logerror("32 read: %02x\n", val);
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return val;
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}
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void qvt70_state::unk_42_w(uint8_t data)
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{
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logerror("42 = %02x\n", data);
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m_nmi_enable = bool(BIT(data, 0));
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}
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void qvt70_state::unk_60_w(uint8_t data)
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{
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logerror("60 = %02x\n", data);
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// m_nmi_enable = bool(BIT(data, 7));
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}
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void qvt70_state::rombank_w(uint8_t data)
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{
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// logerror("rombank_w: %02x\n", data);
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// 765----- unknown
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// ---43--- bankswitching
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@ -100,21 +340,35 @@ void qvt70_state::bankswitch_w(uint8_t data)
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switch (data & 0x19)
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{
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case 0x00: m_bank->set_bank(0); break;
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case 0x08: m_bank->set_bank(1); break;
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case 0x10: m_bank->set_bank(2); break;
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case 0x18: m_bank->set_bank(3); break;
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case 0x01: m_bank->set_bank(4); break;
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case 0x11: m_bank->set_bank(5); break;
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case 0x00: m_rombank->set_entry(0); break;
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case 0x08: m_rombank->set_entry(1); break;
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case 0x10: m_rombank->set_entry(2); break;
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case 0x18: m_rombank->set_entry(3); break;
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case 0x01: m_rombank->set_entry(4); break;
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case 0x11: m_rombank->set_entry(5); break;
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default:
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logerror("Unknown ROM bank: %02x\n", data);
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}
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}
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void qvt70_state::machine_start()
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{
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m_rombank->configure_entries(0, 6, memregion("maincpu")->base(), 0x8000);
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m_ram = std::make_unique<uint8_t[]>(0x12000);
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m_rambank[0]->configure_entries(0, 9, &m_ram[0], 0x2000);
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m_rambank[1]->configure_entries(0, 9, &m_ram[0], 0x2000);
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m_gfxdecode->gfx(0)->set_source(&m_ram[0x2000*7 + 0x0000]);
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m_gfxdecode->gfx(1)->set_source(&m_ram[0x2000*7 + 0x1000]);
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save_pointer(NAME(m_ram), 0x12000);
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}
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void qvt70_state::machine_reset()
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{
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m_nmi_enable = false;
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}
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void qvt70_state::qvt70(machine_config &config)
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@ -123,13 +377,20 @@ void qvt70_state::qvt70(machine_config &config)
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m_maincpu->set_addrmap(AS_PROGRAM, &qvt70_state::mem_map);
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m_maincpu->set_addrmap(AS_IO, &qvt70_state::io_map);
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ADDRESS_MAP_BANK(config, m_bank);
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m_bank->set_map(&qvt70_state::bank_map);
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m_bank->set_data_width(8);
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m_bank->set_addr_width(18);
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m_bank->set_stride(0x8000);
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screen_device &screen(SCREEN(config, "screen", SCREEN_TYPE_RASTER));
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screen.set_refresh_hz(70);
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screen.set_vblank_time(ATTOSECONDS_IN_USEC(2500)); // not accurate
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screen.set_screen_update(FUNC(qvt70_state::screen_update));
|
||||
screen.set_size(1056, 432);
|
||||
screen.set_visarea(0, 1056-1, 0, 432-1);
|
||||
screen.screen_vblank().set(FUNC(qvt70_state::vblank_w));
|
||||
|
||||
PALETTE(config, "palette").set_entries(64);
|
||||
|
||||
GFXDECODE(config, m_gfxdecode, "palette", chars);
|
||||
|
||||
Z80DART(config, "dart", 4'000'000);
|
||||
// dart irq connected to maincpu int
|
||||
|
||||
// 25-pin (dcd, rxd, txd, dtr, dsr, rts, cts and current loop)
|
||||
RS232_PORT(config, "serial1", default_rs232_devices, nullptr);
|
||||
@ -146,4 +407,4 @@ ROM_START( qvt70 )
|
||||
ROM_LOAD( "251513-04_revj.u12", 0x20000, 0x10000, CRC(3960bbd5) SHA1(9db306cef09be21ff43c081ebe11e9b46f617861) ) // 251513-04 C/S:18D0 95' REV.J (checksum matches)
|
||||
ROM_END
|
||||
|
||||
COMP( 1992, qvt70, 0, 0, qvt70, qvt70, qvt70_state, empty_init, "Qume", "QVT-70", MACHINE_IS_SKELETON )
|
||||
COMP( 1992, qvt70, 0, 0, qvt70, qvt70, qvt70_state, empty_init, "Qume", "QVT-70", MACHINE_NOT_WORKING | MACHINE_NO_SOUND )
|
||||
|
||||
Loading…
Reference in New Issue
Block a user