kl5c80a12: Internalize internal RAM and clock divider; update notes

This commit is contained in:
AJR 2020-07-25 13:42:10 -04:00
parent 36caa9da96
commit cb0ad36e92
4 changed files with 57 additions and 46 deletions

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@ -1,28 +1,35 @@
// license:BSD-3-Clause // license:BSD-3-Clause
// copyright-holders:David Haywood,AJR // copyright-holders:AJR
/*************************************************************************** /***************************************************************************
Kawasaki LSI Kawasaki Steel (Kawatetsu) KL5C80A12 CPU
KL5C80A12 CPU (KL5C80A12CFP on hng64.c)
Binary compatible with Z80, significantly faster opcode timings, operating at up to 10Mhz This is based on KC82, an MMU-enhanced version of KC80 (KL5C8400),
Timers / Counters, Parallel / Serial ports/ MMU, Interrupt Controller Kawasaki's Z80-compatible core with an internal 16-bit architecture
and significantly faster opcode timings, operating at up to 10 MHz
(CLK = XIN/2).
(is this different enough to need it's own core?) Important functional blocks:
(todo: everything except MMU) MMU
USART (KP51) (unemulated)
16-bit timer/counters (KP64, KP63) (unemulated)
16-level interrupt controller (KP69) (unemulated)
Parallel ports (KP65, KP66) (unemulated)
512-byte high-speed RAM
External bus interface unit (unemulated)
***************************************************************************/ ***************************************************************************/
#include "emu.h" #include "emu.h"
#include "kl5c80a12.h" #include "kl5c80a12.h"
DEFINE_DEVICE_TYPE(KL5C80A12, kl5c80a12_device, "kl5c80a12", "Kawasaki LSI KL5C80A12") DEFINE_DEVICE_TYPE(KL5C80A12, kl5c80a12_device, "kl5c80a12", "Kawasaki Steel KL5C80A12")
kl5c80a12_device::kl5c80a12_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock) kl5c80a12_device::kl5c80a12_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock)
: z80_device(mconfig, KL5C80A12, tag, owner, clock) : z80_device(mconfig, KL5C80A12, tag, owner, clock)
, m_program_config("program", ENDIANNESS_LITTLE, 8, 20, 0, 16, 10) , m_program_config("program", ENDIANNESS_LITTLE, 8, 20, 0, 16, 10, address_map_constructor(FUNC(kl5c80a12_device::internal_ram), this))
, m_opcodes_config("opcodes", ENDIANNESS_LITTLE, 8, 20, 0, 16, 10) , m_opcodes_config("opcodes", ENDIANNESS_LITTLE, 8, 20, 0, 16, 10, address_map_constructor(FUNC(kl5c80a12_device::internal_ram), this))
, m_io_config("io", ENDIANNESS_LITTLE, 8, 16, 0, address_map_constructor(FUNC(kl5c80a12_device::internal_io), this)) , m_io_config("io", ENDIANNESS_LITTLE, 8, 16, 0, address_map_constructor(FUNC(kl5c80a12_device::internal_io), this))
{ {
std::fill_n(&m_mmu_a[0], 4, 0); std::fill_n(&m_mmu_a[0], 4, 0);
@ -31,6 +38,16 @@ kl5c80a12_device::kl5c80a12_device(const machine_config &mconfig, const char *ta
} }
//-------------------------------------------------
// internal_ram - map for high-speed internal RAM
//-------------------------------------------------
void kl5c80a12_device::internal_ram(address_map &map)
{
map(0xffe00, 0xfffff).ram().share("ram");
}
//------------------------------------------------- //-------------------------------------------------
// internal_io - map for internal I/O registers // internal_io - map for internal I/O registers
//------------------------------------------------- //-------------------------------------------------
@ -138,7 +155,7 @@ void kl5c80a12_device::mmu_remap_pages()
{ {
int n = 4; int n = 4;
u32 base = 0xf0000; // A4 is fixed u32 base = 0xf0000; // A4 is fixed
for (int i = 0x3f; i >= 0; --i) for (u8 i = 0x3f; i != 0; --i)
{ {
while (n != 0 && m_mmu_b[n] >= i) while (n != 0 && m_mmu_b[n] >= i)
{ {

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@ -1,15 +1,8 @@
// license:BSD-3-Clause // license:BSD-3-Clause
// copyright-holders:David Haywood,AJR // copyright-holders:AJR
/*************************************************************************** /***************************************************************************
Kawasaki LSI Kawasaki Steel (Kawatetsu) KL5C80A12 CPU
KL5C80A12 CPU (KL5C80A12CFP on hng64.c)
Binary compatible with Z80, significantly faster opcode timings, operating at up to 10Mhz
Timers / Counters, Parallel / Serial ports/ MMU, Interrupt Controller
(is this different enough to need it's own core?)
(todo: everything, some code currently lives in machine/hng64_net.c but not much)
***************************************************************************/ ***************************************************************************/
@ -19,17 +12,11 @@
#pragma once #pragma once
#include "z80.h" #include "z80.h"
#include "machine/z80ctc.h"
/*************************************************************************** //**************************************************************************
DEVICE CONFIGURATION MACROS // TYPE DEFINITIONS
***************************************************************************/ //**************************************************************************
/***************************************************************************
TYPE DEFINITIONS
***************************************************************************/
class kl5c80a12_device : public z80_device class kl5c80a12_device : public z80_device
{ {
@ -49,6 +36,10 @@ protected:
virtual void device_reset() override; virtual void device_reset() override;
virtual void device_post_load() override; virtual void device_post_load() override;
// device_execute_interface overrides
virtual u64 execute_clocks_to_cycles(u64 clocks) const noexcept override { return (clocks + 2 - 1) / 2; }
virtual u64 execute_cycles_to_clocks(u64 cycles) const noexcept override { return (cycles * 2); }
// device_memory_interface overrides // device_memory_interface overrides
virtual space_config_vector memory_space_config() const override; virtual space_config_vector memory_space_config() const override;
virtual bool memory_translate(int spacenum, int intention, offs_t &address) override; virtual bool memory_translate(int spacenum, int intention, offs_t &address) override;
@ -61,7 +52,9 @@ protected:
virtual u16 arg16() override; virtual u16 arg16() override;
private: private:
void internal_ram(address_map &map);
void internal_io(address_map &map); void internal_io(address_map &map);
void mmu_remap_pages(); void mmu_remap_pages();
u8 mmu_r(offs_t offset); u8 mmu_r(offs_t offset);
void mmu_w(offs_t offset, u8 data); void mmu_w(offs_t offset, u8 data);

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@ -10023,7 +10023,7 @@ WRITE_LINE_MEMBER(ddenlovr_state::hanakanz_rtc_irq)
void ddenlovr_state::hanakanz(machine_config &config) void ddenlovr_state::hanakanz(machine_config &config)
{ {
/* basic machine hardware */ /* basic machine hardware */
KL5C80A12(config, m_maincpu, 8000000); // KL5C80A12 KL5C80A12(config, m_maincpu, 20'000'000); // KL5C80A12
m_maincpu->set_addrmap(AS_PROGRAM, &ddenlovr_state::hanakanz_map); m_maincpu->set_addrmap(AS_PROGRAM, &ddenlovr_state::hanakanz_map);
m_maincpu->set_addrmap(AS_IO, &ddenlovr_state::hanakanz_portmap); m_maincpu->set_addrmap(AS_IO, &ddenlovr_state::hanakanz_portmap);
@ -10068,7 +10068,7 @@ void ddenlovr_state::hkagerou(machine_config &config)
void ddenlovr_state::kotbinyo(machine_config &config) void ddenlovr_state::kotbinyo(machine_config &config)
{ {
/* basic machine hardware */ /* basic machine hardware */
KL5C80A12(config, m_maincpu, XTAL(20'000'000) / 2); // !! KL5C80A12CFP @ 10MHz? (actually 4 times faster than Z80) !! KL5C80A12(config, m_maincpu, XTAL(20'000'000)); // !! KL5C80A12CFP @ 10MHz? (actually 4 times faster than Z80) !!
m_maincpu->set_addrmap(AS_PROGRAM, &ddenlovr_state::hanakanz_map); m_maincpu->set_addrmap(AS_PROGRAM, &ddenlovr_state::hanakanz_map);
m_maincpu->set_addrmap(AS_IO, &ddenlovr_state::kotbinyo_portmap); m_maincpu->set_addrmap(AS_IO, &ddenlovr_state::kotbinyo_portmap);
@ -10471,7 +10471,7 @@ void ddenlovr_state::hparadis(machine_config &config)
void ddenlovr_state::jongtei(machine_config &config) void ddenlovr_state::jongtei(machine_config &config)
{ {
/* basic machine hardware */ /* basic machine hardware */
KL5C80A12(config, m_maincpu, XTAL(20'000'000) / 2); // KL5C80A12 KL5C80A12(config, m_maincpu, XTAL(20'000'000)); // KL5C80A12
m_maincpu->set_addrmap(AS_PROGRAM, &ddenlovr_state::hanakanz_map); m_maincpu->set_addrmap(AS_PROGRAM, &ddenlovr_state::hanakanz_map);
m_maincpu->set_addrmap(AS_IO, &ddenlovr_state::jongtei_portmap); m_maincpu->set_addrmap(AS_IO, &ddenlovr_state::jongtei_portmap);
@ -10685,7 +10685,7 @@ void ddenlovr_state::seljan2(machine_config &config)
void ddenlovr_state::daimyojn(machine_config &config) void ddenlovr_state::daimyojn(machine_config &config)
{ {
/* basic machine hardware */ /* basic machine hardware */
KL5C80A12(config, m_maincpu, XTAL(20'000'000) / 2); KL5C80A12(config, m_maincpu, XTAL(20'000'000));
m_maincpu->set_addrmap(AS_PROGRAM, &ddenlovr_state::hanakanz_map); m_maincpu->set_addrmap(AS_PROGRAM, &ddenlovr_state::hanakanz_map);
m_maincpu->set_addrmap(AS_IO, &ddenlovr_state::daimyojn_portmap); m_maincpu->set_addrmap(AS_IO, &ddenlovr_state::daimyojn_portmap);

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@ -38,7 +38,7 @@ Dumped games: ROMs: Video:
Sammy Kids Medal Series Sammy Kids Medal Series
CPU : Kawasaki KL5C80A120FP (Z80 Compatible High Speed Microcontroller) CPU : Kawasaki KL5C80A12CFP (Z80 Compatible High Speed Microcontroller)
Video : TAXAN KY-3211 Video : TAXAN KY-3211
Sound : OKI M9810B Sound : OKI M9810B
NVRAM : 93C46 and battery backed RAM NVRAM : 93C46 and battery backed RAM
@ -1362,7 +1362,6 @@ void sigmab98_state::animalc_map(address_map &map)
map(0x73000, 0x73021).rw(FUNC(sigmab98_state::vregs_r), FUNC(sigmab98_state::vregs_w)).share("vregs"); map(0x73000, 0x73021).rw(FUNC(sigmab98_state::vregs_r), FUNC(sigmab98_state::vregs_w)).share("vregs");
map(0x73011, 0x73011).nopw(); // IRQ Enable? Screen disable? map(0x73011, 0x73011).nopw(); // IRQ Enable? Screen disable?
map(0x73013, 0x73013).rw(FUNC(sigmab98_state::vblank_r), FUNC(sigmab98_state::vblank_w)); // IRQ Ack? map(0x73013, 0x73013).rw(FUNC(sigmab98_state::vblank_r), FUNC(sigmab98_state::vblank_w)); // IRQ Ack?
map(0xffe00, 0xfffff).ram(); // High speed internal RAM
} }
void sigmab98_state::animalc_io(address_map &map) void sigmab98_state::animalc_io(address_map &map)
@ -1393,7 +1392,6 @@ void sigmab98_state::gocowboy_map(address_map &map)
map(0x72000, 0x721ff).ram().w(m_palette, FUNC(palette_device::write8)).share("palette"); map(0x72000, 0x721ff).ram().w(m_palette, FUNC(palette_device::write8)).share("palette");
map(0x72800, 0x7287f).ram().share("vtable"); map(0x72800, 0x7287f).ram().share("vtable");
map(0x73000, 0x73021).rw(FUNC(sigmab98_state::vregs_r), FUNC(sigmab98_state::vregs_w)).share("vregs"); map(0x73000, 0x73021).rw(FUNC(sigmab98_state::vregs_r), FUNC(sigmab98_state::vregs_w)).share("vregs");
map(0xffe00, 0xfffff).ram(); // High speed internal RAM
} }
@ -1474,7 +1472,6 @@ void sigmab98_state::haekaka_map(address_map &map)
map(0x72800, 0x7287f).ram().share("vtable"); map(0x72800, 0x7287f).ram().share("vtable");
map(0x73000, 0x73021).rw(FUNC(sigmab98_state::vregs_r), FUNC(sigmab98_state::vregs_w)).share("vregs"); map(0x73000, 0x73021).rw(FUNC(sigmab98_state::vregs_r), FUNC(sigmab98_state::vregs_w)).share("vregs");
map(0x73013, 0x73013).r(FUNC(sigmab98_state::haekaka_vblank_r)); map(0x73013, 0x73013).r(FUNC(sigmab98_state::haekaka_vblank_r));
map(0xffe00, 0xfffff).ram(); // High speed internal RAM
} }
void sigmab98_state::haekaka_io(address_map &map) void sigmab98_state::haekaka_io(address_map &map)
@ -1507,7 +1504,6 @@ void sigmab98_state::itazuram_map(address_map &map)
map(0x73000, 0x73021).rw(FUNC(sigmab98_state::vregs_r), FUNC(sigmab98_state::vregs_w)).share("vregs"); map(0x73000, 0x73021).rw(FUNC(sigmab98_state::vregs_r), FUNC(sigmab98_state::vregs_w)).share("vregs");
map(0x73011, 0x73011).nopw(); // IRQ Enable? Screen disable? map(0x73011, 0x73011).nopw(); // IRQ Enable? Screen disable?
map(0x73013, 0x73013).r(FUNC(sigmab98_state::haekaka_vblank_r)).nopw(); // IRQ Ack? map(0x73013, 0x73013).r(FUNC(sigmab98_state::haekaka_vblank_r)).nopw(); // IRQ Ack?
map(0xffe00, 0xfffff).ram(); // High speed internal RAM
} }
void sigmab98_state::itazuram_io(address_map &map) void sigmab98_state::itazuram_io(address_map &map)
@ -1549,7 +1545,6 @@ void sigmab98_state::tdoboon_map(address_map &map)
map(0x72800, 0x7287f).ram().share("vtable"); map(0x72800, 0x7287f).ram().share("vtable");
map(0x73000, 0x73021).rw(FUNC(sigmab98_state::vregs_r), FUNC(sigmab98_state::vregs_w)).share("vregs"); map(0x73000, 0x73021).rw(FUNC(sigmab98_state::vregs_r), FUNC(sigmab98_state::vregs_w)).share("vregs");
map(0x73013, 0x73013).r(FUNC(sigmab98_state::haekaka_vblank_r)); map(0x73013, 0x73013).r(FUNC(sigmab98_state::haekaka_vblank_r));
map(0xffe00, 0xfffff).ram(); // High speed internal RAM
} }
void sigmab98_state::tdoboon_io(address_map &map) void sigmab98_state::tdoboon_io(address_map &map)
@ -2018,7 +2013,7 @@ TIMER_DEVICE_CALLBACK_MEMBER(sigmab98_state::sammymdl_irq)
void sigmab98_state::sammymdl(machine_config &config) void sigmab98_state::sammymdl(machine_config &config)
{ {
KL5C80A12(config, m_maincpu, XTAL(20'000'000) / 2); // !! KL5C80A120FP @ 10MHz? (actually 4 times faster than Z80) !! KL5C80A12(config, m_maincpu, XTAL(20'000'000)); // !! KL5C80A12CFP @ 10MHz? (actually 4 times faster than Z80) !!
m_maincpu->set_addrmap(AS_PROGRAM, &sigmab98_state::animalc_map); m_maincpu->set_addrmap(AS_PROGRAM, &sigmab98_state::animalc_map);
m_maincpu->set_addrmap(AS_IO, &sigmab98_state::animalc_io); m_maincpu->set_addrmap(AS_IO, &sigmab98_state::animalc_io);
@ -2535,15 +2530,16 @@ void lufykzku_state::init_lufykzku()
CPU: CPU:
KAWASAKI KL5C80A120FP (@U1) - Z80 Compatible High Speed Microcontroller KAWASAKI KL5C80A12CFP (@U1) - Z80 Compatible High Speed Microcontroller
XTAL 20 MHz (@X1) XTAL 20 MHz (@X1)
MX29F040TC-12 VM1211L01 (@U2) - 4M-bit [512kx8] CMOS Equal Sector Flash Memory MX29F040TC-12 VM1211L01 (@U2) - 4M-bit [512kx8] CMOS Equal Sector Flash Memory
BSI BS62LV256SC-70 (@U4) - Very Low Power/Voltage CMOS SRAM 32K X 8 bit BSI BS62LV256SC-70 (@U4) - Very Low Power/Voltage CMOS SRAM 32K X 8 bit
(or Toshiba TC55257DFL-70L)
Video: Video:
TAXAN KY-3211 ? (@U17) TAXAN KY-3211 (@U17)
M548262-60 (@U18) - 262144-Word x 8-Bit Multiport DRAM OKI M548262-60 (@U18) - 262144-Word x 8-Bit Multiport DRAM
XTAL 27 MHz (@X3) XTAL 27 MHz (@X3)
Sound: Sound:
@ -2556,13 +2552,18 @@ void lufykzku_state::init_lufykzku()
Other: Other:
Xilinx XC9536 VM1212F01 (@U5) - In-System Programmable CPLD Xilinx XC9536 VM1212F01 (@U5) - In-System Programmable CPLD
MX29F0??C (@U3) - Empty 32 Pin ROM Socket MX29F0?TC (@U3) - Empty 32 Pin DIP Socket
M5295A (@U8) - Watchdog Timer (Near CUT-DEBUG MODE Jumper) M5295A (@U8) - Watchdog Timer (Near CUT-DEBUG MODE Jumper)
M93C46MN6T (@U11?) - Serial EEPROM M93C46MN6T (@U6) - Serial EEPROM
RTC8564 (@U7) - not populated
SN75C1168 (@U10) - Dual RS-422 Transceiver
Cell Battery (@BAT) Cell Battery (@BAT)
25 Pin Edge Connector 25 Pin Edge Connector
56 Pin Cartridge Connector 56 Pin Cartridge Connector
6 Pin Connector 6 Pin Connector - +5V (1), GND (2), TCLK (3), TDO (4), TDI (5), TMS (6)
On Go Go Cowboy, U2 and U10 are unpopulated, but U3 is occupied by a
ST M27C4001-10F1 EPROM.
***************************************************************************/ ***************************************************************************/