From cb1023eb008a8515ffa17856f48f8a07f42a7871 Mon Sep 17 00:00:00 2001 From: angelosa Date: Fri, 30 Dec 2016 02:46:44 +0100 Subject: [PATCH] CPU IRQ trigger & fix regression --- src/mame/machine/namco_c148.cpp | 37 ++++++++++++++++++++++++--------- src/mame/machine/namco_c148.h | 16 ++++++++++++-- 2 files changed, 41 insertions(+), 12 deletions(-) diff --git a/src/mame/machine/namco_c148.cpp b/src/mame/machine/namco_c148.cpp index e66d54721f7..7fd013333f1 100644 --- a/src/mame/machine/namco_c148.cpp +++ b/src/mame/machine/namco_c148.cpp @@ -68,14 +68,15 @@ DEVICE_ADDRESS_MAP_START( map, 16, namco_c148_device ) AM_RANGE(0x0c000, 0x0dfff) AM_READWRITE8(sci_irq_level_r,sci_irq_level_w,0x00ff) // SCIRQ lv AM_RANGE(0x0e000, 0x0ffff) AM_READWRITE8(vblank_irq_level_r,vblank_irq_level_w,0x00ff) // VBlank IRQ lv + AM_RANGE(0x10000, 0x11fff) AM_WRITE(cpu_irq_assert_w) AM_RANGE(0x16000, 0x17fff) AM_READWRITE(cpu_irq_ack_r, cpu_irq_ack_w) // CPUIRQ ack AM_RANGE(0x18000, 0x19fff) AM_READWRITE(ex_irq_ack_r, ex_irq_ack_w) // EXIRQ ack AM_RANGE(0x1a000, 0x1bfff) AM_READWRITE(pos_irq_ack_r, pos_irq_ack_w) // POSIRQ ack AM_RANGE(0x1c000, 0x1dfff) AM_READWRITE(sci_irq_ack_r, sci_irq_ack_w) // SCIRQ ack AM_RANGE(0x1e000, 0x1ffff) AM_READWRITE(vblank_irq_ack_r, vblank_irq_ack_w) // VBlank IRQ ack -// AM_RANGE(0x20000, 0x21fff) // EEPROM ready status (*) - AM_RANGE(0x22000, 0x23fff) AM_WRITE8(ext2_w,0x00ff) // sound CPU reset (*) -// AM_RANGE(0x24000, 0x25fff) // slave & i/o reset (*) + AM_RANGE(0x20000, 0x21fff) AM_READ8(ext_r,0x00ff) // EEPROM ready status (*) + AM_RANGE(0x22000, 0x23fff) AM_WRITE8(ext1_w,0x00ff) // sound CPU reset (*) + AM_RANGE(0x24000, 0x25fff) AM_WRITE8(ext2_w,0x00ff) // slave & i/o reset (*) AM_RANGE(0x26000, 0x27fff) AM_NOP // watchdog ADDRESS_MAP_END @@ -88,6 +89,8 @@ ADDRESS_MAP_END void namco_c148_device::device_start() { m_hostcpu = machine().device(m_hostcpu_tag); + m_linked_c148 = machine().device(m_linked_c148_tag); + // TODO: link to SCI, EX and the screen device controller devices } @@ -116,11 +119,8 @@ inline void namco_c148_device::flush_irq_acks() // If writing an IRQ priority register, clear any pending IRQs. // Dirt Fox and Winning Run require this behaviour // TODO: literal behaviour, Winning Run GPU doesn't seem to care about irq ack ports? - m_hostcpu->set_input_line(m_irqlevel.pos, CLEAR_LINE); - m_hostcpu->set_input_line(m_irqlevel.vblank, CLEAR_LINE); - m_hostcpu->set_input_line(m_irqlevel.cpu, CLEAR_LINE); - m_hostcpu->set_input_line(m_irqlevel.ex, CLEAR_LINE); - m_hostcpu->set_input_line(m_irqlevel.sci, CLEAR_LINE); + for(int i=0;i<8;i++) + m_hostcpu->set_input_line(i,CLEAR_LINE); } WRITE8_MEMBER( namco_c148_device::pos_irq_level_w ) { m_irqlevel.pos = data & 7; flush_irq_acks(); } @@ -142,12 +142,28 @@ WRITE16_MEMBER( namco_c148_device::ex_irq_ack_w ) { m_hostcpu->set_input_line( WRITE16_MEMBER( namco_c148_device::sci_irq_ack_w ) { m_hostcpu->set_input_line(m_irqlevel.sci, CLEAR_LINE); } //************************************************************************** -// IRQ section +// Comm ports //************************************************************************** +READ8_MEMBER( namco_c148_device::ext_r ) +{ + return 0xff; // TODO: bit 0 EEPROM bit +} + +WRITE8_MEMBER( namco_c148_device::ext1_w ) +{ + +} + WRITE8_MEMBER( namco_c148_device::ext2_w ) { - // TODO: bit 1 might be irq enable? + // TODO: bit 1/2 in Winning Run GPU might be irq enable? +} + +WRITE16_MEMBER( namco_c148_device::cpu_irq_assert_w) +{ + // TODO: Starblade relies on this for showing large polygons, is it the right place? + m_linked_c148->cpu_irq_trigger(); } READ8_MEMBER( namco_c148_device::ext_posirq_line_r ) @@ -160,6 +176,7 @@ WRITE8_MEMBER( namco_c148_device::ext_posirq_line_w ) m_posirq_line = data; } + //************************************************************************** // GETTERS/SETTERS //************************************************************************** diff --git a/src/mame/machine/namco_c148.h b/src/mame/machine/namco_c148.h index 6e636e1fd4c..9256136d69f 100644 --- a/src/mame/machine/namco_c148.h +++ b/src/mame/machine/namco_c148.h @@ -42,6 +42,13 @@ public: dev.m_hostcpu_master = is_master; } + static void link_c148_device(device_t &device, const char *tag) + { + namco_c148_device &dev = downcast(device); + + dev.m_linked_c148_tag = tag; + } + DECLARE_READ8_MEMBER( vblank_irq_level_r ); DECLARE_WRITE8_MEMBER( vblank_irq_level_w ); DECLARE_READ16_MEMBER( vblank_irq_ack_r ); @@ -69,23 +76,28 @@ public: DECLARE_READ8_MEMBER( ext_posirq_line_r ); DECLARE_WRITE8_MEMBER( ext_posirq_line_w ); + DECLARE_WRITE16_MEMBER( cpu_irq_assert_w ); + DECLARE_READ8_MEMBER( ext_r ); + DECLARE_WRITE8_MEMBER( ext1_w ); DECLARE_WRITE8_MEMBER( ext2_w ); void vblank_irq_trigger(); void pos_irq_trigger(); - void cpu_irq_trigger(); void ex_irq_trigger(); void sci_irq_trigger(); uint8_t get_posirq_line(); protected: + void cpu_irq_trigger(); // device-level overrides // virtual void device_validity_check(validity_checker &valid) const; virtual void device_start() override; virtual void device_reset() override; private: - cpu_device *m_hostcpu; /**< reference to the host cpu */ + cpu_device *m_hostcpu; /**< reference to the host cpu */ + namco_c148_device *m_linked_c148; /**< reference to linked master/slave c148 */ const char *m_hostcpu_tag; /**< host cpu tag name */ + const char *m_linked_c148_tag; /**< other c148 tag name */ bool m_hostcpu_master; /**< define if host cpu is master */ struct{ uint8_t cpu;