mirror of
https://github.com/holub/mame
synced 2025-06-24 05:17:04 +03:00
nintendo/cham24.cpp: Added save state support and cleaned up code. (#10670)
Also cleaned up sprite RAM DMA trigger trampolines in all NES-like drivers.
This commit is contained in:
0kmg
GitHub
parent
003e5b4879
commit
cb5379c63e
@ -29,7 +29,7 @@ PCB Layout
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| |NTA0002| |
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| |(QFP80)| 24-1.U1 |
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| -------- |
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| 2003 ----------- |
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| ULN2003A ----------- |
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| |LATTICE | |
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| DSW1 |PLSI 1016| |
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|J |(PLCC44) | 24-2.U2 |
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@ -38,8 +38,8 @@ PCB Layout
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|M SW1 21.4771MHz |
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|A |
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| GW6582 LS02 |
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| |-----------| 4040 |
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| 74HC245 |Philips | 4040 |
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| |-----------| MC14040BCP |
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| 74HC245 |Philips | MC14040BCP |
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| |SAA71111AH2| |
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| |20505650 | |
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| |bP0219 | 24-3.U3 |
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@ -71,12 +71,13 @@ class cham24_state : public driver_device
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{
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public:
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cham24_state(const machine_config &mconfig, device_type type, const char *tag)
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: driver_device(mconfig, type, tag),
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m_maincpu(*this, "maincpu"),
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m_ppu(*this, "ppu"),
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m_nt_page(*this, "nt_page%u", 0U),
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m_prg_banks(*this, "prg%u", 0U),
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m_chr_bank(*this, "chr")
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: driver_device(mconfig, type, tag)
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, m_maincpu(*this, "maincpu")
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, m_ppu(*this, "ppu")
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, m_nt_page(*this, "nt_page%u", 0U)
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, m_prg_banks(*this, "prg%u", 0U)
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, m_chr_bank(*this, "chr")
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, m_in(*this, "P%u", 1U)
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{ }
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void cham24(machine_config &config);
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@ -93,18 +94,16 @@ private:
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required_memory_bank_array<2> m_prg_banks;
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required_memory_bank m_chr_bank;
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uint8_t m_prg_chunks;
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required_ioport_array<2> m_in;
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std::unique_ptr<uint8_t[]> m_nt_ram;
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uint32_t m_in_0;
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uint32_t m_in_1;
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uint32_t m_in_0_shift;
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uint32_t m_in_1_shift;
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void sprite_dma_w(address_space &space, uint8_t data);
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uint8_t cham24_IN0_r();
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void cham24_IN0_w(uint8_t data);
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uint8_t cham24_IN1_r();
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void cham24_mapper_w(offs_t offset, uint8_t data);
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std::unique_ptr<u8 []> m_nt_ram;
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u8 m_prg_chunks;
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u8 m_input_latch[2];
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u8 m_input_strobe;
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template <u8 Which> u8 cham24_in_r();
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void cham24_in0_w(u8 data);
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void cham24_mapper_w(offs_t offset, u8 data);
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void cham24_set_mirroring(int mirroring);
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void cham24_map(address_map &map);
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void cham24_ppu_map(address_map &map);
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@ -114,61 +113,46 @@ private:
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void cham24_state::cham24_set_mirroring(int mirroring)
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{
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switch (mirroring)
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{
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case PPU_MIRROR_HORZ:
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for (int i = 0; i < 4; i++)
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m_nt_page[i]->set_entry(BIT(i, 1));
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break;
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case PPU_MIRROR_VERT:
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default:
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for (int i = 0; i < 4; i++)
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m_nt_page[i]->set_entry(i & 1);
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break;
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}
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int bit = mirroring == PPU_MIRROR_HORZ;
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for (int i = 0; i < 4; i++)
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m_nt_page[i]->set_entry(BIT(i, bit));
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}
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void cham24_state::sprite_dma_w(address_space &space, uint8_t data)
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template <u8 Which>
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u8 cham24_state::cham24_in_r()
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{
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int source = (data & 7);
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m_ppu->spriteram_dma(space, source);
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if (m_input_strobe)
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m_input_latch[Which] = m_in[Which]->read();
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u8 ret = 0x40;
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ret |= m_input_latch[Which] & 1;
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if (!machine().side_effects_disabled())
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m_input_latch[Which] >>= 1;
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return ret;
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}
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uint8_t cham24_state::cham24_IN0_r()
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{
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return ((m_in_0 >> m_in_0_shift++) & 0x01) | 0x40;
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}
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void cham24_state::cham24_IN0_w(uint8_t data)
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void cham24_state::cham24_in0_w(u8 data)
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{
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if (data & 0xfe)
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{
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//logerror("Unhandled cham24_IN0_w write: data = %02X\n", data);
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//logerror("Unhandled cham24_in0_w write: data = %02X\n", data);
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}
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if (data & 0x01)
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{
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return;
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}
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m_in_0_shift = 0;
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m_in_1_shift = 0;
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m_in_0 = ioport("P1")->read();
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m_in_1 = ioport("P2")->read();
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if (m_input_strobe & ~data & 1)
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for (int i = 0; i < 2; i++)
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m_input_latch[i] = m_in[i]->read();
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m_input_strobe = data & 1;
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}
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uint8_t cham24_state::cham24_IN1_r()
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{
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return ((m_in_1 >> m_in_1_shift++) & 0x01) | 0x40;
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}
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void cham24_state::cham24_mapper_w(offs_t offset, uint8_t data)
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void cham24_state::cham24_mapper_w(offs_t offset, u8 data)
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{
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// switch PRG bank
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uint8_t prg_bank = BIT(offset, 6, 6);
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uint8_t prg_mode = !BIT(offset, 12);
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u8 prg_bank = BIT(offset, 6, 6);
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u8 prg_mode = !BIT(offset, 12);
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m_prg_banks[0]->set_entry(prg_bank & ~prg_mode);
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m_prg_banks[1]->set_entry(prg_bank | prg_mode);
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@ -181,11 +165,11 @@ void cham24_state::cham24_mapper_w(offs_t offset, uint8_t data)
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void cham24_state::cham24_map(address_map &map)
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{
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map(0x0000, 0x07ff).ram(); /* NES RAM */
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map(0x0000, 0x07ff).mirror(0x1800).ram(); // NES RAM
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map(0x2000, 0x3fff).rw(m_ppu, FUNC(ppu2c0x_device::read), FUNC(ppu2c0x_device::write));
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map(0x4014, 0x4014).w(FUNC(cham24_state::sprite_dma_w));
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map(0x4016, 0x4016).rw(FUNC(cham24_state::cham24_IN0_r), FUNC(cham24_state::cham24_IN0_w)); /* IN0 - input port 1 */
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map(0x4017, 0x4017).r(FUNC(cham24_state::cham24_IN1_r)); /* IN1 - input port 2 / PSG second control register */
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map(0x4014, 0x4014).w(m_ppu, FUNC(ppu2c0x_device::spriteram_dma));
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map(0x4016, 0x4016).rw(FUNC(cham24_state::cham24_in_r<0>), FUNC(cham24_state::cham24_in0_w)); // IN0 - input port 1
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map(0x4017, 0x4017).r(FUNC(cham24_state::cham24_in_r<1>)); // IN1 - input port 2 / PSG second control register
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map(0x8000, 0xbfff).bankr(m_prg_banks[0]).w(FUNC(cham24_state::cham24_mapper_w));
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map(0xc000, 0xffff).bankr(m_prg_banks[1]).w(FUNC(cham24_state::cham24_mapper_w));
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}
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@ -201,20 +185,20 @@ void cham24_state::cham24_ppu_map(address_map &map)
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}
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static INPUT_PORTS_START( cham24 )
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PORT_START("P1") /* IN0 */
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PORT_START("P1") // IN0
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PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_BUTTON2 ) PORT_PLAYER(1)
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PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_BUTTON1 ) PORT_PLAYER(1)
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PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_BUTTON3 ) PORT_PLAYER(1) /* Select */
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PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_BUTTON3 ) PORT_PLAYER(1) // Select
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PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_START1 )
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PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_JOYSTICK_UP ) PORT_PLAYER(1)
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PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_JOYSTICK_DOWN ) PORT_PLAYER(1)
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PORT_BIT( 0x40, IP_ACTIVE_HIGH, IPT_JOYSTICK_LEFT ) PORT_PLAYER(1)
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PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_JOYSTICK_RIGHT ) PORT_PLAYER(1)
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PORT_START("P2") /* IN1 */
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PORT_START("P2") // IN1
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PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_BUTTON2 ) PORT_PLAYER(2)
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PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_BUTTON1 ) PORT_PLAYER(2)
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PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_BUTTON3 ) PORT_PLAYER(2) /* Select */
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PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_BUTTON3 ) PORT_PLAYER(2) // Select
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PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_START2 )
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PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_JOYSTICK_UP ) PORT_PLAYER(2)
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PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_JOYSTICK_DOWN ) PORT_PLAYER(2)
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@ -226,8 +210,8 @@ INPUT_PORTS_END
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void cham24_state::machine_start()
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{
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m_nt_ram = std::make_unique<u8[]>(0x800);
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for (int i = 0; i < 4; i++)
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m_nt_page[i]->configure_entries(0, 2, m_nt_ram.get(), 0x400);
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for (auto &page : m_nt_page)
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page->configure_entries(0, 2, m_nt_ram.get(), 0x400);
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// set up code banking to be done in 16K chunks
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m_prg_chunks = memregion("user1")->bytes() / 0x4000;
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@ -236,6 +220,10 @@ void cham24_state::machine_start()
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// gfx banking always done in 8K chunks
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m_chr_bank->configure_entries(0, memregion("gfx1")->bytes() / 0x2000, memregion("gfx1")->base(), 0x2000);
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save_item(NAME(m_input_latch));
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save_item(NAME(m_input_strobe));
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save_pointer(NAME(m_nt_ram), 0x800);
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}
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void cham24_state::machine_reset()
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@ -251,23 +239,23 @@ void cham24_state::machine_reset()
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void cham24_state::cham24(machine_config &config)
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{
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/* basic machine hardware */
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// basic machine hardware
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RP2A03G(config, m_maincpu, NTSC_APU_CLOCK);
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m_maincpu->set_addrmap(AS_PROGRAM, &cham24_state::cham24_map);
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/* video hardware */
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// video hardware
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screen_device &screen(SCREEN(config, "screen", SCREEN_TYPE_RASTER));
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screen.set_refresh_hz(60);
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screen.set_size(32*8, 262);
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screen.set_visarea(0*8, 32*8-1, 0*8, 30*8-1);
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screen.set_screen_update("ppu", FUNC(ppu2c0x_device::screen_update));
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screen.set_screen_update(m_ppu, FUNC(ppu2c0x_device::screen_update));
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PPU_2C02(config, m_ppu);
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m_ppu->set_addrmap(0, &cham24_state::cham24_ppu_map);
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m_ppu->set_cpu_tag(m_maincpu);
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m_ppu->int_callback().set_inputline(m_maincpu, INPUT_LINE_NMI);
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/* sound hardware */
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// sound hardware
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SPEAKER(config, "mono").front_center();
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m_maincpu->add_route(ALL_OUTPUTS, "mono", 0.50);
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}
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@ -291,4 +279,4 @@ ROM_END
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} // Anonymous namespace
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GAME( 2002, cham24, 0, cham24, cham24, cham24_state, empty_init, ROT0, "bootleg", "Chameleon 24", MACHINE_NOT_WORKING )
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GAME( 2002, cham24, 0, cham24, cham24, cham24_state, empty_init, ROT0, "bootleg", "Chameleon 24", MACHINE_NOT_WORKING | MACHINE_SUPPORTS_SAVE )
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@ -126,7 +126,6 @@ private:
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uint8_t m_money_reg = 0;
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void set_mirroring(int mirroring);
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void sprite_dma_w(address_space &space, uint8_t data);
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uint8_t famibox_IN0_r();
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uint8_t famibox_IN1_r();
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void famibox_IN0_w(uint8_t data);
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@ -170,19 +169,6 @@ void famibox_state::set_mirroring(int mirroring)
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}
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}
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/******************************************************
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NES interface
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*******************************************************/
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void famibox_state::sprite_dma_w(address_space &space, uint8_t data)
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{
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int source = data & 7;
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m_ppu->spriteram_dma(space, source);
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}
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/******************************************************
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Inputs
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@ -396,7 +382,7 @@ void famibox_state::famibox_map(address_map &map)
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{
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map(0x0000, 0x1fff).ram();
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map(0x2000, 0x3fff).rw(m_ppu, FUNC(ppu2c0x_device::read), FUNC(ppu2c0x_device::write));
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map(0x4014, 0x4014).w(FUNC(famibox_state::sprite_dma_w));
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map(0x4014, 0x4014).w(m_ppu, FUNC(ppu2c0x_device::spriteram_dma));
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map(0x4016, 0x4016).rw(FUNC(famibox_state::famibox_IN0_r), FUNC(famibox_state::famibox_IN0_w)); // IN0 - input port 1
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map(0x4017, 0x4017).r(FUNC(famibox_state::famibox_IN1_r)); // IN1 - input port 2 / PSG second control register
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map(0x5000, 0x5fff).rw(FUNC(famibox_state::famibox_system_r), FUNC(famibox_state::famibox_system_w));
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@ -191,7 +191,6 @@ private:
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uint8_t m_supergm3_prg_bank;
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uint8_t m_supergm3_chr_bank;
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void sprite_dma_w(address_space &space, uint8_t data);
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uint8_t multigam_IN0_r();
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void multigam_IN0_w(uint8_t data);
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uint8_t multigam_IN1_r();
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@ -281,18 +280,6 @@ void multigam_state::set_videoram_bank( int start, int count, int bank, int bank
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}
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}
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/******************************************************
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NES interface
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*******************************************************/
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void multigam_state::sprite_dma_w(address_space &space, uint8_t data)
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{
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int source = (data & 7);
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m_ppu->spriteram_dma(space, source);
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}
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/******************************************************
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@ -395,7 +382,7 @@ void multigam_state::multigam_map(address_map &map)
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map(0x0000, 0x07ff).ram(); /* NES RAM */
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map(0x0800, 0x0fff).ram(); /* additional RAM */
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map(0x2000, 0x3fff).rw(m_ppu, FUNC(ppu2c0x_device::read), FUNC(ppu2c0x_device::write));
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map(0x4014, 0x4014).w(FUNC(multigam_state::sprite_dma_w));
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map(0x4014, 0x4014).w(m_ppu, FUNC(ppu2c0x_device::spriteram_dma));
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map(0x4016, 0x4016).rw(FUNC(multigam_state::multigam_IN0_r), FUNC(multigam_state::multigam_IN0_w)); /* IN0 - input port 1 */
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map(0x4017, 0x4017).r(FUNC(multigam_state::multigam_IN1_r)); /* IN1 - input port 2 / PSG second control register */
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map(0x5000, 0x5ffe).rom();
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@ -414,7 +401,7 @@ void multigam_state::multigmt_map(address_map &map)
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map(0x2000, 0x3fff).rw(m_ppu, FUNC(ppu2c0x_device::read), FUNC(ppu2c0x_device::write));
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map(0x3000, 0x3000).w(FUNC(multigam_state::multigam_switch_prg_rom));
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map(0x3fff, 0x3fff).w(FUNC(multigam_state::multigam_switch_gfx_rom));
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map(0x4014, 0x4014).w(FUNC(multigam_state::sprite_dma_w));
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map(0x4014, 0x4014).w(m_ppu, FUNC(ppu2c0x_device::spriteram_dma));
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map(0x4016, 0x4016).rw(FUNC(multigam_state::multigam_IN0_r), FUNC(multigam_state::multigam_IN0_w)); /* IN0 - input port 1 */
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map(0x4017, 0x4017).r(FUNC(multigam_state::multigam_IN1_r)); /* IN1 - input port 2 / PSG second control register */
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map(0x5000, 0x5ffe).rom();
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@ -686,7 +673,7 @@ void multigam_state::multigm3_map(address_map &map)
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map(0x0000, 0x07ff).ram(); /* NES RAM */
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map(0x0800, 0x0fff).ram(); /* additional RAM */
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map(0x2000, 0x3fff).rw(m_ppu, FUNC(ppu2c0x_device::read), FUNC(ppu2c0x_device::write));
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map(0x4014, 0x4014).w(FUNC(multigam_state::sprite_dma_w));
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map(0x4014, 0x4014).w(m_ppu, FUNC(ppu2c0x_device::spriteram_dma));
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map(0x4016, 0x4016).rw(FUNC(multigam_state::multigam_IN0_r), FUNC(multigam_state::multigam_IN0_w)); /* IN0 - input port 1 */
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map(0x4017, 0x4017).r(FUNC(multigam_state::multigam_IN1_r)); /* IN1 - input port 2 / PSG second control register */
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map(0x5001, 0x5001).w(FUNC(multigam_state::multigm3_switch_prg_rom));
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@ -980,7 +967,7 @@ void multigam_state::supergm3_map(address_map &map)
|
||||
map(0x0000, 0x07ff).ram(); /* NES RAM */
|
||||
map(0x0800, 0x0fff).ram(); /* additional RAM */
|
||||
map(0x2000, 0x3fff).rw(m_ppu, FUNC(ppu2c0x_device::read), FUNC(ppu2c0x_device::write));
|
||||
map(0x4014, 0x4014).w(FUNC(multigam_state::sprite_dma_w));
|
||||
map(0x4014, 0x4014).w(m_ppu, FUNC(ppu2c0x_device::spriteram_dma));
|
||||
map(0x4016, 0x4016).rw(FUNC(multigam_state::multigam_IN0_r), FUNC(multigam_state::multigam_IN0_w)); /* IN0 - input port 1 */
|
||||
map(0x4017, 0x4017).r(FUNC(multigam_state::multigam_IN1_r)); /* IN1 - input port 2 / PSG second control register */
|
||||
map(0x4fff, 0x4fff).portr("IN0");
|
||||
|
||||
@ -20,16 +20,11 @@
|
||||
#include "speaker.h"
|
||||
|
||||
|
||||
void nes_state::nes_vh_sprite_dma_w(address_space &space, uint8_t data)
|
||||
{
|
||||
m_ppu->spriteram_dma(space, data);
|
||||
}
|
||||
|
||||
void nes_state::nes_map(address_map &map)
|
||||
{
|
||||
map(0x0000, 0x07ff).ram().mirror(0x1800).share("mainram"); // RAM
|
||||
map(0x2000, 0x3fff).rw(m_ppu, FUNC(ppu2c0x_device::read), FUNC(ppu2c0x_device::write)); // PPU registers
|
||||
map(0x4014, 0x4014).w(FUNC(nes_state::nes_vh_sprite_dma_w)); // stupid address space hole
|
||||
map(0x4014, 0x4014).w(m_ppu, FUNC(ppu2c0x_device::spriteram_dma)); // stupid address space hole
|
||||
map(0x4016, 0x4016).rw(FUNC(nes_state::nes_in0_r), FUNC(nes_state::nes_in0_w)); // IN0 - input port 1
|
||||
map(0x4017, 0x4017).r(FUNC(nes_state::nes_in1_r)); // IN1 - input port 2
|
||||
// 0x4100-0x5fff -> LOW HANDLER defined on a pcb base
|
||||
|
||||
@ -64,7 +64,6 @@ public:
|
||||
uint8_t fc_in0_r();
|
||||
uint8_t fc_in1_r();
|
||||
void fc_in0_w(uint8_t data);
|
||||
void nes_vh_sprite_dma_w(address_space &space, uint8_t data);
|
||||
virtual void machine_start() override;
|
||||
virtual void machine_reset() override;
|
||||
virtual void video_start() override;
|
||||
|
||||
@ -182,7 +182,7 @@ void nes_arcade_bl_state::nes_cpu_map(address_map &map)
|
||||
{
|
||||
map(0x0000, 0x07ff).mirror(0x1800).ram();
|
||||
map(0x2000, 0x3fff).rw(m_ppu, FUNC(ppu2c0x_device::read), FUNC(ppu2c0x_device::write));
|
||||
map(0x4014, 0x4014).lw8(NAME([this] (address_space &space, u8 data) { m_ppu->spriteram_dma(space, data); }));
|
||||
map(0x4014, 0x4014).w(m_ppu, FUNC(ppu2c0x_device::spriteram_dma));
|
||||
map(0x4016, 0x4016).rw(FUNC(nes_arcade_bl_state::in_r<0>), FUNC(nes_arcade_bl_state::in0_w)); // IN0 - input port 1
|
||||
map(0x4017, 0x4017).r(FUNC(nes_arcade_bl_state::in_r<1>)); // IN1 - input port 2 / PSG second control register
|
||||
|
||||
|
||||
@ -35,8 +35,6 @@ protected:
|
||||
virtual void machine_reset() override;
|
||||
virtual void video_start() override;
|
||||
|
||||
void sprite_dma_w(address_space &space, uint8_t data);
|
||||
|
||||
virtual uint8_t in0_r();
|
||||
virtual uint8_t in1_r();
|
||||
virtual void in0_w(uint8_t data);
|
||||
@ -246,12 +244,6 @@ private:
|
||||
};
|
||||
|
||||
|
||||
void nes_clone_state::sprite_dma_w(address_space &space, uint8_t data)
|
||||
{
|
||||
int source = (data & 7);
|
||||
m_ppu->spriteram_dma(space, source);
|
||||
}
|
||||
|
||||
// Standard NES style inputs (not using bus device as there are no real NES controller ports etc. these are all-in-one units and can be custom
|
||||
uint8_t nes_clone_state::in0_r()
|
||||
{
|
||||
@ -292,10 +284,10 @@ void nes_clone_state::nes_clone_basemap(address_map& map)
|
||||
map(0x0000, 0x07ff).ram();
|
||||
map(0x2000, 0x3fff).rw(m_ppu, FUNC(ppu2c0x_device::read), FUNC(ppu2c0x_device::write));
|
||||
|
||||
map(0x4014, 0x4014).w(m_ppu, FUNC(ppu2c0x_device::spriteram_dma));
|
||||
|
||||
map(0x4016, 0x4016).rw(FUNC(nes_clone_state::in0_r), FUNC(nes_clone_state::in0_w));
|
||||
map(0x4017, 0x4017).r(FUNC(nes_clone_state::in1_r));
|
||||
|
||||
map(0x4014, 0x4014).w(FUNC(nes_clone_state::sprite_dma_w));
|
||||
}
|
||||
|
||||
void nes_clone_state::nes_clone_map(address_map& map)
|
||||
|
||||
@ -187,7 +187,7 @@ void m8_state::m8_map(address_map &map)
|
||||
{
|
||||
map(0x0000, 0x07ff).mirror(0x1800).ram();
|
||||
map(0x2000, 0x3fff).rw(m_ppu, FUNC(ppu2c0x_device::read), FUNC(ppu2c0x_device::write));
|
||||
map(0x4014, 0x4014).lw8(NAME([this] (address_space &space, u8 data) { m_ppu->spriteram_dma(space, data); }));
|
||||
map(0x4014, 0x4014).w(m_ppu, FUNC(ppu2c0x_device::spriteram_dma));
|
||||
map(0x4016, 0x4016).rw(FUNC(m8_state::m8_in0_r), FUNC(m8_state::m8_in0_w)); // IN0 - input port 1
|
||||
map(0x4017, 0x4017).r(FUNC(m8_state::m8_in1_r)); // IN1 - input port 2 / PSG second control register
|
||||
|
||||
|
||||
@ -131,7 +131,7 @@ void m82_state::m82_map(address_map &map)
|
||||
{
|
||||
map(0x0000, 0x07ff).mirror(0x1800).ram();
|
||||
map(0x2000, 0x3fff).rw(m_ppu, FUNC(ppu2c0x_device::read), FUNC(ppu2c0x_device::write));
|
||||
map(0x4014, 0x4014).lw8(NAME([this] (address_space &space, u8 data) { m_ppu->spriteram_dma(space, data); }));
|
||||
map(0x4014, 0x4014).w(m_ppu, FUNC(ppu2c0x_device::spriteram_dma));
|
||||
map(0x4016, 0x4016).rw(FUNC(m82_state::m82_in0_r), FUNC(m82_state::m82_in0_w)); // IN0 - input port 1
|
||||
map(0x4017, 0x4017).r(FUNC(m82_state::m82_in1_r)); // IN1 - input port 2 / PSG second control register
|
||||
|
||||
|
||||
@ -55,8 +55,6 @@ protected:
|
||||
virtual void machine_reset() override;
|
||||
virtual void video_start() override;
|
||||
|
||||
void sprite_dma_w(address_space &space, uint8_t data);
|
||||
|
||||
virtual void io_w(uint8_t data);
|
||||
virtual void extio_w(uint8_t data);
|
||||
bool m_isbanked;
|
||||
@ -179,11 +177,6 @@ void nes_sh6578_state::bank_w(int bank, uint16_t offset, uint8_t data)
|
||||
m_fullrom->write8(address, data);
|
||||
}
|
||||
|
||||
void nes_sh6578_state::sprite_dma_w(address_space &space, uint8_t data)
|
||||
{
|
||||
m_ppu->spriteram_dma(space, data);
|
||||
}
|
||||
|
||||
uint8_t nes_sh6578_state::bankswitch_r(offs_t offset)
|
||||
{
|
||||
return m_bankswitch[offset];
|
||||
@ -469,7 +462,7 @@ void nes_sh6578_state::nes_sh6578_map(address_map& map)
|
||||
map(0x2040, 0x207f).rw(m_ppu, FUNC(ppu_sh6578_device::palette_read), FUNC(ppu_sh6578_device::palette_write));
|
||||
|
||||
map(0x4000, 0x4017).w(m_apu, FUNC(nesapu_device::write));
|
||||
map(0x4014, 0x4014).w(FUNC(nes_sh6578_state::sprite_dma_w));
|
||||
map(0x4014, 0x4014).w(m_ppu, FUNC(ppu_sh6578_device::spriteram_dma));
|
||||
map(0x4015, 0x4015).r(m_apu, FUNC(nesapu_device::status_r));
|
||||
map(0x4016, 0x4016).rw(FUNC(nes_sh6578_state::io0_r), FUNC(nes_sh6578_state::io_w));
|
||||
map(0x4017, 0x4017).r(FUNC(nes_sh6578_state::io1_r));
|
||||
|
||||
@ -367,7 +367,6 @@ private:
|
||||
DECLARE_WRITE_LINE_MEMBER(up8w_w);
|
||||
u8 ram_8w_r(offs_t offset);
|
||||
void ram_8w_w(offs_t offset, u8 data);
|
||||
void sprite_dma_w(address_space &space, u8 data);
|
||||
void time_w(offs_t offset, u8 data);
|
||||
DECLARE_WRITE_LINE_MEMBER(sdcs_w);
|
||||
DECLARE_WRITE_LINE_MEMBER(cntrl_mask_w);
|
||||
@ -646,11 +645,6 @@ void playch10_state::ram_8w_w(offs_t offset, u8 data)
|
||||
m_ram_8w[offset] = data;
|
||||
}
|
||||
|
||||
void playch10_state::sprite_dma_w(address_space &space, u8 data)
|
||||
{
|
||||
m_ppu->spriteram_dma(space, data);
|
||||
}
|
||||
|
||||
// Only used in single monitor bios
|
||||
|
||||
void playch10_state::time_w(offs_t offset, u8 data)
|
||||
@ -1519,7 +1513,7 @@ void playch10_state::cart_map(address_map &map)
|
||||
{
|
||||
map(0x0000, 0x07ff).mirror(0x1800).ram();
|
||||
map(0x2000, 0x3fff).rw(m_ppu, FUNC(ppu2c0x_device::read), FUNC(ppu2c0x_device::write));
|
||||
map(0x4014, 0x4014).w(FUNC(playch10_state::sprite_dma_w));
|
||||
map(0x4014, 0x4014).w(m_ppu, FUNC(ppu2c0x_device::spriteram_dma));
|
||||
map(0x4016, 0x4016).rw(FUNC(playch10_state::pc10_in0_r), FUNC(playch10_state::pc10_in0_w));
|
||||
map(0x4017, 0x4017).r(FUNC(playch10_state::pc10_in1_r)); // IN1 - input port 2 / PSG second control register
|
||||
// Games that don't bank PRG
|
||||
|
||||
@ -186,7 +186,6 @@ protected:
|
||||
|
||||
virtual void machine_reset() override;
|
||||
|
||||
template <u8 Side> void sprite_dma_w(address_space &space, u8 data);
|
||||
template <u8 Side> void vsnes_coin_counter_w(offs_t offset, u8 data);
|
||||
template <u8 Side> u8 vsnes_coin_counter_r(offs_t offset);
|
||||
template <u8 Side> void vsnes_in0_w(u8 data);
|
||||
@ -355,15 +354,6 @@ private:
|
||||
//******************************************************************************
|
||||
|
||||
|
||||
template <u8 Side>
|
||||
void vs_base_state::sprite_dma_w(address_space &space, u8 data)
|
||||
{
|
||||
if (Side == MAIN)
|
||||
m_ppu1->spriteram_dma(space, data & 0x07);
|
||||
else
|
||||
m_ppu2->spriteram_dma(space, data & 0x07);
|
||||
}
|
||||
|
||||
template <u8 Side>
|
||||
void vs_base_state::vsnes_coin_counter_w(offs_t offset, u8 data)
|
||||
{
|
||||
@ -996,7 +986,7 @@ void vs_base_state::vsnes_cpu1_map(address_map &map)
|
||||
{
|
||||
map(0x0000, 0x07ff).mirror(0x1800).ram();
|
||||
map(0x2000, 0x3fff).rw(m_ppu1, FUNC(ppu2c0x_device::read), FUNC(ppu2c0x_device::write));
|
||||
map(0x4014, 0x4014).w(FUNC(vs_base_state::sprite_dma_w<MAIN>));
|
||||
map(0x4014, 0x4014).w(m_ppu1, FUNC(ppu2c0x_device::spriteram_dma));
|
||||
map(0x4016, 0x4016).rw(FUNC(vs_base_state::vsnes_in0_r<MAIN>), FUNC(vs_base_state::vsnes_in0_w<MAIN>));
|
||||
map(0x4017, 0x4017).r(FUNC(vs_base_state::vsnes_in1_r<MAIN>)); // IN1 - input port 2 / PSG second control register
|
||||
map(0x4020, 0x5fff).rw(FUNC(vs_base_state::vsnes_coin_counter_r<MAIN>), FUNC(vs_base_state::vsnes_coin_counter_w<MAIN>));
|
||||
@ -1015,7 +1005,7 @@ void vs_base_state::vsnes_cpu2_map(address_map &map)
|
||||
{
|
||||
map(0x0000, 0x07ff).mirror(0x1800).ram();
|
||||
map(0x2000, 0x3fff).rw(m_ppu2, FUNC(ppu2c0x_device::read), FUNC(ppu2c0x_device::write));
|
||||
map(0x4014, 0x4014).w(FUNC(vs_base_state::sprite_dma_w<SUB>));
|
||||
map(0x4014, 0x4014).w(m_ppu2, FUNC(ppu2c0x_device::spriteram_dma));
|
||||
map(0x4016, 0x4016).rw(FUNC(vs_base_state::vsnes_in0_r<SUB>), FUNC(vs_base_state::vsnes_in0_w<SUB>));
|
||||
map(0x4017, 0x4017).r(FUNC(vs_base_state::vsnes_in1_r<SUB>)); // IN1 - input port 2 / PSG second control register
|
||||
map(0x4020, 0x5fff).rw(FUNC(vs_base_state::vsnes_coin_counter_r<SUB>), FUNC(vs_base_state::vsnes_coin_counter_w<SUB>));
|
||||
|
||||
Loading…
Reference in New Issue
Block a user