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video/pc_vga_cirrus.cpp: rectify linear addressing enable, fix regression with mtouchxl and SDD
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angelosa
parent
cf4c8d1f6f
commit
cb98157c46
@ -7,9 +7,7 @@
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* TODO:
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* - Original Acumos AVGA1/2 chipsets (Cirrus Logic eventually bought Acumos and rebranded);
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* - Fix or implement hidden DAC modes (15bpp + mixed, true color, others);
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* - bebox: logo at startup is squashed;
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* - zorro/picasso2: many blitting errors, verify HW cursor;
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* - zorro/picasso2: segmentation fault on exit
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* - Merge with trs/vis.cpp implementation (CL-GD5200 RAMDAC with custom VGA controller)
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*
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*/
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@ -20,14 +18,14 @@
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#include "screen.h"
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#define LOG_REG (1U << 1)
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#define LOG_REGS (1U << 1)
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#define LOG_BLIT (1U << 2)
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#define LOG_HDAC (1U << 3) // log hidden DAC
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#define LOG_BANK (1U << 4) // log offset registers
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#define LOG_PLL (1U << 5)
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#define VERBOSE (LOG_GENERAL | LOG_HDAC | LOG_REG | LOG_BLIT)
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//#define LOG_OUTPUT_FUNC osd_printf_info
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#define VERBOSE (LOG_GENERAL | LOG_HDAC | LOG_REGS | LOG_BLIT)
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#define LOG_OUTPUT_FUNC osd_printf_info
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#include "logmacro.h"
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@ -193,7 +191,7 @@ void cirrus_gd5428_vga_device::crtc_map(address_map &map)
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return m_cr19;
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}),
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NAME([this] (offs_t offset, u8 data) {
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LOGMASKED(LOG_REG, "CR19: Interlace End %02x\n", data);
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LOGMASKED(LOG_REGS, "CR19: Interlace End %02x\n", data);
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m_cr19 = data;
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})
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);
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@ -202,7 +200,7 @@ void cirrus_gd5428_vga_device::crtc_map(address_map &map)
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return m_cr1a;
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}),
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NAME([this] (offs_t offset, u8 data) {
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LOGMASKED(LOG_REG, "CR1A: Interlace Control %02x\n", data);
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LOGMASKED(LOG_REGS, "CR1A: Interlace Control %02x\n", data);
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m_cr1a = data;
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vga.crtc.horz_blank_end = (vga.crtc.horz_blank_end & 0xff3f) | ((data & 0x30) << 2);
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vga.crtc.vert_blank_end = (vga.crtc.vert_blank_end & 0xfcff) | ((data & 0xc0) << 2);
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@ -214,7 +212,7 @@ void cirrus_gd5428_vga_device::crtc_map(address_map &map)
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return m_cr1b;
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}),
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NAME([this] (offs_t offset, u8 data) {
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LOGMASKED(LOG_REG, "CR1B: Extended Display Controls %02x\n", data);
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LOGMASKED(LOG_REGS, "CR1B: Extended Display Controls %02x\n", data);
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m_cr1b = data;
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vga.crtc.start_addr_latch &= ~0x070000;
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vga.crtc.start_addr_latch |= ((data & 0x01) << 16);
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@ -226,7 +224,8 @@ void cirrus_gd5428_vga_device::crtc_map(address_map &map)
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// map(0x25, 0x25) PSR Part Status (r/o, "factory testing and internal tracking only")
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map(0x27, 0x27).lr8(
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NAME([this] (offs_t offset) {
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LOGMASKED(LOG_REG, "CR27: Read ID\n");
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// NOTE: verbose
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//LOGMASKED(LOG_REGS, "CR27: Read ID\n");
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return m_chip_id;
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})
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);
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@ -292,6 +291,7 @@ void cirrus_gd5428_vga_device::gc_map(address_map &map)
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return gc_mode_ext;
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}),
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NAME([this](offs_t offset, u8 data) {
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LOGMASKED(LOG_REGS, "GRB: Graphics Controller Mode Extensions %02x\n", data);
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gc_mode_ext = data;
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if(!(data & 0x04))
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{
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@ -525,12 +525,18 @@ void cirrus_gd5428_vga_device::sequencer_map(address_map &map)
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recompute_params();
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})
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);
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map(0x07, 0x07).lw8(
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map(0x07, 0x07).lrw8(
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NAME([this] (offs_t offset) {
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return vga.sequencer.data[0x07];
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}),
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NAME([this] (offs_t offset, u8 data) {
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// TODO: bebox startup enables this
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if((data & 0xf0) != 0)
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popmessage("pc_vga_cirrus: 1MB framebuffer window enabled at %iMB (%02x)",data >> 4,data);
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// xxxx ---- Memory Segment
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// 0000 ---- VGA segmenting
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// llll ---- (any other value) Linear addressing
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// ---- -xx- CRTC Character Clock Divider
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// ---- ---x Select 8bpp High Resolution Mode
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vga.sequencer.data[0x07] = data;
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LOGMASKED(LOG_REGS, "SR7: Extended Sequencer Mode %02x\n", data);
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recompute_params();
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})
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);
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@ -1121,14 +1127,14 @@ void cirrus_gd5428_vga_device::copy_pixel(uint8_t src, uint8_t dst)
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res = 0xff;
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break;
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case 0x50: // DSna / DPna
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// used by picasso2, unknown purpose
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// used by zorro2:picasso2p, unknown purpose
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res = (dst & (~src));
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break;
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case 0x59: // SRCINVERT
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res = src ^ dst;
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break;
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case 0x6d: // SRCPAINT / DSo
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// picasso2 on VGA Workbench (upper right icon)
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// zorro2:picasso2p on VGA Workbench (upper right icon)
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res = src | dst;
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break;
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default:
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@ -1188,10 +1194,10 @@ uint8_t cirrus_gd5428_vga_device::mem_r(offs_t offset)
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const uint8_t bank = offset_select(offset);
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// FIXME: workaround crash behaviour in picasso2
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// it will otherwise provide an offset of 0x1fxxxx in the gc_locked below
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// causing a crash during adapter init
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if(svga.rgb8_en || svga.rgb15_en || svga.rgb16_en || svga.rgb24_en)
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// TODO: incomplete, just enough for zorro2:picasso2p to not outright crash at display init
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// value should be a base to apply, also GRB[5] remaps banking granularity
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// NOTE: bebox also wants this
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if(vga.sequencer.data[0x07] & 0xf0)
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{
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return svga_device::mem_linear_r((offset & 0xffff) + bank * 0x10000);
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}
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@ -1349,8 +1355,8 @@ void cirrus_gd5428_vga_device::mem_w(offs_t offset, uint8_t data)
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const uint8_t bank = offset_select(offset);
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// FIXME: as above
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if(svga.rgb8_en || svga.rgb15_en || svga.rgb16_en || svga.rgb24_en)
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// TODO: as above
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if(vga.sequencer.data[0x07] & 0xf0)
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{
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svga_device::mem_linear_w((offset + bank * 0x10000), data);
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return;
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@ -1519,7 +1525,7 @@ void cirrus_gd5430_vga_device::crtc_map(address_map &map)
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return m_cr1d;
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}),
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NAME([this] (offs_t offset, u8 data) {
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LOGMASKED(LOG_REG, "CR1D: Overlay Extended Control %02x\n", data);
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LOGMASKED(LOG_REGS, "CR1D: Overlay Extended Control %02x\n", data);
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m_cr1d = data;
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// TODO: '34/'36 onward
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vga.crtc.start_addr_latch = (vga.crtc.start_addr_latch & 0xf7ffff) | (BIT(data, 7) << 19);
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@ -247,7 +247,8 @@ void mtxl_state::at486(machine_config &config)
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// on board devices
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ISA16_SLOT(config, "board1", 0, "mb:isabus", pc_isa16_cards, "ide", true).set_option_machine_config("ide", cdrom); // FIXME: determine ISA bus clock
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ISA16_SLOT(config, "isa1", 0, "mb:isabus", pc_isa16_cards, "svga_dm", true); // original is a gd-5440
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// TODO: original is a gd-5440, PCI only (svga_dm is '30)
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ISA16_SLOT(config, "isa1", 0, "mb:isabus", pc_isa16_cards, "svga_dm", true);
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ns16550_device &uart(NS16550(config, "ns16550", XTAL(1'843'200)));
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uart.out_tx_callback().set("microtouch", FUNC(microtouch_device::rx));
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