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(MESS) cat.c: updated comments with latest research. [Lord Nightmare]
This commit is contained in:
Jonathan Gevaryahu
parent
caa49d56a7
commit
cc299c4066
@ -331,7 +331,7 @@ ToDo:
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// Defines
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#undef DEBUG_VIDEO_ENABLE_W
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#undef DEBUG_GA2OPR_W
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#undef DEBUG_VIDEO_CONTROL_W
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#undef DEBUG_FLOPPY_CONTROL_W
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@ -340,8 +340,8 @@ ToDo:
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#undef DEBUG_FLOPPY_DATA_R
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#undef DEBUG_FLOPPY_STATUS_R
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#undef DEBUG_PRINTER_DATA_W
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#undef DEBUG_PRINTER_CONTROL_W
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#define DEBUG_PRINTER_DATA_W 1
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#define DEBUG_PRINTER_CONTROL_W 1
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#undef DEBUG_MODEM_R
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#undef DEBUG_MODEM_W
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@ -491,7 +491,7 @@ public:
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UINT8 m_duart_inp;
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/* gate array 2 has a 16-bit counter inside which counts at 10mhz and
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rolls over at FFFF->0000; on roll-over (or maybe at FFFF terminal count)
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it triggers the KTOBF output. It does this every 6.5535ms, which causes
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it triggers the KTDBF output. It does this every 6.5535ms, which causes
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a 74LS74 d-latch at IC100 to switch the state of the DUART IP2 line;
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this causes the DUART to fire an interrupt, which makes the 68000 read
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the keyboard.
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@ -613,7 +613,9 @@ WRITE16_MEMBER( cat_state::cat_keyboard_w )
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m_keyboard_line = data >> 8;
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}
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// 0x800004-0x800005 write = printer data
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// 0x800004-0x800005 'pr.data' write
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// /DSTB (centronics pin 1) is implied by the cat source code to be pulsed
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// low (for some unknown period of time) upon any write to this port.
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WRITE16_MEMBER( cat_state::cat_printer_data_w )
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{
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#ifdef DEBUG_PRINTER_DATA_W
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@ -680,23 +682,27 @@ READ16_MEMBER( cat_state::cat_keyboard_r )
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case 0x80: retVal = m_y7->read() << 8; break;
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}
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}
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if ((m_pr_cont != 0x0800) && (m_pr_cont != 0x0900) && (m_pr_cont != 0x0a00))
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{
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fprintf(stderr,"Read from keyboard in %06X with unexpected pr_cont %04X\n", 0x80000a+(offset<<1), m_pr_cont);
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}
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return retVal;
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}
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// 0x80000c-0x80000d (unused in cat source code; may have originally been a separate read only port where 800006 would have been write-only)
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// 0x80000e-0x80000f read
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// 0x80000e-0x80000f 'pr.cont' read
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READ16_MEMBER( cat_state::cat_battery_r )
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{
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/*
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* FEDCBA98 (76543210 is open bus)
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* |||||||\-- ?
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* ||||||\--- ?
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* |||||\---- ?
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* ||||\----- ?
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* |||\------ ?
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* ||\------- ?
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* |\-------- ?
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* |||||||\-- ? possibly PE (pin 1) read ("PAPER OUT" pin 12 of centronics port)
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* ||||||\--- ? possibly SLCT/ERR (pin 3) read ("not selected or error" NAND of pins 32 and 13 of centronics port)
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* |||||\---- (always 0?)
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* ||||\----- (always 0?)
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* |||\------ (always 0?)
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* ||\------- (always 0?)
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* |\-------- (always 0?)
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* \--------- Battery status (0 = good, 1 = bad)
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*/
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/* just return that battery is full, i.e. bit 15 is 0 */
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@ -704,15 +710,15 @@ READ16_MEMBER( cat_state::cat_battery_r )
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// TODO: hook this to a dipswitch
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return 0x0080;
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}
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// 0x80000e-0x80000f write
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// 0x80000e-0x80000f 'pr.cont' write
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WRITE16_MEMBER( cat_state::cat_printer_control_w )
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{
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/*
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* FEDCBA98 (76543210 is ignored)
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* |||||||\-- CC line enable (pin 34) (verified from cat source code)
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* ||||||\--- LEDE line enable (pin 33) (verified from cat source code)
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* |||||\---- ? May control pin 32?
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* ||||\----- ? always seems to be written as high?
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* |||||\---- ?
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* ||||\----- ? may be IPP (pin 2) write (non-standard pin 34 of centronics port) or another watchdog reset bit; may also be /DSTB-enable-on-pr.data-write
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* |||\------ ?
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* ||\------- ?
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* |\-------- ?
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@ -743,13 +749,13 @@ WRITE16_MEMBER( cat_state::cat_modem_w )
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#endif
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}
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// 0x830000: 6ms counter (used for KTOBF)
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// 0x830000: 6ms counter (used for KTDBF)
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READ16_MEMBER( cat_state::cat_6ms_counter_r )
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{
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return m_6ms_counter;
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}
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/* 0x840001: 'opr' Output Port Register
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/* 0x840001: 'opr' or 'ga2opr' Output Port Register
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* writing 0x1c (or probably anything with bit 3 set) here resets the watchdog
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* if the watchdog expires an NMI is sent to the cpu
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*/
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@ -851,7 +857,7 @@ static ADDRESS_MAP_START(cat_mem, AS_PROGRAM, 16, cat_state)
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AM_RANGE(0x040000, 0x043fff) AM_RAM AM_SHARE("svram") AM_MIRROR(0x18C000)// SRAM powered by battery
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AM_RANGE(0x200000, 0x27ffff) AM_ROM AM_REGION("svrom",0x0000) AM_MIRROR(0x180000) // SV ROM
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AM_RANGE(0x400000, 0x47ffff) AM_RAM AM_SHARE("p_cat_vram") AM_MIRROR(0x180000) // 512 KB RAM
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AM_RANGE(0x600000, 0x67ffff) AM_READWRITE(cat_2e80_r,cat_video_control_w) AM_MIRROR(0x180000) // Gate Array #1: Video
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AM_RANGE(0x600000, 0x67ffff) AM_READWRITE(cat_2e80_r,cat_video_control_w) AM_MIRROR(0x180000) // Gate Array #1: Video Addressing and Timing, dram refresh timing, dram /cs and /wr (ga2 does the actual video invert/display and access to the dram data bus)
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AM_RANGE(0x800000, 0x800001) AM_READWRITE(cat_floppy_control_r, cat_floppy_control_w) AM_MIRROR(0x18FFE0) // floppy control lines and readback
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AM_RANGE(0x800002, 0x800003) AM_READWRITE(cat_0080_r, cat_keyboard_w) AM_MIRROR(0x18FFE0) // keyboard col write
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AM_RANGE(0x800004, 0x800005) AM_READWRITE(cat_0080_r, cat_printer_data_w) AM_MIRROR(0x18FFE0) // Centronics Printer Data
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@ -864,8 +870,8 @@ static ADDRESS_MAP_START(cat_mem, AS_PROGRAM, 16, cat_state)
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AM_RANGE(0x810000, 0x81001f) AM_DEVREADWRITE8("duartn68681", duartn68681_device, read, write, 0xff ) AM_MIRROR(0x18FFE0)
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AM_RANGE(0x820000, 0x82003f) AM_READWRITE(cat_modem_r,cat_modem_w) AM_MIRROR(0x18FFC0) // AMI S35213 Modem Chip, all access is on bit 7
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AM_RANGE(0x830000, 0x830001) AM_READ(cat_6ms_counter_r) AM_MIRROR(0x18FFFE) // 16bit 6ms counter clocked by output of another 16bit counter clocked at 10mhz
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AM_RANGE(0x840000, 0x840001) AM_READWRITE(cat_2e80_r,cat_opr_w) AM_MIRROR(0x18FFFE) // Output port register (video enable, invert, watchdog reset)
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//AM_RANGE(0x850000, 0x850001) AM_READ(cat_video_status) AM_MIRROR(0x18FFFE) // video status and watchdog read: hblank, vblank or draw?
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AM_RANGE(0x840000, 0x840001) AM_READWRITE(cat_2e80_r,cat_opr_w) AM_MIRROR(0x18FFFE) // GA2 Output port register (video enable, invert, watchdog reset, phone relays)
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//AM_RANGE(0x850000, 0x850001) AM_READ(cat_wdt_r) AM_MIRROR(0x18FFFE) // watchdog and power fail state read
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AM_RANGE(0x860000, 0x860001) AM_READWRITE(cat_0000_r, cat_tcb_w) AM_MIRROR(0x18FFFE) // Test mode
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AM_RANGE(0x870000, 0x870001) AM_READ(cat_2e80_r) AM_MIRROR(0x18FFFE) // Open bus?
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AM_RANGE(0xA00000, 0xA00001) AM_READ(cat_2e80_r) AM_MIRROR(0x1FFFFE) // Open bus/dtack? The 0xA00000-0xA3ffff area is ram used for shadow rom storage on cat developer machines, which is either banked over top of, or jumped to instead of the normal rom
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@ -999,7 +1005,7 @@ void cat_state::device_timer(emu_timer &timer, device_timer_id id, int param, vo
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TIMER_CALLBACK_MEMBER(cat_state::counter_6ms_callback)
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{
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// This is effectively also the KTOBF line 'clock' output to the d-latch before the duart
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// This is effectively also the KTDBF line 'clock' output to the d-latch before the duart
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// Hence, invert the d-latch on the duart's input ports.
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// n68681 now properly generates interrupts when this bit changes, the previous hack is no longer necessary.
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m_duart_inp ^= 0x04;
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@ -1066,7 +1072,7 @@ UINT32 cat_state::screen_update_cat(screen_device &screen, bitmap_ind16 &bitmap,
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}
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/* The duart is the only thing actually connected to the cpu IRQ pin
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* The KTOBF output of the gate array 2 (itself the terminal count output
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* The KTDBF output of the gate array 2 (itself the terminal count output
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* of a 16-bit counter clocked at ~10mhz, hence 6.5536ms period) goes to a
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* d-latch and inputs on ip2 of the duart, causing the duart to fire an irq;
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* this is used by the cat to read the keyboard.
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@ -1091,10 +1097,10 @@ WRITE_LINE_MEMBER(cat_state::cat_duart_txa)
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/* mc68681 DUART Input pins:
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* IP0: CTS [using the DUART builtin hardware-CTS feature?]
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* IP1: Centronics ACK (IP1 changes state 0->1 or 1->0 on the falling edge of /ACK using a d-latch)
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* IP2: KTOBF (IP2 changes state 0->1 or 1->0 on the rising edge of KTOBF using a d-latch; KTOBF is a 6.5536ms-period squarewave generated by one of the gate arrays, I need to check with a scope to see whether it is a single spike/pulse every 6.5536ms or if from the gate array it inverts every 6.5536ms, documentation isn't 100% clear but I suspect the former) [uses the Delta IP2 state change detection feature to generate an interrupt; I'm not sure if IP2 is used as a counter clock source but given the beep frequency of the real unit I very much doubt it, 6.5536ms is too slow]
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* IP1: Centronics /ACK (pin 10) positive edge detect (IP1 changes state 0->1 or 1->0 on the rising edge of /ACK using a 74ls74a d-flipflop)
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* IP2: KTDBF (IP2 changes state 0->1 or 1->0 on the rising edge of KTDBF using a 74ls74a d-flipflop; KTDBF is a 6.5536ms-period squarewave generated by one of the gate arrays, I need to check with a scope to see whether it is a single spike/pulse every 6.5536ms or if from the gate array it inverts every 6.5536ms, documentation isn't 100% clear but I suspect the former) [uses the Delta IP2 state change detection feature to generate an interrupt; I'm not sure if IP2 is used as a counter clock source but given the beep frequency of the real unit I very much doubt it, 6.5536ms is too slow]
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* IP3: RG ("ring" input)
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* IP4: Centronics BUSY
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* IP4: Centronics BUSY (pin 11), inverted
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* IP5: DSR
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*/
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@ -1137,7 +1143,7 @@ static MACHINE_CONFIG_START( cat, cat_state )
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MCFG_VIDEO_START_OVERRIDE(cat_state,cat)
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MCFG_DUARTN68681_ADD( "duartn68681", XTAL_19_968MHz*2/11 ) // duart is normally clocked by 3.6864mhz xtal, but cat seemingly uses a divider from the main xtal instead which probably yields 3.63054545Mhz. There is a trace to cut and a mounting area to allow using an actual 3.6864mhz xtal if you so desire
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MCFG_DUARTN68681_ADD( "duartn68681", (XTAL_19_968MHz*2)/11 ) // duart is normally clocked by 3.6864mhz xtal, but cat seemingly uses a divider from the main xtal instead which probably yields 3.63054545Mhz. There is a trace to cut and a mounting area to allow using an actual 3.6864mhz xtal if you so desire
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MCFG_DUARTN68681_IRQ_CALLBACK(WRITELINE(cat_state, cat_duart_irq_handler))
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MCFG_DUARTN68681_A_TX_CALLBACK(WRITELINE(cat_state, cat_duart_txa))
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MCFG_DUARTN68681_OUTPORT_CALLBACK(WRITE8(cat_state, cat_duart_output))
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@ -1626,7 +1632,7 @@ ROM_START( cat )
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* Based on the inputs and outputs of this pal, almost if not the entire
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* open bus and mirrored areas of the cat address space could be made
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* to cause bus errors. REMAP was probably used to 'open up' the A00000-A7ffff
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* shadow rom/ram area and make it writable without erroring.
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* shadow rom/ram area and make it writeable without erroring.
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*/
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ROM_END
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