From cc659dcabd47c3c1efb8efed8a2310ce364bad47 Mon Sep 17 00:00:00 2001 From: mahlemiut Date: Mon, 24 Sep 2012 13:15:50 +0000 Subject: [PATCH] (MESS) svga_s3: added extra extended start address and banking registers (no whatsnew) --- src/emu/video/pc_vga.c | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/src/emu/video/pc_vga.c b/src/emu/video/pc_vga.c index 45ec3e1e066..982955e28e8 100644 --- a/src/emu/video/pc_vga.c +++ b/src/emu/video/pc_vga.c @@ -2755,12 +2755,18 @@ static UINT8 s3_crtc_reg_read(running_machine &machine, UINT8 index) case 0x4f: res = s3.cursor_pattern_y; break; + case 0x51: + res = (vga.crtc.start_addr & 0x0c0000) >> 18; + break; case 0x55: res = s3.extended_dac_ctrl; break; case 0x67: res = s3.ext_misc_ctrl_2; break; + case 0x69: + res = vga.crtc.start_addr >> 16; + break; case 0x6a: res = svga.bank_r & 0x7f; break; @@ -2964,6 +2970,9 @@ bit 0-5 Pattern Display Start Y-Pixel Position. case 0x51: vga.crtc.start_addr &= ~0xc0000; vga.crtc.start_addr |= ((data & 0x3) << 18); + svga.bank_w = (svga.bank_w & 0xcf) | ((data & 0x0c) << 2); + svga.bank_r = svga.bank_r; + s3_define_video_mode(); break; case 0x53: s3.cr53 = data; @@ -2996,10 +3005,14 @@ bit 0-1 DAC Register Select Bits. Passed to the RS2 and RS3 pins on the s3.ext_misc_ctrl_2 = data; s3_define_video_mode(); //printf("%02x X\n",data); - //debugger_break(machine); + break; + case 0x69: + vga.crtc.start_addr &= ~0x1f0000; + vga.crtc.start_addr |= ((data & 0x1f) << 16); + s3_define_video_mode(); break; case 0x6a: - svga.bank_w = data & 0xf; + svga.bank_w = data & 0x3f; svga.bank_r = svga.bank_w; if(data & 0x60) fatalerror("TODO: s3 bank selects above 1M\n");