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macOS compile fix and first pass at cancer removal from rainbow.cpp, nw

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This commit is contained in:
mooglyguy 2018-12-05 21:43:57 +01:00
parent e1a2212fba
commit ccd87f82ec
1 changed files with 506 additions and 518 deletions
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404
src/mame/drivers/rainbow.cpp
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@ -698,22 +698,28 @@ private:
hard_disk_file *rainbow_hdc_file(int ref); hard_disk_file *rainbow_hdc_file(int ref);
uint8_t m_GDC_WRITE_BUFFER[16]; // 16 x 8 bits for CPU, 8 x 16 for GDC uint8_t m_gdc_write_buffer[16]; // 16 x 8 bits for CPU, 8 x 16 for GDC
uint8_t m_GDC_COLOR_MAP[32]; uint8_t m_gdc_color_map[32];
uint8_t m_GDC_SCROLL_BUFFER[256]; uint8_t m_gdc_scroll_buffer[256];
uint8_t m_GDC_INDIRECT_REGISTER, m_GDC_MODE_REGISTER, m_GDC_scroll_index, m_GDC_color_map_index, m_GDC_write_buffer_index; uint8_t m_gdc_indirect_register;
uint8_t m_GDC_ALU_PS_REGISTER, m_GDC_FG_BG; uint8_t m_gdc_mode_register;
uint8_t m_gdc_scroll_index;
uint8_t m_gdc_color_map_index;
uint8_t m_gdc_write_buffer_index;
uint8_t m_gdc_alu_ps_register;
uint8_t m_gdc_fg_bg;
uint8_t m_vpat, m_patmult, m_patcnt, m_patidx; uint8_t m_vpat, m_patmult, m_patcnt, m_patidx;
uint16_t m_GDC_WRITE_MASK; uint16_t m_gdc_write_mask;
bool m_ONBOARD_GRAPHICS_SELECTED; // (internal switch, on board video to mono out) bool m_onboard_graphics_selected; // (internal switch, on board video to mono out)
bool m_SCREEN_BLANK; bool m_screen_blank;
uint8_t m_monitor_suggested; uint8_t m_monitor_suggested;
int INT88, INTZ80; int m_int88;
int m_intz80;
bool m_zflip; // Z80 alternate memory map with A15 inverted bool m_zflip; // Z80 alternate memory map with A15 inverted
bool m_z80_halted; bool m_z80_halted;
@ -751,7 +757,7 @@ private:
uint8_t m_hdc_buffer[2048]; uint8_t m_hdc_buffer[2048];
bool m_POWER_GOOD; bool m_power_good;
emu_timer *cmd_timer; emu_timer *cmd_timer;
emu_timer *switch_off_timer; emu_timer *switch_off_timer;
@ -785,29 +791,29 @@ if(m_patidx == 0) m_patidx = 7;
#define OPTION_GRFX_RESET \ #define OPTION_GRFX_RESET \
lower_8088_irq(IRQ_GRF_INTR_L); \ lower_8088_irq(IRQ_GRF_INTR_L); \
m_monitor_suggested = m_inp13->read(); \ m_monitor_suggested = m_inp13->read(); \
m_GDC_INDIRECT_REGISTER = 0; \ m_gdc_indirect_register = 0; \
m_GDC_color_map_index = 0; \ m_gdc_color_map_index = 0; \
for(int i=0; i <256; i++) { m_GDC_SCROLL_BUFFER[i] = i; }; \ for (int i = 0; i < 256; i++) \
m_GDC_scroll_index = 0; \ m_gdc_scroll_buffer[i] = i; \
m_GDC_write_buffer_index = 0; \ m_gdc_scroll_index = 0; \
m_GDC_WRITE_MASK = 0x00; \ m_gdc_write_buffer_index = 0; \
m_GDC_ALU_PS_REGISTER = 0x0F; \ m_gdc_write_mask = 0x00; \
m_GDC_FG_BG = 0xF0; \ m_gdc_alu_ps_register = 0x0F; \
m_GDC_MODE_REGISTER &= GDC_MODE_VECTOR | GDC_MODE_HIGHRES | GDC_MODE_ENABLE_WRITES | GDC_MODE_READONLY_SCROLL_MAP;\ m_gdc_fg_bg = 0xF0; \
m_GDC_MODE_REGISTER |= GDC_MODE_ENABLE_VIDEO; \ m_gdc_mode_register &= GDC_MODE_VECTOR | GDC_MODE_HIGHRES | GDC_MODE_ENABLE_WRITES | GDC_MODE_READONLY_SCROLL_MAP;\
m_gdc_mode_register |= GDC_MODE_ENABLE_VIDEO; \
logerror("\n** OPTION GRFX. RESET **\n"); logerror("\n** OPTION GRFX. RESET **\n");
UPD7220_DISPLAY_PIXELS_MEMBER( rainbow_state::hgdc_display_pixels ) UPD7220_DISPLAY_PIXELS_MEMBER( rainbow_state::hgdc_display_pixels )
{ {
const rgb_t *paletteX = m_palette2->palette()->entry_list_raw(); const rgb_t *paletteX = m_palette2->palette()->entry_list_raw();
int xi;
uint16_t plane0, plane1, plane2, plane3; uint16_t plane0, plane1, plane2, plane3;
uint8_t pen; uint8_t pen;
if(m_ONBOARD_GRAPHICS_SELECTED && (m_inp13->read() != DUAL_MONITOR) ) if (m_onboard_graphics_selected && (m_inp13->read() != DUAL_MONITOR))
{ {
for(xi=0;xi<16;xi++) // blank screen when VT102 output active (..) for (int xi = 0; xi < 16; xi++) // blank screen when VT102 output active (..)
{ {
if (bitmap.cliprect().contains(x + xi, y)) if (bitmap.cliprect().contains(x + xi, y))
bitmap.pix32(y, x + xi) = 0; bitmap.pix32(y, x + xi) = 0;
@ -817,16 +823,16 @@ UPD7220_DISPLAY_PIXELS_MEMBER( rainbow_state::hgdc_display_pixels )
// ********************* GET BITMAP DATA FOR 4 PLANES *************************************** // ********************* GET BITMAP DATA FOR 4 PLANES ***************************************
// _READ_ BIT MAP from 2 or 4 planes (plane 0 is least, plane 3 most significant). See page 42 / 43 // _READ_ BIT MAP from 2 or 4 planes (plane 0 is least, plane 3 most significant). See page 42 / 43
if(m_GDC_MODE_REGISTER & GDC_MODE_HIGHRES) if (m_gdc_mode_register & GDC_MODE_HIGHRES)
{ {
address = ( m_GDC_SCROLL_BUFFER[ ((address & 0x7FC0) >> 7) & 0xff ] << 7) | (address & 0x7F); address = ( m_gdc_scroll_buffer[ ((address & 0x7FC0) >> 7) & 0xff ] << 7) | (address & 0x7F);
plane0 = m_video_ram[((address & 0x7fff) + 0x00000) >> 1]; plane0 = m_video_ram[((address & 0x7fff) + 0x00000) >> 1];
plane1 = m_video_ram[((address & 0x7fff) + 0x10000) >> 1]; plane1 = m_video_ram[((address & 0x7fff) + 0x10000) >> 1];
plane2 = plane3 = 0; plane2 = plane3 = 0;
} }
else else
{ {
address = ( m_GDC_SCROLL_BUFFER[ ((address & 0x3FC0) >> 7) & 0xff ] << 7) | (address & 0x7F); address = ( m_gdc_scroll_buffer[ ((address & 0x3FC0) >> 7) & 0xff ] << 7) | (address & 0x7F);
// MED.RESOLUTION (4 planes, 4 color bits, 16 color map entries / 16 -or 4- MONOCHROME SHADES) // MED.RESOLUTION (4 planes, 4 color bits, 16 color map entries / 16 -or 4- MONOCHROME SHADES)
plane0 = m_video_ram[((address & 0x3fff) + 0x00000) >> 1]; plane0 = m_video_ram[((address & 0x3fff) + 0x00000) >> 1];
plane1 = m_video_ram[((address & 0x3fff) + 0x10000) >> 1]; plane1 = m_video_ram[((address & 0x3fff) + 0x10000) >> 1];
@ -836,7 +842,7 @@ UPD7220_DISPLAY_PIXELS_MEMBER( rainbow_state::hgdc_display_pixels )
bool mono = (m_monitor_suggested == MONO_MONITOR) ? true : false; // 1 = MONO, 2 = COLOR, 3 = DUAL MONITOR; 4 = AUTO bool mono = (m_monitor_suggested == MONO_MONITOR) ? true : false; // 1 = MONO, 2 = COLOR, 3 = DUAL MONITOR; 4 = AUTO
for(xi=0;xi<16;xi++) for (int xi = 0; xi < 16; xi++)
{ {
pen = BIT(plane0 ,xi) | pen = BIT(plane0 ,xi) |
(BIT(plane1 ,xi) << 1) | (BIT(plane1 ,xi) << 1) |
@ -865,7 +871,7 @@ static void rainbow_floppies(device_slot_interface &device)
void rainbow_state::machine_start() void rainbow_state::machine_start()
{ {
m_POWER_GOOD = false; // Simulate AC_OK signal from power supply. m_power_good = false; // Simulate AC_OK signal from power supply.
cmd_timer = timer_alloc(0); cmd_timer = timer_alloc(0);
cmd_timer->adjust(attotime::from_msec(MS_TO_POWER_GOOD)); cmd_timer->adjust(attotime::from_msec(MS_TO_POWER_GOOD));
@ -874,7 +880,7 @@ void rainbow_state::machine_start()
m_digits.resolve(); m_digits.resolve();
m_SCREEN_BLANK = false; m_screen_blank = false;
auto *printer_port = subdevice<rs232_port_device>("printer"); auto *printer_port = subdevice<rs232_port_device>("printer");
printer_port->write_dtr(0); printer_port->write_dtr(0);
@ -1145,8 +1151,6 @@ void rainbow_state::machine_reset()
uint32_t unmap_start = m_inp8->read(); uint32_t unmap_start = m_inp8->read();
// Verify RAM size matches hardware (DIP switches) // Verify RAM size matches hardware (DIP switches)
uint8_t NVRAM_LOCATION;
uint32_t check;
#ifdef ASSUME_RAINBOW_A_HARDWARE #ifdef ASSUME_RAINBOW_A_HARDWARE
printf("\n*** RAINBOW A MODEL ASSUMED (64 - 832 K RAM).\n"); printf("\n*** RAINBOW A MODEL ASSUMED (64 - 832 K RAM).\n");
@ -1156,8 +1160,8 @@ void rainbow_state::machine_reset()
printf("\nWARNING: 896 K is not a valid memory configuration on Rainbow 100 A!\n"); printf("\nWARNING: 896 K is not a valid memory configuration on Rainbow 100 A!\n");
} }
check = (unmap_start >> 16)-1; // guess. uint32_t check = (unmap_start >> 16)-1; // guess.
NVRAM_LOCATION = m_p_nvram[0x84]; // location not verified yet. DMT RAM check tests offset $84 ! uint8_t nvram_location = m_p_nvram[0x84]; // location not verified yet. DMT RAM check tests offset $84 !
#ifdef RTC_ENABLED #ifdef RTC_ENABLED
// *********************************** / DS1315 'PHANTOM CLOCK' IMPLEMENTATION FOR 'DEC-100-A' *************************************** // *********************************** / DS1315 'PHANTOM CLOCK' IMPLEMENTATION FOR 'DEC-100-A' ***************************************
@ -1174,8 +1178,8 @@ void rainbow_state::machine_reset()
printf("\nWARNING: 64 K is not a valid memory size on Rainbow 100-B!\n"); printf("\nWARNING: 64 K is not a valid memory size on Rainbow 100-B!\n");
} }
check = (unmap_start >> 16) - 2; uint32_t check = (unmap_start >> 16) - 2;
NVRAM_LOCATION = m_p_nvram[0xdb]; uint8_t nvram_location = m_p_nvram[0xdb];
#ifdef RTC_ENABLED #ifdef RTC_ENABLED
// *********************************** / DS1315 'PHANTOM CLOCK' IMPLEMENTATION FOR 'DEC-100-B' *************************************** // *********************************** / DS1315 'PHANTOM CLOCK' IMPLEMENTATION FOR 'DEC-100-B' ***************************************
@ -1184,8 +1188,8 @@ void rainbow_state::machine_reset()
// *********************************** / DS1315 'PHANTOM CLOCK' IMPLEMENTATION FOR 'DEC-100-B' *************************************** // *********************************** / DS1315 'PHANTOM CLOCK' IMPLEMENTATION FOR 'DEC-100-B' ***************************************
#endif #endif
#endif #endif
if (check != NVRAM_LOCATION) if (check != nvram_location)
printf("\nNOTE: RAM configuration does not match NVRAM.\nUNMAP_START = %05x NVRAM VALUE = %02x SHOULD BE: %02x\n", unmap_start, NVRAM_LOCATION, check); printf("\nNOTE: RAM configuration does not match NVRAM.\nUNMAP_START = %05x NVRAM VALUE = %02x SHOULD BE: %02x\n", unmap_start, nvram_location, check);
if (END_OF_RAM > unmap_start) if (END_OF_RAM > unmap_start)
{ {
@ -1248,8 +1252,11 @@ void rainbow_state::machine_reset()
OPTION_GRFX_RESET OPTION_GRFX_RESET
OPTION_RESET_PATTERNS OPTION_RESET_PATTERNS
for(int i=0; i <32; i++) { m_GDC_COLOR_MAP[i] = 0x00; }; for (int i = 0; i < 32; i++)
m_GDC_color_map_index = 0; {
m_gdc_color_map[i] = 0x00;
};
m_gdc_color_map_index = 0;
// *********** Z80 // *********** Z80
m_z80->set_input_line(INPUT_LINE_HALT, ASSERT_LINE); m_z80->set_input_line(INPUT_LINE_HALT, ASSERT_LINE);
@ -1258,8 +1265,8 @@ void rainbow_state::machine_reset()
m_zflip = true; // ZRESET high on startup m_zflip = true; // ZRESET high on startup
m_diagnostic = 0; // DIAGNOSTIC_R/W registers (shouldn't it be 1?) m_diagnostic = 0; // DIAGNOSTIC_R/W registers (shouldn't it be 1?)
INTZ80 = false; m_intz80 = false;
INT88 = false; m_int88 = false;
// *********** SERIAL COMM. (7201) // *********** SERIAL COMM. (7201)
m_mpsc->reset(); m_mpsc->reset();
@ -1296,12 +1303,11 @@ void rainbow_state::device_timer(emu_timer &timer, device_timer_id tid, int para
switch (tid) switch (tid)
{ {
case 0: case 0:
cmd_timer->adjust(attotime::never); cmd_timer->adjust(attotime::never);
if (m_POWER_GOOD == false) if (m_power_good == false)
{ {
m_POWER_GOOD = true; m_power_good = true;
printf("\n**** POWER GOOD ****\n"); printf("\n**** POWER GOOD ****\n");
} }
else else
@ -1347,7 +1353,7 @@ uint32_t rainbow_state::screen_update_rainbow(screen_device &screen, bitmap_ind1
} }
int palette_selected; int palette_selected;
if( m_ONBOARD_GRAPHICS_SELECTED && (monitor_selected == COLOR_MONITOR) ) if (m_onboard_graphics_selected && (m_monitor_suggested == COLOR_MONITOR))
palette_selected = 2; // Color monitor; green text palette_selected = 2; // Color monitor; green text
else else
palette_selected = m_inp9->read(); palette_selected = m_inp9->read();
@ -1355,9 +1361,7 @@ uint32_t rainbow_state::screen_update_rainbow(screen_device &screen, bitmap_ind1
m_crtc->palette_select(palette_selected); m_crtc->palette_select(palette_selected);
m_crtc->video_update(bitmap, cliprect); m_crtc->video_update(bitmap, cliprect);
if( m_SCREEN_BLANK || if (m_screen_blank || ((!m_onboard_graphics_selected) && (m_inp13->read() != DUAL_MONITOR))) // dual monitor: never blank all
( (!m_ONBOARD_GRAPHICS_SELECTED) && (m_inp13->read() != DUAL_MONITOR) ) // dual monitor: never blank all
)
m_crtc->video_blanking(bitmap, cliprect); m_crtc->video_blanking(bitmap, cliprect);
else else
m_crtc->video_update(bitmap, cliprect); m_crtc->video_update(bitmap, cliprect);
@ -1541,7 +1545,7 @@ WRITE8_MEMBER(rainbow_state::ext_ram_w)
// - also needed to set time/date (*). Reads $ed000, writes ed0fe/ed0ff. // - also needed to set time/date (*). Reads $ed000, writes ed0fe/ed0ff.
WRITE8_MEMBER(rainbow_state::rtc_w) WRITE8_MEMBER(rainbow_state::rtc_w)
{ {
if((m_inp11->read() == 0x01)) // if enabled... if (m_inp11->read() == 0x01) // if enabled...
{ {
switch (offset) switch (offset)
{ {
@ -1568,7 +1572,7 @@ WRITE8_MEMBER(rainbow_state::rtc_w)
// Requires CLIKCLOK.COM or RBCLIK21.COM (freeware from Latrobe). Uses FC000/FE000. // Requires CLIKCLOK.COM or RBCLIK21.COM (freeware from Latrobe). Uses FC000/FE000.
READ8_MEMBER(rainbow_state::rtc_r) READ8_MEMBER(rainbow_state::rtc_r)
{ {
if((m_inp11->read() == 0x01)) // if enabled... if (m_inp11->read() == 0x01) // if enabled...
{ {
switch (offset) switch (offset)
{ {
@ -1640,8 +1644,8 @@ READ8_MEMBER(rainbow_state::corvus_status_r)
switch_off_timer->adjust(attotime::from_msec(500)); switch_off_timer->adjust(attotime::from_msec(500));
uint8_t status = m_corvus_hdc->status_r(space, 0); uint8_t status = m_corvus_hdc->status_r(space, 0);
uint8_t data = (status & 0x80) ? 1 : 0; // 0x80 BUSY (Set = Busy, Clear = Ready) uint8_t data = BIT(status, 7); // 0x80 BUSY (Set = Busy, Clear = Ready)
data |= (status & 0x40) ? 0 : 2; // 0x40 DIR. (Controller -> Host, or Host->Controller) data |= BIT(status, 6) << 1; // 0x40 DIR. (Controller -> Host, or Host->Controller)
return data; return data;
} }
} }
@ -1681,8 +1685,7 @@ hard_disk_file *rainbow_state::rainbow_hdc_file(int drv)
if (drv != 0) if (drv != 0)
return nullptr; return nullptr;
harddisk_image_device *img = nullptr; harddisk_image_device *img = dynamic_cast<harddisk_image_device *>(subdevice("decharddisk1"));
img = dynamic_cast<harddisk_image_device *>(subdevice("decharddisk1"));
if (!img) if (!img)
return nullptr; return nullptr;
@ -1697,8 +1700,7 @@ hard_disk_file *rainbow_state::rainbow_hdc_file(int drv)
// CYLINDERS: 151 (~ 5 MB) to 1024 (max. cylinders on WD1010 controller) // CYLINDERS: 151 (~ 5 MB) to 1024 (max. cylinders on WD1010 controller)
if (((info->sectors <= RD51_SECTORS_PER_TRACK)) && if (((info->sectors <= RD51_SECTORS_PER_TRACK)) &&
((info->heads >= 1) && (info->heads <= RD51_MAX_HEAD)) && // HEADS WITHIN 1...8 ((info->heads >= 1) && (info->heads <= RD51_MAX_HEAD)) && // HEADS WITHIN 1...8
((info->cylinders > 150) && (info->cylinders <= RD51_MAX_CYLINDER)) ((info->cylinders > 150) && (info->cylinders <= RD51_MAX_CYLINDER)))
)
{ {
m_hdc_drive_ready = true; m_hdc_drive_ready = true;
return file; // HAS SANE GEOMETRY return file; // HAS SANE GEOMETRY
@ -1742,8 +1744,8 @@ WRITE_LINE_MEMBER(rainbow_state::hdc_read_sector)
if (!m_hdc_write_gate) // do not read when WRITE GATE is on if (!m_hdc_write_gate) // do not read when WRITE GATE is on
{ {
uint8_t SDH = (m_hdc->read(generic_space(), 0x06)); uint8_t sdh = (m_hdc->read(generic_space(), 0x06));
int drv = (SDH & (8 + 16)) >> 3; // get DRIVE from SDH register int drv = (sdh & (8 + 16)) >> 3; // get DRIVE from SDH register
if ((state == 0) && (last_state == 1) && (drv == 0)) if ((state == 0) && (last_state == 1) && (drv == 0))
{ {
@ -1769,10 +1771,10 @@ WRITE_LINE_MEMBER(rainbow_state::hdc_read_sector)
output().set_value("led1", 1); output().set_value("led1", 1);
// Pointer to info + C + H + S // Pointer to info + C + H + S
uint32_t lbasector = get_and_print_lbasector(this, info, cylinder, SDH & 0x07, sector_number); uint32_t lbasector = get_and_print_lbasector(this, info, cylinder, sdh & 0x07, sector_number);
if ((cylinder <= info->cylinders) && // filter invalid ranges if ((cylinder <= info->cylinders) && // filter invalid ranges
(SECTOR_SIZES[(SDH >> 5) & 0x03] == info->sectorbytes) // may not vary in image! (SECTOR_SIZES[(sdh >> 5) & 0x03] == info->sectorbytes) // may not vary in image!
) )
{ {
read_status = 5; read_status = 5;
@ -1787,7 +1789,7 @@ WRITE_LINE_MEMBER(rainbow_state::hdc_read_sector)
if (read_status != 0) if (read_status != 0)
{ {
logerror("...** READ FAILED WITH STATUS %u ** (CYLINDER %u - HEAD %u - SECTOR # %u - SECTOR_SIZE %u ) ***\n", logerror("...** READ FAILED WITH STATUS %u ** (CYLINDER %u - HEAD %u - SECTOR # %u - SECTOR_SIZE %u ) ***\n",
read_status, cylinder, SDH & 0x07, sector_number, SECTOR_SIZES[(SDH >> 5) & 0x03] read_status, cylinder, sdh & 0x07, sector_number, SECTOR_SIZES[(sdh >> 5) & 0x03]
); );
} }
@ -1815,9 +1817,7 @@ WRITE_LINE_MEMBER(rainbow_state::hdc_write_sector)
int drv = ((m_hdc->read(generic_space(), 0x06)) & (8 + 16)) >> 3; // get DRIVE from SDH register int drv = ((m_hdc->read(generic_space(), 0x06)) & (8 + 16)) >> 3; // get DRIVE from SDH register
if (((state == 0) && (wg_last == 1)) // Check correct state transition and DRIVE 0 .... if (state == 0 && wg_last == 1 && drv == 0) // Check correct state transition and DRIVE 0 ....
&& (drv == 0)
)
{ {
output().set_value("led1", 0); // (1 = OFF ) =HARD DISK ACTIVITY = output().set_value("led1", 0); // (1 = OFF ) =HARD DISK ACTIVITY =
switch_off_timer->adjust(attotime::from_msec(500)); switch_off_timer->adjust(attotime::from_msec(500));
@ -1859,18 +1859,17 @@ int rainbow_state::do_write_sector()
output().set_value("led1", 0); // ON output().set_value("led1", 0); // ON
switch_off_timer->adjust(attotime::from_msec(500)); switch_off_timer->adjust(attotime::from_msec(500));
hard_disk_file *local_hard_disk; hard_disk_file *local_hard_disk = rainbow_hdc_file(0); // one hard disk for now.
local_hard_disk = rainbow_hdc_file(0); // one hard disk for now.
if (local_hard_disk) if (local_hard_disk)
{ {
hard_disk_info *info; hard_disk_info *info = hard_disk_get_info(local_hard_disk);
if ((info = hard_disk_get_info(local_hard_disk))) if (info)
{ {
feedback = 10; feedback = 10;
output().set_value("led1", 1); // OFF output().set_value("led1", 1); // OFF
uint8_t SDH = (m_hdc->read(generic_space(), 0x06)); uint8_t sdh = (m_hdc->read(generic_space(), 0x06));
int hi = (m_hdc->read(generic_space(), 0x05)) & 0x07; int hi = (m_hdc->read(generic_space(), 0x05)) & 0x07;
uint16_t cylinder = (m_hdc->read(generic_space(), 0x04)) | (hi << 8); uint16_t cylinder = (m_hdc->read(generic_space(), 0x04)) | (hi << 8);
@ -1878,17 +1877,16 @@ int rainbow_state::do_write_sector()
int sector_number = m_hdc->read(generic_space(), 0x03); int sector_number = m_hdc->read(generic_space(), 0x03);
int sector_count = m_hdc->read(generic_space(), 0x02); // (1 = single sector) int sector_count = m_hdc->read(generic_space(), 0x02); // (1 = single sector)
if (!((cylinder <= info->cylinders) && // filter invalid cylinders if (!(cylinder <= info->cylinders && // filter invalid cylinders
(SECTOR_SIZES[(SDH >> 5) & 0x03] == info->sectorbytes) // 512, may not vary SECTOR_SIZES[(sdh >> 5) & 0x03] == info->sectorbytes // 512, may not vary
)) ))
{ {
logerror("...*** SANITY CHECK FAILED (CYLINDER %u vs. info->cylinders %u - - SECTOR_SIZE %u vs. info->sectorbytes %u) ***\n", logerror("...*** SANITY CHECK FAILED (CYLINDER %u vs. info->cylinders %u - - SECTOR_SIZE %u vs. info->sectorbytes %u) ***\n",
cylinder, info->cylinders, SECTOR_SIZES[(SDH >> 5) & 0x03], info->sectorbytes cylinder, info->cylinders, SECTOR_SIZES[(sdh >> 5) & 0x03], info->sectorbytes);
);
return 50; return 50;
} }
// Pointer to info + C + H + S // Pointer to info + C + H + S
uint32_t lbasector = get_and_print_lbasector(this, info, cylinder, SDH & 0x07, sector_number); uint32_t lbasector = get_and_print_lbasector(this, info, cylinder, sdh & 0x07, sector_number);
if (sector_count != 1) // ignore all SECTOR_COUNTS != 1 if (sector_count != 1) // ignore all SECTOR_COUNTS != 1
return 88; // logerror(" - ** IGNORED (SECTOR_COUNT !=1) **\n"); return 88; // logerror(" - ** IGNORED (SECTOR_COUNT !=1) **\n");
@ -1944,7 +1942,7 @@ READ8_MEMBER(rainbow_state::hd_status_68_r)
{ {
// (*) Bits 5-7 : HARD WIRED IDENTIFICATION BITS, bits 5+7 = 1 and bit 6 = 0 (= 101 f?r RD51 module) // (*) Bits 5-7 : HARD WIRED IDENTIFICATION BITS, bits 5+7 = 1 and bit 6 = 0 (= 101 f?r RD51 module)
int data = 0xe0; // 111 gives DRIVE NOT READY (when W is pressed on boot screen) int data = 0xe0; // 111 gives DRIVE NOT READY (when W is pressed on boot screen)
if ((m_inp5->read() == 0x01) && (rainbow_hdc_file(0) != nullptr)) if (m_inp5->read() == 0x01 && rainbow_hdc_file(0) != nullptr)
data = 0xa0; // A0 : OK, DRIVE IS READY (!) data = 0xa0; // A0 : OK, DRIVE IS READY (!)
int my_offset = 0x07; int my_offset = 0x07;
@ -2048,16 +2046,16 @@ positioned over cylinder 0 (the data track furthest away from the spindle).
*/ */
READ8_MEMBER(rainbow_state::hd_status_69_r) READ8_MEMBER(rainbow_state::hd_status_69_r)
{ {
int HS = m_hdc->read(space, 0x06) & (1 + 2 + 4); // SDH bits 0-2 = HEAD # int hs = m_hdc->read(space, 0x06) & (1 + 2 + 4); // SDH bits 0-2 = HEAD #
// logerror("(x69 READ) %i = HEAD SELECT WD1010\n", HS); // logerror("(x69 READ) %i = HEAD SELECT WD1010\n", hs);
uint8_t data = (HS << 1); uint8_t data = (hs << 1);
// DRIVE SELECT: 2 bits in SDH register of WDx010 could address 4 drives. // DRIVE SELECT: 2 bits in SDH register of WDx010 could address 4 drives.
// External circuit supports 1 drive here (DRIVE 0 selected or deselected) // External circuit supports 1 drive here (DRIVE 0 selected or deselected)
int DRV = ((m_hdc->read(space, 0x06) >> 3) & 0x01); // 0x03 gives error R6 with DIAG.DISK int drv = ((m_hdc->read(space, 0x06) >> 3) & 0x01); // 0x03 gives error R6 with DIAG.DISK
if (DRV == 0) if (drv == 0)
data |= 1; // logerror("(x69 READ) %i = _DRIVE # 0_ SELECT! \n", DRV); data |= 1; // logerror("(x69 READ) %i = _DRIVE # 0_ SELECT! \n", drv);
if (m_hdc_write_gate) // WRITE GATE (cached here) if (m_hdc_write_gate) // WRITE GATE (cached here)
data |= 16; data |= 16;
@ -2103,7 +2101,7 @@ READ_LINE_MEMBER(rainbow_state::hdc_write_fault)
WRITE_LINE_MEMBER(rainbow_state::hdc_bcr) WRITE_LINE_MEMBER(rainbow_state::hdc_bcr)
{ {
static int bcr_state; static int bcr_state;
if ((bcr_state == 0) && (state == 1)) if (bcr_state == 0 && state == 1)
hdc_buffer_counter_reset(); hdc_buffer_counter_reset();
bcr_state = state; bcr_state = state;
} }
@ -2125,7 +2123,7 @@ WRITE_LINE_MEMBER(rainbow_state::hdc_bdrq)
static int old_state; static int old_state;
// logerror("BDRQ - BUFFER DATA REQUEST OBTAINED: %u\n", state); // logerror("BDRQ - BUFFER DATA REQUEST OBTAINED: %u\n", state);
if ((state == 1) && (old_state == 0)) if (state == 1 && old_state == 0)
{ {
hdc_buffer_counter_reset(); hdc_buffer_counter_reset();
@ -2174,15 +2172,14 @@ READ8_MEMBER(rainbow_state::system_parameter_r)
M : old RAM extension (128 / 192 K ?) detected with OPTION_PRESENT bit, newer models 'by presence'. M : old RAM extension (128 / 192 K ?) detected with OPTION_PRESENT bit, newer models 'by presence'.
BIOS uses a seperate IRQ vector for RAM board detection (at least on a 100-B). BIOS uses a seperate IRQ vector for RAM board detection (at least on a 100-B).
*/ */
return (((m_inp5->read() == 1) ? 0 : 1) | return ((m_inp5->read() == 1 ? 0 : 1) |
((m_inp7->read() == 1) ? 0 : 4) | // Floppy is always present (bit 1 zero) (m_inp7->read() == 1 ? 0 : 4) | // Floppy is always present (bit 1 zero)
#ifdef OLD_RAM_BOARD_PRESENT #ifdef OLD_RAM_BOARD_PRESENT
((m_inp8->read() > MOTHERBOARD_RAM) ? 0 : 8) | (m_inp8->read() > MOTHERBOARD_RAM ? 0 : 8) |
#else #else
8 | // unverified 8 | // unverified
#endif #endif
16 | 32 | 64 | 128 // unverified 16 | 32 | 64 | 128); // unverified
);
} }
// [02] COMMUNICATIONS STATUS REGISTER - PAGE 154 (**** READ **** ) // [02] COMMUNICATIONS STATUS REGISTER - PAGE 154 (**** READ **** )
@ -2197,19 +2194,17 @@ READ8_MEMBER(rainbow_state::system_parameter_r)
READ8_MEMBER(rainbow_state::comm_control_r) READ8_MEMBER(rainbow_state::comm_control_r)
{ {
bool is_mhfu_enabled = false; bool is_mhfu_enabled = false;
if (m_POWER_GOOD) if (m_power_good)
is_mhfu_enabled = m_crtc->MHFU(MHFU_IS_ENABLED); is_mhfu_enabled = m_crtc->MHFU(MHFU_IS_ENABLED);
return ( return (m_comm_port->ri_r() ? 0x01 : 0x00) |
(m_comm_port->ri_r() ? 0x01 : 0x00) |
(m_comm_port->si_r() ? 0x02 : 0x00) | (m_comm_port->si_r() ? 0x02 : 0x00) |
(m_comm_port->dsr_r() ? 0x04 : 0x00) | (m_comm_port->dsr_r() ? 0x04 : 0x00) |
(m_comm_port->cts_r() ? 0x08 : 0x00) | (m_comm_port->cts_r() ? 0x08 : 0x00) |
(m_comm_port->dcd_r() ? 0x10 : 0x00) | (m_comm_port->dcd_r() ? 0x10 : 0x00) |
(is_mhfu_enabled ? 0x00 : 0x20) | // (L) status of MHFU flag => bit pos.5 (is_mhfu_enabled ? 0x00 : 0x20) | // (L) status of MHFU flag => bit pos.5
((INT88) ? 0x00 : 0x40) | // (L) (m_int88 ? 0x00 : 0x40) | // (L)
((INTZ80) ? 0x00 : 0x80) // (L) (m_intz80 ? 0x00 : 0x80); // (L)
);
} }
@ -2251,7 +2246,7 @@ WRITE8_MEMBER(rainbow_state::i8088_latch_w)
m_z80->set_input_line_and_vector(0, ASSERT_LINE, 0xf7); m_z80->set_input_line_and_vector(0, ASSERT_LINE, 0xf7);
m_z80_mailbox = data; m_z80_mailbox = data;
INTZ80 = true; // m_intz80 = true;
} }
// Z80 reads port 0x00 // Z80 reads port 0x00
@ -2261,7 +2256,7 @@ READ8_MEMBER(rainbow_state::z80_latch_r)
// logerror("Read %02x from Z80 mailbox\n", m_z80_mailbox); // logerror("Read %02x from Z80 mailbox\n", m_z80_mailbox);
m_z80->set_input_line(0, CLEAR_LINE); m_z80->set_input_line(0, CLEAR_LINE);
INTZ80 = false; m_intz80 = false;
return m_z80_mailbox; return m_z80_mailbox;
} }
@ -2273,7 +2268,7 @@ WRITE8_MEMBER(rainbow_state::z80_latch_w)
raise_8088_irq(IRQ_8088_MAILBOX); raise_8088_irq(IRQ_8088_MAILBOX);
m_8088_mailbox = data; m_8088_mailbox = data;
INT88 = true; m_int88 = true;
} }
// 8088 reads port 0x00. See page 133 (4-34) // 8088 reads port 0x00. See page 133 (4-34)
@ -2282,7 +2277,7 @@ READ8_MEMBER(rainbow_state::i8088_latch_r)
// logerror("Read %02x from 8088 mailbox\n", m_8088_mailbox); // logerror("Read %02x from 8088 mailbox\n", m_8088_mailbox);
lower_8088_irq(IRQ_8088_MAILBOX); lower_8088_irq(IRQ_8088_MAILBOX);
INT88 = false; m_int88 = false;
return m_8088_mailbox; return m_8088_mailbox;
} }
@ -2355,20 +2350,18 @@ READ8_MEMBER(rainbow_state::z80_generalstat_r)
if ((fdc_status & 0x80) == 0) // (see WD_FDC: S_WP = 0x40, S_NRDY = 0x80, S_TR00 = 0x04) if ((fdc_status & 0x80) == 0) // (see WD_FDC: S_WP = 0x40, S_NRDY = 0x80, S_TR00 = 0x04)
fdc_ready = 1; fdc_ready = 1;
if ( fdc_ready && ((fdc_status & 0x40) == 0) && m_POWER_GOOD ) if (fdc_ready && ((fdc_status & 0x40) == 0) && m_power_good)
fdc_write_gate = 1; // "valid only when drive is selected" ! fdc_write_gate = 1; // "valid only when drive is selected" !
} }
// logerror(" RDY:%x WG:%d ",fdc_ready,fdc_write_gate); // logerror(" RDY:%x WG:%d ",fdc_ready,fdc_write_gate);
int data = ( int data = (fdc_step ? 0x00 : 0x80) |
((fdc_step) ? 0x00 : 0x80) | (fdc_write_gate ? 0x00 : 0x40) |
((fdc_write_gate) ? 0x00 : 0x40) | (tk00 ? 0x20 : 0x00) | // ***** ALL LOW ACTIVE - EXCEPT tk00 :
((tk00) ? 0x20 : 0x00) | // ***** ALL LOW ACTIVE - EXCEPT tk00 : (last_dir ? 0x00 : 0x10) |
((last_dir) ? 0x00 : 0x10) | (fdc_ready ? 0x00 : 0x08) |
((fdc_ready) ? 0x00 : 0x08) | (m_int88 ? 0x00 : 0x04) |
((INT88) ? 0x00 : 0x04) | (m_intz80 ? 0x00 : 0x02) |
((INTZ80) ? 0x00 : 0x02) | (m_zflip ? 0x00 : 0x01);
((m_zflip) ? 0x00 : 0x01)
);
return data; return data;
} }
@ -2555,23 +2548,21 @@ IRQ_CALLBACK_MEMBER(rainbow_state::irq_callback)
WRITE_LINE_MEMBER(rainbow_state::GDC_vblank_irq) WRITE_LINE_MEMBER(rainbow_state::GDC_vblank_irq)
{ {
// VERIFICATION NEEDED: IRQ raised before or after new palette loaded...? // VERIFICATION NEEDED: IRQ raised before or after new palette loaded...?
if(m_GDC_MODE_REGISTER & GDC_MODE_ENABLE_VSYNC_IRQ) // 0x40 if (m_gdc_mode_register & GDC_MODE_ENABLE_VSYNC_IRQ) // 0x40
raise_8088_irq(IRQ_GRF_INTR_L); raise_8088_irq(IRQ_GRF_INTR_L);
else else
lower_8088_irq(IRQ_GRF_INTR_L); lower_8088_irq(IRQ_GRF_INTR_L);
uint8_t xi, red, green, blue, mono;
m_monitor_suggested = m_inp13->read(); m_monitor_suggested = m_inp13->read();
if((m_monitor_suggested < 1) || (m_monitor_suggested > 3)) if (m_monitor_suggested < 1 || m_monitor_suggested > 3)
m_monitor_suggested = COLOR_MONITOR; m_monitor_suggested = COLOR_MONITOR;
int mono_sum = 0; int mono_sum = 0;
int green_sum = 0; int green_sum = 0;
for(xi=0;xi<16;xi++) // DELAYED LOAD OF PALETTE ... for (uint8_t xi = 0; xi < 16; xi++) // DELAYED LOAD OF PALETTE ...
{ {
uint8_t colordata1 = m_GDC_COLOR_MAP[xi]; uint8_t colordata1 = m_gdc_color_map[xi];
uint8_t colordata2 = m_GDC_COLOR_MAP[xi + 16]; // Does it matter if the palette is incomplete...? uint8_t colordata2 = m_gdc_color_map[xi + 16]; // Does it matter if the palette is incomplete...?
// Color map: 32 x 8 // Color map: 32 x 8
// 2nd 16 Byte 1st 16 Bytes (colordata1) // 2nd 16 Byte 1st 16 Bytes (colordata1)
@ -2580,19 +2571,18 @@ WRITE_LINE_MEMBER(rainbow_state::GDC_vblank_irq)
// Mono Blue Red Green // Mono Blue Red Green
// NOTE: 2nd 16 BYTES ARE MONO PALETTE, 1st 16 ARE COLOR PALETTE * HERE * (on the VT240 driver, it is the other way round) // NOTE: 2nd 16 BYTES ARE MONO PALETTE, 1st 16 ARE COLOR PALETTE * HERE * (on the VT240 driver, it is the other way round)
mono = (colordata2 & 0xF0) >> 4; // FIXME: limit palette in appropriate modes on 100-A uint8_t mono = (colordata2 & 0xF0) >> 4; // FIXME: limit palette in appropriate modes on 100-A
mono_sum += mono; mono_sum += mono;
blue = (colordata2 & 0x0F); uint8_t blue = (colordata2 & 0x0F);
red = (colordata1 & 0xF0) >> 4; uint8_t red = (colordata1 & 0xF0) >> 4;
green =(colordata1 & 0x0F); uint8_t green =(colordata1 & 0x0F);
green_sum += green; green_sum += green;
switch (m_monitor_suggested) switch (m_monitor_suggested)
{ {
case MONO_MONITOR: case MONO_MONITOR:
{
switch (m_inp9->read()) // - monochrome monitor (phosphor) type (1,2,3) switch (m_inp9->read()) // - monochrome monitor (phosphor) type (1,2,3)
{ {
case 1: // BLACK & WHITE case 1: // BLACK & WHITE
@ -2614,10 +2604,9 @@ WRITE_LINE_MEMBER(rainbow_state::GDC_vblank_irq)
break; break;
} }
break; break;
}
case COLOR_MONITOR: case COLOR_MONITOR:
if(!(m_GDC_MODE_REGISTER & GDC_MODE_ENABLE_VIDEO)) if (!(m_gdc_mode_register & GDC_MODE_ENABLE_VIDEO))
red = blue = 0; // Page 21 of AA-AE36A (PDF) explains why red = blue = 0; // Page 21 of AA-AE36A (PDF) explains why
m_palette2->set_pen_color(xi, pal4bit(red) , pal4bit(mono) , pal4bit(blue)); m_palette2->set_pen_color(xi, pal4bit(red) , pal4bit(mono) , pal4bit(blue));
@ -2627,10 +2616,9 @@ WRITE_LINE_MEMBER(rainbow_state::GDC_vblank_irq)
m_palette2->set_pen_color(xi, pal4bit(red), pal4bit(green), pal4bit(blue)); m_palette2->set_pen_color(xi, pal4bit(red), pal4bit(green), pal4bit(blue));
break; break;
} }
} // palette (loop) } // palette (loop)
if( (green_sum >0) && (green_sum == mono_sum) ) // (R-G-B + M) palette (split cable). Examples: PACMAN, AutoCad if (green_sum > 0 && green_sum == mono_sum) // (R-G-B + M) palette (split cable). Examples: PACMAN, AutoCad
{ {
if (m_monitor_suggested == MONO_MONITOR) if (m_monitor_suggested == MONO_MONITOR)
logerror("\n[HINT: COLOR PALETTE DETECTED - SUITABLE FOR DUAL MONITOR] "); logerror("\n[HINT: COLOR PALETTE DETECTED - SUITABLE FOR DUAL MONITOR] ");
@ -2638,7 +2626,7 @@ WRITE_LINE_MEMBER(rainbow_state::GDC_vblank_irq)
m_monitor_suggested = DUAL_MONITOR; m_monitor_suggested = DUAL_MONITOR;
} }
if((green_sum == 0) && (mono_sum > 0)) // No green = original DEC spec. Example: NLANDER. All older libaries use R-M-B. if (green_sum == 0 && mono_sum > 0) // No green = original DEC spec. Example: NLANDER. All older libaries use R-M-B.
{ {
if (m_inp13->read() == AUTODETECT_MONITOR) if (m_inp13->read() == AUTODETECT_MONITOR)
m_monitor_suggested = COLOR_MONITOR; m_monitor_suggested = COLOR_MONITOR;
@ -2656,7 +2644,7 @@ WRITE_LINE_MEMBER(rainbow_state::video_interrupt)
else else
lower_8088_irq(IRQ_8088_VBL); lower_8088_irq(IRQ_8088_VBL);
if (state == ASSERT_LINE && m_POWER_GOOD && m_crtc->MHFU(MHFU_IS_ENABLED)) // If enabled... if (state == ASSERT_LINE && m_power_good && m_crtc->MHFU(MHFU_IS_ENABLED)) // If enabled...
{ {
if (m_crtc->MHFU(MHFU_VALUE) > 10) // + more than (10 * 16.666) msecs gone (108 ms would be by the book) if (m_crtc->MHFU(MHFU_VALUE) > 10) // + more than (10 * 16.666) msecs gone (108 ms would be by the book)
{ {
@ -2672,11 +2660,7 @@ WRITE_LINE_MEMBER(rainbow_state::video_interrupt)
// Reflects bits from 'diagnostic_w' (1:1), except test jumpers // Reflects bits from 'diagnostic_w' (1:1), except test jumpers
READ8_MEMBER(rainbow_state::diagnostic_r) // 8088 (port 0A READ). Fig.4-29 + table 4-15 READ8_MEMBER(rainbow_state::diagnostic_r) // 8088 (port 0A READ). Fig.4-29 + table 4-15
{ {
return ((m_diagnostic & (0xf1)) | return ((m_diagnostic & 0xf1) | m_inp1->read() | m_inp2->read() | m_inp3->read());
m_inp1->read() |
m_inp2->read() |
m_inp3->read()
);
} }
WRITE8_MEMBER(rainbow_state::diagnostic_w) // 8088 (port 0A WRITTEN). Fig.4-28 + table 4-15 WRITE8_MEMBER(rainbow_state::diagnostic_w) // 8088 (port 0A WRITTEN). Fig.4-28 + table 4-15
@ -2711,19 +2695,21 @@ WRITE8_MEMBER(rainbow_state::diagnostic_w) // 8088 (port 0A WRITTEN). Fig.4-28 +
m_fdc->reset(); // See formatter description p.197 or 5-13 m_fdc->reset(); // See formatter description p.197 or 5-13
} }
m_SCREEN_BLANK = (data & 2) ? false : true; m_screen_blank = BIT(data, 1);
// Switch determines how the monochrome output pin is taken from: // Switch determines how the monochrome output pin is taken from:
// 0 = M(ono) out from system module (DC011/DC012). Default, also used to setup dual monitors. // 0 = M(ono) out from system module (DC011/DC012). Default, also used to setup dual monitors.
// 1 = M(ono) output from GRAPHICS OPTION. (G)reen remains unused with a single COLOR monitor. // 1 = M(ono) output from GRAPHICS OPTION. (G)reen remains unused with a single COLOR monitor.
m_ONBOARD_GRAPHICS_SELECTED = (data & 0x04) ? false : true; m_onboard_graphics_selected = (data & 0x04) ? false : true;
if(!m_ONBOARD_GRAPHICS_SELECTED) if (!m_onboard_graphics_selected)
{ {
if (m_inp7->read() == 1) if (m_inp7->read() == 1)
{
printf("\nHINT: GRAPHICS OPTION ON. TEXT ONLY (DC011/DC012) OUTPUT NOW DISABLED.\n"); printf("\nHINT: GRAPHICS OPTION ON. TEXT ONLY (DC011/DC012) OUTPUT NOW DISABLED.\n");
}
else else
{ printf("\nALARM: GRAPHICS OPTION * SWITCHED OFF * VIA DIP. TEXT OUTPUT STILL ENABLED!\n"); { printf("\nALARM: GRAPHICS OPTION * SWITCHED OFF * VIA DIP. TEXT OUTPUT STILL ENABLED!\n");
m_ONBOARD_GRAPHICS_SELECTED = true; m_onboard_graphics_selected = true;
} }
logerror("DATA: %x (PC=%x)\n", data, m_i8088->pc()); logerror("DATA: %x (PC=%x)\n", data, m_i8088->pc());
} }
@ -2821,7 +2807,7 @@ WRITE_LINE_MEMBER(rainbow_state::kbd_txready_w)
TIMER_DEVICE_CALLBACK_MEMBER(rainbow_state::hd_motor_tick) TIMER_DEVICE_CALLBACK_MEMBER(rainbow_state::hd_motor_tick)
{ {
if (m_POWER_GOOD) if (m_power_good)
m_crtc->MHFU(MHFU_COUNT); // // Increment IF ENABLED and POWER_GOOD, return count m_crtc->MHFU(MHFU_COUNT); // // Increment IF ENABLED and POWER_GOOD, return count
m_hdc_index_latch = true; // HDC drive index signal (not working ?) m_hdc_index_latch = true; // HDC drive index signal (not working ?)
@ -2846,18 +2832,18 @@ WRITE_LINE_MEMBER(rainbow_state::irq_hi_w)
READ16_MEMBER(rainbow_state::vram_r) READ16_MEMBER(rainbow_state::vram_r)
{ {
if((!(m_GDC_MODE_REGISTER & GDC_MODE_VECTOR)) || machine().side_effects_disabled()) // (NOT VECTOR MODE) if ((!(m_gdc_mode_register & GDC_MODE_VECTOR)) || machine().side_effects_disabled()) // (NOT VECTOR MODE)
{ {
// SCROLL_MAP IN BITMAP MODE ONLY...? // SCROLL_MAP IN BITMAP MODE ONLY...?
if(m_GDC_MODE_REGISTER & GDC_MODE_HIGHRES) if (m_gdc_mode_register & GDC_MODE_HIGHRES)
offset = ( m_GDC_SCROLL_BUFFER[ (offset & 0x3FC0) >> 6 ] << 6) | (offset & 0x3F); offset = (m_gdc_scroll_buffer[(offset & 0x3FC0) >> 6] << 6) | (offset & 0x3F);
else else
offset = ( m_GDC_SCROLL_BUFFER[ (offset & 0x1FC0) >> 6 ] << 6) | (offset & 0x3F); offset = (m_gdc_scroll_buffer[(offset & 0x1FC0) >> 6] << 6) | (offset & 0x3F);
int readback_plane = 0; int readback_plane = 0;
if( !(m_GDC_MODE_REGISTER & GDC_MODE_ENABLE_WRITES) ) // 0x10 // READBACK OPERATION - if ENABLE_WRITES NOT SET if (!(m_gdc_mode_register & GDC_MODE_ENABLE_WRITES)) // 0x10 // READBACK OPERATION - if ENABLE_WRITES NOT SET
readback_plane = (m_GDC_MODE_REGISTER & GDC_MODE_READBACK_PLANE_MASK) >> 2; // READBACK PLANE 00..02, mask in bits 2+3 readback_plane = (m_gdc_mode_register & GDC_MODE_READBACK_PLANE_MASK) >> 2; // READBACK PLANE 00..02, mask in bits 2+3
return m_video_ram[ (offset & 0x7fff) + (0x8000 * readback_plane)]; return m_video_ram[ (offset & 0x7fff) + (0x8000 * readback_plane)];
} }
@ -2867,15 +2853,15 @@ READ16_MEMBER(rainbow_state::vram_r)
// NOTE: Rainbow has separate registers for fore and background. // NOTE: Rainbow has separate registers for fore and background.
WRITE16_MEMBER(rainbow_state::vram_w) WRITE16_MEMBER(rainbow_state::vram_w)
{ {
if(m_GDC_MODE_REGISTER & GDC_MODE_HIGHRES) if (m_gdc_mode_register & GDC_MODE_HIGHRES)
offset = ( m_GDC_SCROLL_BUFFER[ (offset & 0x3FC0) >> 6 ] << 6) | (offset & 0x3F); offset = (m_gdc_scroll_buffer[(offset & 0x3FC0) >> 6] << 6) | (offset & 0x3F);
else else
offset = ( m_GDC_SCROLL_BUFFER[ (offset & 0x1FC0) >> 6 ] << 6) | (offset & 0x3F); offset = (m_gdc_scroll_buffer[(offset & 0x1FC0) >> 6] << 6) | (offset & 0x3F);
offset &= 0xffff; // same as in VT240? offset &= 0xffff; // same as in VT240?
uint16_t chr = data; // VT240 : uint8_t uint16_t chr = data; // VT240 : uint8_t
if(m_GDC_MODE_REGISTER & GDC_MODE_VECTOR) // VT240 : if(SELECT_VECTOR_PATTERN_REGISTER) if (m_gdc_mode_register & GDC_MODE_VECTOR) // VT240 : if(SELECT_VECTOR_PATTERN_REGISTER)
{ {
chr = bitswap<8>(m_vpat, m_patidx, m_patidx, m_patidx, m_patidx, m_patidx, m_patidx, m_patidx, m_patidx); chr = bitswap<8>(m_vpat, m_patidx, m_patidx, m_patidx, m_patidx, m_patidx, m_patidx, m_patidx, m_patidx);
chr |= (chr << 8); chr |= (chr << 8);
@ -2888,20 +2874,20 @@ WRITE16_MEMBER(rainbow_state::vram_w)
} }
else else
{ {
chr = m_GDC_WRITE_BUFFER[ m_GDC_write_buffer_index++ ]; chr = m_gdc_write_buffer[ m_gdc_write_buffer_index++ ];
m_GDC_write_buffer_index &= 0xf; m_gdc_write_buffer_index &= 0xf;
chr |= (m_GDC_WRITE_BUFFER[m_GDC_write_buffer_index++] << 8); chr |= (m_gdc_write_buffer[m_gdc_write_buffer_index++] << 8);
m_GDC_write_buffer_index &= 0xf; m_gdc_write_buffer_index &= 0xf;
} }
if(m_GDC_MODE_REGISTER & GDC_MODE_ENABLE_WRITES) // 0x10 if (m_gdc_mode_register & GDC_MODE_ENABLE_WRITES) // 0x10
{ {
// ALU_PS register: controls logic used in writing to the bitmap / inhibiting of writing to specified planes. // ALU_PS register: controls logic used in writing to the bitmap / inhibiting of writing to specified planes.
// plane select and logic operations on write buffer... (and more) **** SEE PAGE 36 **** // plane select and logic operations on write buffer... (and more) **** SEE PAGE 36 ****
int ps = m_GDC_ALU_PS_REGISTER & 0x0F; // PLANE SELECT 0..3 // VT 240 : ~m_GDC_ALU_PS_REGISTER & 3; int ps = m_gdc_alu_ps_register & 0x0F; // PLANE SELECT 0..3 // VT 240 : ~m_gdc_alu_ps_register & 3;
uint8_t fore = ( (m_GDC_FG_BG & 0xf0) ) >> 4; uint8_t fore = ((m_gdc_fg_bg & 0xf0)) >> 4;
uint8_t back = (m_GDC_FG_BG & 0x0f); // background : 0..3 confirmed, see p.39 AA-AE36A (PDF) uint8_t back = (m_gdc_fg_bg & 0x0f); // background : 0..3 confirmed, see p.39 AA-AE36A (PDF)
for (int i = 0; i <= 3; i++) for (int i = 0; i <= 3; i++)
{ {
@ -2913,7 +2899,7 @@ WRITE16_MEMBER(rainbow_state::vram_w)
for (int j = 0; j <= 15; j++) // REPLACE MODE : one replaced by FG, zero by BG ( 16 instead of 8 bit on VT240 ) for (int j = 0; j <= 15; j++) // REPLACE MODE : one replaced by FG, zero by BG ( 16 instead of 8 bit on VT240 )
out |= BIT(chr, j) ? ((fore & 1) << j) : ((back & 1) << j); out |= BIT(chr, j) ? ((fore & 1) << j) : ((back & 1) << j);
switch ((m_GDC_ALU_PS_REGISTER) & ALU_PS_MODE_MASK) switch ((m_gdc_alu_ps_register) & ALU_PS_MODE_MASK)
{ {
case OVERLAY_MODE: // (OR) case OVERLAY_MODE: // (OR)
out |= mem; out |= mem;
@ -2927,12 +2913,12 @@ WRITE16_MEMBER(rainbow_state::vram_w)
break; break;
} }
if(!(m_GDC_MODE_REGISTER & GDC_MODE_VECTOR)) // 0 : Text Mode and Write Mask Batch if (!(m_gdc_mode_register & GDC_MODE_VECTOR)) // 0 : Text Mode and Write Mask Batch
out = (out & ~m_GDC_WRITE_MASK) | (mem & m_GDC_WRITE_MASK); out = (out & ~m_gdc_write_mask) | (mem & m_gdc_write_mask);
else else
out = (out & ~data) | (mem & data); out = (out & ~data) | (mem & data);
if(m_GDC_MODE_REGISTER & GDC_MODE_ENABLE_WRITES) // 0x10 if (m_gdc_mode_register & GDC_MODE_ENABLE_WRITES) // 0x10
m_video_ram[(offset & 0xffff) + (0x8000 * i)] = out; m_video_ram[(offset & 0xffff) + (0x8000 * i)] = out;
} // if plane selected } // if plane selected
@ -2952,19 +2938,19 @@ READ8_MEMBER(rainbow_state::GDC_EXTRA_REGISTER_r)
switch (offset) switch (offset)
{ {
case 0: case 0:
data = m_GDC_MODE_REGISTER; // ? data = m_gdc_mode_register; // ?
break; break;
case 1: case 1:
if(m_GDC_INDIRECT_REGISTER & GDC_SELECT_SCROLL_MAP ) // 0x80 if (m_gdc_indirect_register & GDC_SELECT_SCROLL_MAP ) // 0x80
{ {
// Documentation says it is always incremented (read and write): // Documentation says it is always incremented (read and write):
data = m_GDC_SCROLL_BUFFER[m_GDC_scroll_index++]; // // * READ * SCROLL_MAP ( 256 x 8 ) data = m_gdc_scroll_buffer[m_gdc_scroll_index++]; // // * READ * SCROLL_MAP ( 256 x 8 )
m_GDC_scroll_index &= 0xFF; // 0...255 (CPU accesses 256 bytes) m_gdc_scroll_index &= 0xFF; // 0...255 (CPU accesses 256 bytes)
break; break;
} }
else else
logerror("\n * UNEXPECTED CASE: READ REGISTER 50..55 with INDIRECT_REGISTER $%02x and OFFSET $%02x *", m_GDC_INDIRECT_REGISTER, offset); logerror("\n * UNEXPECTED CASE: READ REGISTER 50..55 with INDIRECT_REGISTER $%02x and OFFSET $%02x *", m_gdc_indirect_register, offset);
break; break;
case 6: case 6:
@ -2976,7 +2962,7 @@ READ8_MEMBER(rainbow_state::GDC_EXTRA_REGISTER_r)
break; break;
default: default:
logerror("\n * UNHANDLED CASE: READ REGISTER 50..55 with INDIRECT_REGISTER $%02x and OFFSET $%02x *", m_GDC_INDIRECT_REGISTER, offset); logerror("\n * UNHANDLED CASE: READ REGISTER 50..55 with INDIRECT_REGISTER $%02x and OFFSET $%02x *", m_gdc_indirect_register, offset);
break; break;
} // switch } // switch
return data; return data;
@ -2987,6 +2973,7 @@ WRITE8_MEMBER(rainbow_state::GDC_EXTRA_REGISTER_w)
static int last_message, last_mode, last_readback, last_scroll_index; static int last_message, last_mode, last_readback, last_scroll_index;
if (offset > 0) // Port $50 reset done @ boot ROM 1EB4/8 regardless if option present. if (offset > 0) // Port $50 reset done @ boot ROM 1EB4/8 regardless if option present.
{
if (m_inp7->read() != 1) if (m_inp7->read() != 1)
{ {
if (last_message != 1) if (last_message != 1)
@ -2997,6 +2984,7 @@ WRITE8_MEMBER(rainbow_state::GDC_EXTRA_REGISTER_w)
} }
return; return;
} }
}
switch (offset) switch (offset)
{ {
@ -3013,27 +3001,27 @@ WRITE8_MEMBER(rainbow_state::GDC_EXTRA_REGISTER_w)
break; break;
case 1: // 51h = DATA loaded into (a register previously addressed by a write to 53h) case 1: // 51h = DATA loaded into (a register previously addressed by a write to 53h)
if(m_GDC_INDIRECT_REGISTER & GDC_SELECT_WRITE_BUFFER) // 0x01 if (m_gdc_indirect_register & GDC_SELECT_WRITE_BUFFER) // 0x01
{ {
m_GDC_write_buffer_index = 0; // (writing to 51h CLEARS the index counter) m_gdc_write_buffer_index = 0; // (writing to 51h CLEARS the index counter)
break; break;
} }
if(m_GDC_INDIRECT_REGISTER & GDC_SELECT_COLOR_MAP ) // 0x20 if (m_gdc_indirect_register & GDC_SELECT_COLOR_MAP) // 0x20
{ {
m_GDC_COLOR_MAP[m_GDC_color_map_index++] = ~data; // tilde data verified by DIAGNOSTIC! m_gdc_color_map[m_gdc_color_map_index++] = ~data; // tilde data verified by DIAGNOSTIC!
if(m_GDC_color_map_index == 32) if (m_gdc_color_map_index == 32)
{ {
m_GDC_color_map_index = 0; // 0...31 (CPU accesses 32 bytes m_gdc_color_map_index = 0; // 0...31 (CPU accesses 32 bytes
printf("\n * COLOR MAP FULLY LOADED *"); printf("\n * COLOR MAP FULLY LOADED *");
for (int zi = 0; zi < 16; zi++) for (int zi = 0; zi < 16; zi++)
{ {
int g = m_GDC_COLOR_MAP[zi] & 0x0F; int g = m_gdc_color_map[zi] & 0x0F;
int r = (m_GDC_COLOR_MAP[zi] & 0xF0) >> 4; int r = (m_gdc_color_map[zi] & 0xF0) >> 4;
int b = m_GDC_COLOR_MAP[zi + 16] & 0x0F; int b = m_gdc_color_map[zi + 16] & 0x0F;
int m = (m_GDC_COLOR_MAP[zi + 16] & 0xF0) >> 4; int m = (m_gdc_color_map[zi + 16] & 0xF0) >> 4;
printf("\n[%d] %1x %1x %1x %1x (1:1)", zi, r , g , b , m); printf("\n[%d] %1x %1x %1x %1x (1:1)", zi, r , g , b , m);
} }
printf("\n------------------------------"); printf("\n------------------------------");
@ -3041,51 +3029,51 @@ WRITE8_MEMBER(rainbow_state::GDC_EXTRA_REGISTER_w)
break; break;
} }
if(m_GDC_INDIRECT_REGISTER & GDC_SELECT_SCROLL_MAP ) // 0x80 if (m_gdc_indirect_register & GDC_SELECT_SCROLL_MAP) // 0x80
{ {
if(!( m_GDC_MODE_REGISTER & GDC_MODE_READONLY_SCROLL_MAP)) // ? READONLY / WRITE logic correct...? if (!(m_gdc_mode_register & GDC_MODE_READONLY_SCROLL_MAP)) // ? READONLY / WRITE logic correct...?
{ {
m_GDC_SCROLL_BUFFER[m_GDC_scroll_index] = data; // // WRITE TO SCROLL_MAP ( 256 x 8 ) m_gdc_scroll_buffer[m_gdc_scroll_index] = data; // // WRITE TO SCROLL_MAP ( 256 x 8 )
if(m_GDC_scroll_index == 255) if (m_gdc_scroll_index == 255)
printf("\n ---- SCROLL MAP FULLY LOADED ---*"); printf("\n ---- SCROLL MAP FULLY LOADED ---*");
m_GDC_scroll_index++; m_gdc_scroll_index++;
m_GDC_scroll_index &= 0xFF; // 0...255 (CPU accesses 256 bytes) m_gdc_scroll_index &= 0xFF; // 0...255 (CPU accesses 256 bytes)
} }
break; break;
} }
// -----------------PATTERN + MULTIPLIER USED IN VECTOR MODE ONLY! // -----------------PATTERN + MULTIPLIER USED IN VECTOR MODE ONLY!
// SEE PAGE 37 OF AA-AE36A (PDF). // SEE PAGE 37 OF AA-AE36A (PDF).
if(m_GDC_INDIRECT_REGISTER & GDC_SELECT_PATTERN_MULTIPLIER) // 0x02 if (m_gdc_indirect_register & GDC_SELECT_PATTERN_MULTIPLIER) // 0x02
{ {
// On a Rainbow, 12 indicates a multiplier of 16-12 = 4 (example) // On a Rainbow, 12 indicates a multiplier of 16-12 = 4 (example)
m_patmult = 16 - (data & 15); // 4 bit register // VT240: "patmult_w" m_patmult = 16 - (data & 15); // 4 bit register // VT240: "patmult_w"
break; break;
} }
if(m_GDC_INDIRECT_REGISTER & GDC_SELECT_PATTERN) // 0x04 if (m_gdc_indirect_register & GDC_SELECT_PATTERN) // 0x04
{ {
// NOTE : Pattern Multiplier MUST BE LOADED before (!) // NOTE : Pattern Multiplier MUST BE LOADED before (!)
m_vpat = data; m_vpat = data;
break; break;
} }
if(m_GDC_INDIRECT_REGISTER & GDC_SELECT_FG_BG) // 0x08 if (m_gdc_indirect_register & GDC_SELECT_FG_BG) // 0x08
{ {
m_GDC_FG_BG = data; // Neither bitswap nor negated (and also not both)... m_gdc_fg_bg = data; // Neither bitswap nor negated (and also not both)...
break; // Next: prepare FG / BG (4 bits each) + plane in ALU - PLANE_SELECT register. break; // Next: prepare FG / BG (4 bits each) + plane in ALU - PLANE_SELECT register.
} }
if(m_GDC_INDIRECT_REGISTER & GDC_SELECT_ALU_PS) // 0x10 if (m_gdc_indirect_register & GDC_SELECT_ALU_PS) // 0x10
{ {
m_GDC_ALU_PS_REGISTER = ~data; // Negated... m_gdc_alu_ps_register = ~data; // Negated...
break; break;
} }
if(m_GDC_INDIRECT_REGISTER & GDC_SELECT_MODE_REGISTER) // 0x40 if (m_gdc_indirect_register & GDC_SELECT_MODE_REGISTER) // 0x40
{ {
m_GDC_MODE_REGISTER = data; // Neither bitswap nor negated (and also not both)... m_gdc_mode_register = data; // Neither bitswap nor negated (and also not both)...
if (data & GDC_MODE_HIGHRES) // 0x01 if (data & GDC_MODE_HIGHRES) // 0x01
{ {
@ -3119,16 +3107,16 @@ WRITE8_MEMBER(rainbow_state::GDC_EXTRA_REGISTER_w)
if (data & GDC_MODE_ENABLE_WRITES) // 0x10 if (data & GDC_MODE_ENABLE_WRITES) // 0x10
logerror(" READBACK: OFF - ENABLE_WRITES "); logerror(" READBACK: OFF - ENABLE_WRITES ");
else // READBACK PLANE 00..02 - mask in bits 2+3: else // READBACK PLANE 00..02 - mask in bits 2+3:
logerror(" READBACK MODE; plane = %02x ", m_GDC_MODE_REGISTER & GDC_MODE_READBACK_PLANE_MASK); // unsure if PLANE is set... already?! logerror(" READBACK MODE; plane = %02x ", m_gdc_mode_register & GDC_MODE_READBACK_PLANE_MASK); // unsure if PLANE is set... already?!
} }
if(last_scroll_index != m_GDC_scroll_index) if (last_scroll_index != m_gdc_scroll_index)
{ {
last_scroll_index = m_GDC_scroll_index; last_scroll_index = m_gdc_scroll_index;
if (data & GDC_MODE_READONLY_SCROLL_MAP) // 0x20 if (data & GDC_MODE_READONLY_SCROLL_MAP) // 0x20
logerror(" SCROLL MAP READ_ONLY. Index : %02x ", m_GDC_scroll_index); logerror(" SCROLL MAP READ_ONLY. Index : %02x ", m_gdc_scroll_index);
else else
logerror(" SCROLL MAP IS WRITABLE. Index : %02x ", m_GDC_scroll_index); logerror(" SCROLL MAP IS WRITABLE. Index : %02x ", m_gdc_scroll_index);
} }
if (!(data & GDC_MODE_ENABLE_VSYNC_IRQ)) // 0x40 if (!(data & GDC_MODE_ENABLE_VSYNC_IRQ)) // 0x40
@ -3138,7 +3126,7 @@ WRITE8_MEMBER(rainbow_state::GDC_EXTRA_REGISTER_w)
break; break;
} // GDC_SELECT_MODE_REGISTER } // GDC_SELECT_MODE_REGISTER
logerror("\n* UNIMPLEMENTED CASE. MODE = %02x / m_GDC_INDIRECT_REGISTER = %02x\n",m_GDC_MODE_REGISTER, m_GDC_INDIRECT_REGISTER); logerror("\n* UNIMPLEMENTED CASE. MODE = %02x / m_gdc_indirect_register = %02x\n",m_gdc_mode_register, m_gdc_indirect_register);
break; break;
case 2: case 2:
@ -3149,30 +3137,30 @@ WRITE8_MEMBER(rainbow_state::GDC_EXTRA_REGISTER_w)
// -------------------- WRITE BUFFER USED IN WORD MODE ONLY ! // -------------------- WRITE BUFFER USED IN WORD MODE ONLY !
// "OUTPUT WRITE BUFFER IS THE INVERSE OF THE INPUT" (quote from 4-3 of the PDF) // "OUTPUT WRITE BUFFER IS THE INVERSE OF THE INPUT" (quote from 4-3 of the PDF)
// BITSWAP SEEMS NECESSARY (see digits in DOODLE)... ! // BITSWAP SEEMS NECESSARY (see digits in DOODLE)... !
m_GDC_WRITE_BUFFER[m_GDC_write_buffer_index++] = ~bitswap<8>(data, 0, 1, 2, 3, 4, 5, 6, 7); m_gdc_write_buffer[m_gdc_write_buffer_index++] = ~bitswap<8>(data, 0, 1, 2, 3, 4, 5, 6, 7);
m_GDC_write_buffer_index &= 0xf; // write up to 16 bytes to port 52h. m_gdc_write_buffer_index &= 0xf; // write up to 16 bytes to port 52h.
break; break;
case 3: // 53h Indirect Register; address selection for indirect addressing. See 51h. case 3: // 53h Indirect Register; address selection for indirect addressing. See 51h.
m_GDC_INDIRECT_REGISTER = data ^ 0xff; m_gdc_indirect_register = data ^ 0xff;
// Index to WRITE_BUFFER is reset via dummy write to port 51h (not here!). // Index to WRITE_BUFFER is reset via dummy write to port 51h (not here!).
if(m_GDC_INDIRECT_REGISTER & GDC_SELECT_COLOR_MAP ) // 0x20 if (m_gdc_indirect_register & GDC_SELECT_COLOR_MAP) // 0x20
m_GDC_color_map_index = 0; // (also clears the index counter) m_gdc_color_map_index = 0; // (also clears the index counter)
// NEXT: 32 BYTE COLOR MAP, LOADED TO $51 // NEXT: 32 BYTE COLOR MAP, LOADED TO $51
//if(m_GDC_INDIRECT_REGISTER & GDC_SELECT_MODE_REGISTER) // 0x40 //if (m_gdc_indirect_register & GDC_SELECT_MODE_REGISTER) // 0x40
// logerror(" *** SELECT MODE REGISTER"); // logerror(" *** SELECT MODE REGISTER");
if(m_GDC_INDIRECT_REGISTER & GDC_SELECT_SCROLL_MAP ) // 0x80 if (m_gdc_indirect_register & GDC_SELECT_SCROLL_MAP) // 0x80
{ {
if(last_scroll_index != m_GDC_scroll_index) if (last_scroll_index != m_gdc_scroll_index)
{ {
last_scroll_index = m_GDC_scroll_index; last_scroll_index = m_gdc_scroll_index;
logerror(" *** SCROLL INDEX COUNTER RESET, old value = %d", m_GDC_scroll_index); logerror(" *** SCROLL INDEX COUNTER RESET, old value = %d", m_gdc_scroll_index);
} }
m_GDC_scroll_index = 0; // (also clears the index counter) m_gdc_scroll_index = 0; // (also clears the index counter)
} // NEXT: LOAD 256 BYTE SCROLL MAP INTO $51 } // NEXT: LOAD 256 BYTE SCROLL MAP INTO $51
break; break;
@ -3180,10 +3168,10 @@ WRITE8_MEMBER(rainbow_state::GDC_EXTRA_REGISTER_w)
// There is no specific order for the WRITE_MASK (according to txt/code samples in DEC's PDF). // There is no specific order for the WRITE_MASK (according to txt/code samples in DEC's PDF).
// NOTE: LOW <-> HI JUXTAPOSITION! // NOTE: LOW <-> HI JUXTAPOSITION!
case 4: // 54h Write Mask LOW case 4: // 54h Write Mask LOW
m_GDC_WRITE_MASK = ( bitswap<8>(data, 0, 1, 2, 3, 4, 5, 6, 7) << 8 ) | ( m_GDC_WRITE_MASK & 0x00FF ); m_gdc_write_mask = ( bitswap<8>(data, 0, 1, 2, 3, 4, 5, 6, 7) << 8 ) | ( m_gdc_write_mask & 0x00FF );
break; break;
case 5: // 55h Write Mask HIGH case 5: // 55h Write Mask HIGH
m_GDC_WRITE_MASK = ( m_GDC_WRITE_MASK & 0xFF00 ) | bitswap<8>(data, 0, 1, 2, 3, 4, 5, 6, 7); m_gdc_write_mask = ( m_gdc_write_mask & 0xFF00 ) | bitswap<8>(data, 0, 1, 2, 3, 4, 5, 6, 7);
break; break;
case 6: case 6: