mirror of
https://github.com/holub/mame
synced 2025-04-22 16:31:49 +03:00
added tmc0270_cpu_device, preliminary
This commit is contained in:
hap
parent
d3daab0a21
commit
cd02eac42e
@ -91,6 +91,8 @@ unknown cycle: CME, SSE, SSS
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#define M_STSL 0x00080000 /* STATUS to Status Latch */
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#define M_YTP 0x00100000 /* Y to +ALU */
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#define M_RSTR 0x00200000 /* -> F_RSTR */
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/* Standard/fixed instructions - these are documented more in their specific handlers below */
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#define F_BR 0x00000001
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#define F_CALL 0x00000002
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@ -115,7 +117,7 @@ unknown cycle: CME, SSE, SSS
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// supported types:
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// note: dice information assumes the orientation is pictured with RAM at the bottom-left
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// note: dice information assumes the orientation is pictured with RAM at the bottom-left, except where noted
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// TMS1000
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// - 64x4bit RAM array at the bottom-left
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@ -127,8 +129,8 @@ unknown cycle: CME, SSE, SSS
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// - 20-term output PLA(opla) at the top-left
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// - the ALU is between the opla and mpla
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const device_type TMS1000 = &device_creator<tms1000_cpu_device>; // 28-pin DIP, 11 R pins
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const device_type TMS1200 = &device_creator<tms1200_cpu_device>; // 40-pin DIP, 13 R pins
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const device_type TMS1070 = &device_creator<tms1070_cpu_device>; // same as tms1000, just supports higher voltage
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const device_type TMS1200 = &device_creator<tms1200_cpu_device>; // 40-pin DIP, 13 R pins
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// TMS1270 has 10 O pins, how does that work?
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// TMS1100 is nearly the same as TMS1000, some different opcodes, and with double the RAM and ROM
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@ -140,17 +142,23 @@ const device_type TMS1300 = &device_creator<tms1300_cpu_device>; // 40-pin DIP,
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// - 2048x9bit ROM array at the bottom-left
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// - main instructions PLA at the top half, to the right of the midline
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// - 64-term microinstructions PLA between the RAM and ROM, supporting 20 microinstructions
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// - 16-term output PLA and segment PLA above the RAM
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const device_type TMS0980 = &device_creator<tms0980_cpu_device>; // 28-pin DIP, 9 R pins
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// - 16-term output PLA and segment PLA above the RAM (rotate opla 90 degrees)
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const device_type TMS0980 = &device_creator<tms0980_cpu_device>; // 28-pin DIP, 9 R pins, 5 K pins
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// TMS0970 is a stripped-down version of the TMS0980, itself acting more like a TMS1000
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// - 64x4bit RAM array at the bottom-left
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// - 1024x8bit ROM array at the bottom-right
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// - RAM and ROM is exactly the same as TMS1000
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// - main instructions PLA at the top half, to the right of the midline
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// - 32-term microinstructions PLA between the RAM and ROM, supporting 15 microinstructions
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// - 16-term output PLA and segment PLA above the RAM
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// - 16-term output PLA and segment PLA above the RAM (rotate opla 90 degrees)
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const device_type TMS0970 = &device_creator<tms0970_cpu_device>; // 28-pin DIP, 11 R pins
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// TMC0270 on the other hand, is a TMS0980 with earrings and a new hat. The new changes look like a quick afterthought, almost hacky
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// - RAM, ROM, and main instructions PLA is exactly the same as TMS0980
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// - 64-term microinstructions PLA between the RAM and ROM, supporting 20 microinstructions plus optional separate lines for custom opcode handling
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// - 48-term output PLA above the RAM (rotate opla 90 degrees)
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const device_type TMC0270 = &device_creator<tmc0270_cpu_device>; // 40-pin DIP, 16 O pins, 8 R pins (the other R pins are internally hooked up to support more I/O)
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// TMC0260 is same? except opla is 32 instead of 48 terms
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static ADDRESS_MAP_START(program_11bit_9, AS_PROGRAM, 16, tms1xxx_cpu_device)
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AM_RANGE(0x000, 0xfff) AM_ROM
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@ -232,6 +240,17 @@ tms0980_cpu_device::tms0980_cpu_device(const machine_config &mconfig, const char
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{
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}
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tms0980_cpu_device::tms0980_cpu_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, UINT8 o_pins, UINT8 r_pins, UINT8 k_pins, UINT8 pc_bits, UINT8 byte_bits, UINT8 x_bits, int prgwidth, address_map_constructor program, int datawidth, address_map_constructor data, const char *shortname, const char *source)
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: tms0970_cpu_device(mconfig, type, name, tag, owner, clock, o_pins, r_pins, k_pins, pc_bits, byte_bits, x_bits, prgwidth, program, datawidth, data, shortname, source)
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{
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}
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tmc0270_cpu_device::tmc0270_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
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: tms0980_cpu_device(mconfig, TMC0270, "TMC0270", tag, owner, clock, 16, 8, 4, 7, 9, 4, 12, ADDRESS_MAP_NAME(program_11bit_9), 8, ADDRESS_MAP_NAME(data_64x9_as4), "tmc0270", __FILE__)
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{
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}
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static MACHINE_CONFIG_FRAGMENT(tms1000)
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@ -287,6 +306,23 @@ machine_config_constructor tms0980_cpu_device::device_mconfig_additions() const
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}
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static MACHINE_CONFIG_FRAGMENT(tmc0270)
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// main opcodes PLA, microinstructions PLA, output PLA
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MCFG_PLA_ADD("ipla", 9, 22, 24)
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MCFG_PLA_FILEFORMAT(PLA_FMT_BERKELEY)
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MCFG_PLA_ADD("mpla", 6, 21, 64)
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MCFG_PLA_FILEFORMAT(PLA_FMT_BERKELEY)
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MCFG_PLA_ADD("opla", 6, 16, 48)
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MCFG_PLA_FILEFORMAT(PLA_FMT_BERKELEY)
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MACHINE_CONFIG_END
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machine_config_constructor tmc0270_cpu_device::device_mconfig_additions() const
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{
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return MACHINE_CONFIG_NAME(tmc0270);
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}
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offs_t tms1000_cpu_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options)
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{
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@ -357,6 +393,7 @@ void tms1xxx_cpu_device::device_start()
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m_cs = 0;
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m_r = 0;
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m_o = 0;
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m_o_latch = 0;
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m_cki_bus = 0;
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m_c4 = 0;
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m_p = 0;
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@ -370,7 +407,7 @@ void tms1xxx_cpu_device::device_start()
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m_clatch = 0;
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m_add = 0;
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m_bl = 0;
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m_ram_in = 0;
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m_dam_in = 0;
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m_ram_out = 0;
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@ -381,6 +418,10 @@ void tms1xxx_cpu_device::device_start()
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m_micro = 0;
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m_subcycle = 0;
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m_a_prev = m_a;
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m_r_prev = m_r;
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m_o_prev = m_o;
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// register for savestates
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save_item(NAME(m_pc));
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save_item(NAME(m_sr));
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@ -394,6 +435,7 @@ void tms1xxx_cpu_device::device_start()
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save_item(NAME(m_cs));
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save_item(NAME(m_r));
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save_item(NAME(m_o));
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save_item(NAME(m_o_latch));
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save_item(NAME(m_cki_bus));
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save_item(NAME(m_c4));
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save_item(NAME(m_p));
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@ -418,6 +460,10 @@ void tms1xxx_cpu_device::device_start()
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save_item(NAME(m_micro));
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save_item(NAME(m_subcycle));
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save_item(NAME(m_a_prev));
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save_item(NAME(m_r_prev));
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save_item(NAME(m_o_prev));
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// register state for debugger
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state_add(TMS0980_PC, "PC", m_pc ).formatstr("%02X");
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state_add(TMS0980_SR, "SR", m_sr ).formatstr("%01X");
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@ -570,11 +616,12 @@ UINT32 tms0980_cpu_device::decode_micro(UINT8 sel)
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sel = BITSWAP8(sel,7,6,0,1,2,3,4,5); // lines are reversed
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UINT32 mask = m_mpla->read(sel);
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mask ^= 0x43fc3; // invert active-negative
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// _______ ______ _____ _____ _____ _____ ______ _____ ______ _____ _____
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const UINT32 md[20] = { M_NDMTP, M_DMTP, M_AUTY, M_AUTA, M_CKM, M_SSE, M_CKP, M_YTP, M_MTP, M_ATN, M_NATN, M_MTN, M_15TN, M_CKN, M_NE, M_C8, M_SSS, M_CME, M_CIN, M_STO };
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for (int bit = 0; bit < 20; bit++)
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// note: M_RSTR is specific to TMC02x0, it redirects to F_RSTR
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// _______ ______ _____ _____ _____ _____ ______ _____ ______ _____ _____
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const UINT32 md[21] = { M_NDMTP, M_DMTP, M_AUTY, M_AUTA, M_CKM, M_SSE, M_CKP, M_YTP, M_MTP, M_ATN, M_NATN, M_MTN, M_15TN, M_CKN, M_NE, M_C8, M_SSS, M_CME, M_CIN, M_STO, M_RSTR };
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for (int bit = 0; bit < 21 && bit < m_mpla->outputs(); bit++)
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if (mask & (1 << bit))
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decode |= md[bit];
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@ -619,7 +666,9 @@ void tms0980_cpu_device::device_reset()
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//-------------------------------------------------
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// program counter/opcode decode
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//-------------------------------------------------
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void tms1xxx_cpu_device::next_pc()
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{
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@ -666,6 +715,20 @@ void tms0980_cpu_device::read_opcode()
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next_pc();
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}
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void tmc0270_cpu_device::read_opcode()
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{
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tms0980_cpu_device::read_opcode();
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// RSTR is on the mpla
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if (m_micro & M_RSTR)
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m_fixed |= F_RSTR;
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}
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//-------------------------------------------------
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// i/o handling
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//-------------------------------------------------
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void tms1xxx_cpu_device::write_o_output(UINT8 data)
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{
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@ -684,6 +747,17 @@ void tms0970_cpu_device::write_o_output(UINT8 data)
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m_write_o(0, m_o & m_o_mask, 0xffff);
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}
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void tmc0270_cpu_device::dynamic_output()
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{
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// TODO..
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m_a_prev = m_a;
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m_r_prev = m_r;
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m_o_prev = m_o;
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}
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UINT8 tms1xxx_cpu_device::read_k_input()
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{
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// K1,2,4,8,3 (KC test pin is not emulated)
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@ -692,6 +766,13 @@ UINT8 tms1xxx_cpu_device::read_k_input()
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return (k & 0xf) | k3;
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}
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UINT8 tmc0270_cpu_device::read_k_input()
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{
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// TODO..
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return tms1xxx_cpu_device::read_k_input();
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}
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void tms1xxx_cpu_device::set_cki_bus()
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{
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@ -746,7 +827,10 @@ void tms0980_cpu_device::set_cki_bus()
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}
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// fixed opcode set
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//-------------------------------------------------
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// fixed opcode set
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//-------------------------------------------------
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// TMS1000/common:
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@ -841,7 +925,7 @@ void tms1xxx_cpu_device::op_comc()
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}
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// TMS09x0-specific
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// TMS0970-specific (and possibly child classes)
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void tms0970_cpu_device::op_setr()
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{
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// SETR: set output register
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@ -858,7 +942,7 @@ void tms0970_cpu_device::op_tdo()
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}
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// TMS0980-specific
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// TMS0980-specific (and possibly child classes)
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void tms0980_cpu_device::op_comx()
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{
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// COMX: complement X register, but not the MSB
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@ -904,38 +988,24 @@ void tms1xxx_cpu_device::op_sbl()
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}
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void tms1xxx_cpu_device::execute_fixed_opcode()
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// TMC0270-specific
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void tmc0270_cpu_device::op_tdo()
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{
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switch (m_fixed)
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{
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case F_SBIT: op_sbit(); break;
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case F_RBIT: op_rbit(); break;
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case F_SETR: op_setr(); break;
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case F_RSTR: op_rstr(); break;
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case F_TDO: op_tdo(); break;
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case F_CLO: op_clo(); break;
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case F_LDX: op_ldx(); break;
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case F_COMX: op_comx(); break;
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case F_COMX8:op_comx8();break;
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case F_LDP: op_ldp(); break;
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case F_COMC: op_comc(); break;
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case F_OFF: op_off(); break;
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case F_SEAC: op_seac(); break;
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case F_REAC: op_reac(); break;
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case F_SAL: op_sal(); break;
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case F_SBL: op_sbl(); break;
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case F_XDA: op_xda(); break;
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default:
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// BR, CALL, RETN are handled in execute_run
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if (m_fixed & ~(F_BR | F_CALL | F_RETN))
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fatalerror("%s unsupported fixed opcode %03X %04X!\n", tag(), m_opcode, m_fixed);
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break;
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}
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// TDO: transfer data out
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if (m_status)
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m_o_latch = m_a;
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else
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m_o = m_o_latch | (m_a << 4 & 0x30);
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// handled further in dynamic_output
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}
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//-------------------------------------------------
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// execute_run
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//-------------------------------------------------
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void tms1xxx_cpu_device::execute_run()
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{
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do
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@ -995,6 +1065,7 @@ void tms1xxx_cpu_device::execute_run()
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// execute: k input valid, read ram, clear alu inputs
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set_cki_bus();
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dynamic_output();
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m_ram_in = m_data->read_byte(m_ram_address) & 0xf;
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m_dam_in = m_data->read_byte(m_ram_address | (0x10 << (m_x_bits-1))) & 0xf;
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m_ram_out = -1;
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@ -1056,8 +1127,24 @@ void tms1xxx_cpu_device::execute_run()
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if (m_micro & M_STO || (m_micro & M_CME && m_eac == m_add))
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m_ram_out = m_a;
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// handle the fixed opcodes here
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execute_fixed_opcode();
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// handle the other fixed opcodes here
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if (m_fixed & F_SBIT) op_sbit();
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if (m_fixed & F_RBIT) op_rbit();
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if (m_fixed & F_SETR) op_setr();
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if (m_fixed & F_RSTR) op_rstr();
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if (m_fixed & F_TDO) op_tdo();
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if (m_fixed & F_CLO) op_clo();
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if (m_fixed & F_LDX) op_ldx();
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if (m_fixed & F_COMX) op_comx();
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if (m_fixed & F_COMX8) op_comx8();
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if (m_fixed & F_LDP) op_ldp();
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if (m_fixed & F_COMC) op_comc();
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if (m_fixed & F_OFF) op_off();
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if (m_fixed & F_SEAC) op_seac();
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if (m_fixed & F_REAC) op_reac();
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if (m_fixed & F_SAL) op_sal();
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if (m_fixed & F_SBL) op_sbl();
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if (m_fixed & F_XDA) op_xda();
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// execute: write ram
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if (m_ram_out != -1)
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@ -83,11 +83,11 @@ protected:
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void state_string_export(const device_state_entry &entry, astring &string);
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void next_pc();
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void execute_fixed_opcode();
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virtual void write_o_output(UINT8 data);
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virtual UINT8 read_k_input();
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virtual void set_cki_bus();
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virtual void dynamic_output() { ; } // not used by default
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virtual void read_opcode();
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virtual void op_sbit();
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@ -122,13 +122,17 @@ protected:
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UINT8 m_pa; // 4-bit page address register
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UINT8 m_pb; // 4-bit page buffer register
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UINT8 m_a; // 4-bit accumulator
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UINT8 m_a_prev;
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UINT8 m_x; // 2,3,or 4-bit RAM X register
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UINT8 m_y; // 4-bit RAM Y register
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UINT8 m_ca; // chapter address bit
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UINT8 m_cb; // chapter buffer bit
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UINT8 m_cs; // chapter subroutine bit
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UINT16 m_r;
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UINT16 m_r_prev;
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UINT16 m_o;
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UINT16 m_o_prev;
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UINT16 m_o_latch; // TMC0270 hold latch
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UINT8 m_cki_bus;
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UINT8 m_c4;
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UINT8 m_p; // 4-bit adder p(lus)-input
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@ -258,6 +262,7 @@ class tms0980_cpu_device : public tms0970_cpu_device
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{
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public:
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tms0980_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
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tms0980_cpu_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, UINT8 o_pins, UINT8 r_pins, UINT8 k_pins, UINT8 pc_bits, UINT8 byte_bits, UINT8 x_bits, int prgwidth, address_map_constructor program, int datawidth, address_map_constructor data, const char *shortname, const char *source);
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protected:
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// overrides
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@ -273,11 +278,31 @@ protected:
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virtual void read_opcode();
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virtual void op_comx();
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private:
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UINT32 decode_micro(UINT8 sel);
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};
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class tmc0270_cpu_device : public tms0980_cpu_device
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{
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public:
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tmc0270_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
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protected:
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// overrides
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virtual machine_config_constructor device_mconfig_additions() const;
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virtual void write_o_output(UINT8 data) { tms1xxx_cpu_device::write_o_output(data); }
|
||||
virtual UINT8 read_k_input();
|
||||
virtual void dynamic_output();
|
||||
virtual void read_opcode();
|
||||
|
||||
virtual void op_setr() { tms1xxx_cpu_device::op_setr(); }
|
||||
virtual void op_rstr() { tms1xxx_cpu_device::op_rstr(); }
|
||||
virtual void op_tdo();
|
||||
};
|
||||
|
||||
|
||||
|
||||
extern const device_type TMS1000;
|
||||
extern const device_type TMS1070;
|
||||
@ -286,6 +311,7 @@ extern const device_type TMS1100;
|
||||
extern const device_type TMS1300;
|
||||
extern const device_type TMS0970;
|
||||
extern const device_type TMS0980;
|
||||
extern const device_type TMC0270;
|
||||
|
||||
|
||||
#endif /* _TMS0980_H_ */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user