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Merge pull request #2827 from JoakimLarsson/z80scc_cleanup
z80scc: general cleanup part III
This commit is contained in:
Joakim Larsson Edström
GitHub
commit
cd2ffe6b09
@ -128,7 +128,7 @@ DONE (x) (p=partly) NMOS CMOS ESCC EMSCC
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#define CHANA_TAG "cha"
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#define CHANB_TAG "chb"
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enum
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enum : uint8_t
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{
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RR0_RX_CHAR_AVAILABLE = 0x01,
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RR0_ZC = 0x02,
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@ -140,7 +140,7 @@ enum
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RR0_BREAK_ABORT = 0x80
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};
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enum
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enum : uint8_t
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{
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RR1_ALL_SENT = 0x01,
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RR1_RESIDUE_CODE_MASK = 0x0e,
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@ -150,15 +150,7 @@ enum
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RR1_END_OF_FRAME = 0x80
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};
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enum
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{
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RR2_INT_VECTOR_MASK = 0xff, // SCC channel A, SIO channel B (special case)
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RR2_INT_VECTOR_V1 = 0x02, // SIO (special case) /SCC Channel B
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RR2_INT_VECTOR_V2 = 0x04, // SIO (special case) /SCC Channel B
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RR2_INT_VECTOR_V3 = 0x08 // SIO (special case) /SCC Channel B
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};
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enum
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enum : uint8_t
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{
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RR3_CHANB_EXT_IP = 0x01, // SCC IP pending registers
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RR3_CHANB_TX_IP = 0x02, // only read in Channel A (for both channels)
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@ -169,7 +161,7 @@ enum
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};
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// Universal Bus WR0 commands for 85X30
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enum
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enum : uint8_t
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{
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WR0_REGISTER_MASK = 0x07,
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WR0_COMMAND_MASK = 0x38, // COMMANDS
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@ -188,7 +180,7 @@ enum
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WR0_CRC_RESET_TX_UNDERRUN = 0xc0 // 1 1
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};
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enum // ZBUS WR0 commands or 80X30
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enum : uint8_t // ZBUS WR0 commands or 80X30
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{
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WR0_Z_COMMAND_MASK = 0x38, // COMMANDS
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WR0_Z_NULL_1 = 0x00, // 0 0 0
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@ -204,7 +196,7 @@ enum // ZBUS WR0 commands or 80X30
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WR0_Z_SEL_SHFT_RIGHT = 0x03 // 1 1
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};
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enum
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enum : uint8_t
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{
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WR1_EXT_INT_ENABLE = 0x01,
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WR1_TX_INT_ENABLE = 0x02,
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@ -219,7 +211,7 @@ enum
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WR1_WREQ_ENABLE = 0x80
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};
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enum
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enum : uint8_t
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{
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WR3_RX_ENABLE = 0x01,
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WR3_SYNC_CHAR_LOAD_INHIBIT = 0x02,
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@ -234,7 +226,7 @@ enum
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WR3_RX_WORD_LENGTH_8 = 0xc0
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};
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enum
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enum : uint8_t
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{
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WR4_PARITY_ENABLE = 0x01,
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WR4_PARITY_EVEN = 0x02,
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@ -256,7 +248,7 @@ enum
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WR4_CLOCK_RATE_X64 = 0xc0
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};
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enum
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enum : uint8_t
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{
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WR5_TX_CRC_ENABLE = 0x01,
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WR5_RTS = 0x02,
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@ -271,12 +263,12 @@ enum
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WR5_DTR = 0x80
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};
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enum
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enum : uint8_t
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{
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WR7P_TX_FIFO_EMPTY = 0x04
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};
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enum
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enum : uint8_t
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{
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WR9_CMD_MASK = 0xC0,
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WR9_CMD_NORESET = 0x00,
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@ -291,7 +283,7 @@ enum
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WR9_BIT_IACK = 0x20
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};
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enum
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enum : uint8_t
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{
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WR10_8_6_BIT_SYNC = 0x01,
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WR10_LOOP_MODE = 0x02,
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@ -308,7 +300,7 @@ enum
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WR10_CRC_PRESET = 0x80
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};
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enum
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enum : uint8_t
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{
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WR11_RCVCLK_TYPE = 0x80,
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WR11_RCVCLK_SRC_MASK = 0x60, // RCV CLOCK
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@ -329,7 +321,7 @@ enum
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WR11_TRXSRC_SRC_DPLL = 0x03 // 1 1
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};
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enum
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enum : uint8_t
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{
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WR14_DPLL_CMD_MASK = 0xe0, // Command
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WR14_CMD_NULL = 0x00, // 0 0 0
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@ -347,7 +339,7 @@ enum
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WR14_LOCAL_LOOPBACK = 0x10
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};
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enum
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enum : uint8_t
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{
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WR15_WR7PRIME = 0x01,
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WR15_ZEROCOUNT = 0x02,
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@ -1814,7 +1806,7 @@ uint8_t z80scc_channel::scc_register_read( uint8_t reg)
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{
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case REG_RR0_STATUS: data = do_sccreg_rr0(); break; // TODO: verify handling of SCC specific bits: D6 and D1
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case REG_RR1_SPEC_RCV_COND: data = do_sccreg_rr1(); break;
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case REG_RR2_INTERRUPT_VECT: data = do_sccreg_rr2(); break; // Channel dependent and SCC specific handling compared to SIO
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case REG_RR2_INTERRUPT_VECT: data = do_sccreg_rr2(); break;
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/* registers 3-7 are specific to SCC. TODO: Check variant and log/stop misuse */
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case REG_RR3_INTERUPPT_PEND: data = wreg ? m_wr3 : do_sccreg_rr3(); break;
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case REG_RR4_WR4_OR_RR0: data = wreg ? m_wr4 : do_sccreg_rr4(); break;
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@ -1999,7 +1991,7 @@ void z80scc_channel::do_sccreg_wr0(uint8_t data)
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void z80scc_channel::do_sccreg_wr1(uint8_t data)
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{
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LOG("%s(%02x) \"%s\": %c : %s - %02x\n", FUNCNAME, data, owner()->tag(), 'A' + m_index, FUNCNAME, data);
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/* TODO: Sort out SCC specific behaviours from legacy SIO behaviours:
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/* TODO: Sort out SCC specific behaviours from legacy SIO behaviours inherited from z80dart.cpp:
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- Channel B only bits vs
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- Parity Is Special Condition, bit2 */
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m_wr1 = data;
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@ -2807,31 +2799,6 @@ WRITE_LINE_MEMBER( z80scc_channel::dcd_w )
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WRITE_LINE_MEMBER( z80scc_channel::ri_w )
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{
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LOGINT("\"%s\": %c : RI %u - not implemented\n", owner()->tag(), 'A' + m_index, state);
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#if 0 // TODO: This code is inherited from another device driver and not correct for SCC
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if (m_ri != state)
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{
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// set ring indicator state
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m_ri = state;
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if (!m_rx_rr0_latch)
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{
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if (m_ri)
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m_rr0 |= RR0_RI;
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else
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m_rr0 &= ~RR0_RI;
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if (m_wr1 & WR1_EXT_INT_ENABLE)
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{
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// trigger interrupt
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m_uart->trigger_interrupt(m_index, INT_EXTERNAL);
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// latch read register 0
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m_rx_rr0_latch = 1;
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}
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}
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}
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#endif
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}
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//-------------------------------------------------
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