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tms5220.cpp : Remove unnecessary arguments in handlers (#4692)
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@ -67,7 +67,7 @@ READ8Z_MEMBER( ti_speech_synthesizer_device::readz )
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// lines by setting the address bus to a different value, but the
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// Geneve may behave differently. This may not 100% reflect the real
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// situation, but it ensures a safe processing.
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m_vsp->combined_rsq_wsq_w(machine().dummy_space(), 0, ~0);
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m_vsp->combined_rsq_wsq_w(~0);
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}
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}
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@ -106,11 +106,11 @@ SETADDRESS_DBIN_MEMBER( ti_speech_synthesizer_device::setaddress_dbin )
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// both RS* and WS* are active, which is illegal.
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// Alternatively, we'll use the combined settings method
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m_vsp->combined_rsq_wsq_w(machine().dummy_space(), 0, m_reading ? ~tms5220_device::RS : ~tms5220_device::WS);
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m_vsp->combined_rsq_wsq_w(m_reading ? ~tms5220_device::RS : ~tms5220_device::WS);
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}
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else
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// If other address, turn off RS* and WS* (negative logic!)
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m_vsp->combined_rsq_wsq_w(machine().dummy_space(), 0, ~0);
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m_vsp->combined_rsq_wsq_w(~0);
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}
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/****************************************************************************/
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@ -125,7 +125,7 @@ WRITE_LINE_MEMBER( ti_speech_synthesizer_device::speech_ready )
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if ((state==0) && !m_reading)
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// Clear the lines only when we are done with writing.
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m_vsp->combined_rsq_wsq_w(machine().dummy_space(), 0, ~0);
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m_vsp->combined_rsq_wsq_w(~0);
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}
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void ti_speech_synthesizer_device::device_start()
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@ -1890,7 +1890,7 @@ WRITE_LINE_MEMBER( tms5220_device::wsq_w )
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* /RS is bit 1, /WS is bit 0
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* Note this is a hack and probably can be removed later, once the 'real' line handlers above defer by at least 4 clock cycles before taking effect
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*/
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WRITE8_MEMBER( tms5220_device::combined_rsq_wsq_w )
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void tms5220_device::combined_rsq_wsq_w(u8 data)
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{
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uint8_t falling_edges;
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m_true_timing = true;
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@ -48,7 +48,7 @@ public:
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WRITE_LINE_MEMBER( rsq_w );
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WRITE_LINE_MEMBER( wsq_w );
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DECLARE_WRITE8_MEMBER( combined_rsq_wsq_w );
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void combined_rsq_wsq_w(u8 data);
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/* this combined_rsq_wsq_w hack is necessary for specific systems such as
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the TI 99/8 since the 5220c and cd2501ecd do specific things if both lines
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go active or inactive at slightly different times by separate write_line
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@ -123,7 +123,7 @@ WRITE8_MEMBER( pes_state::rsq_wsq_w )
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logerror("port0 write: RSWS states updated: /RS: %d, /WS: %d\n", (data&0x2)>>1, data&0x1);
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#endif
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/* /RS is bit 1, /WS is bit 0 */
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m_speech->combined_rsq_wsq_w(space, 0, data&0x3);
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m_speech->combined_rsq_wsq_w(data&0x3);
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}
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WRITE8_MEMBER( pes_state::port1_w )
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