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ficpio2: add PCI bus and chipset. -bios 2 and 3 now boot. Other BIOSes require some cache funkiness.

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This commit is contained in:
mahlemiut 2015-09-24 14:15:28 +12:00
parent 7c3674f16b
commit cdb93cff68
10 changed files with 525 additions and 13 deletions
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2
scripts/src/bus.lua
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@ -1588,6 +1588,8 @@ if (BUSES["LPCI"]~=null) then
MAME_DIR .. "src/devices/bus/lpci/southbridge.h",
MAME_DIR .. "src/devices/bus/lpci/mpc105.c",
MAME_DIR .. "src/devices/bus/lpci/mpc105.h",
MAME_DIR .. "src/devices/bus/lpci/vt82c505.c",
MAME_DIR .. "src/devices/bus/lpci/vt82c505.h",
}
end

13
scripts/src/machine.lua
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@ -2688,3 +2688,16 @@ if (MACHINES["NSC810"]~=null) then
MAME_DIR .. "src/devices/machine/nsc810.h",
}
end
---------------------------------------------------
--
--@src/devices/machine/vt82c496.h,MACHINES["VT82C496"] = true
---------------------------------------------------
if (MACHINES["VT82C496"]~=null) then
files {
MAME_DIR .. "src/devices/machine/vt82c496.c",
MAME_DIR .. "src/devices/machine/vt82c496.h",
}
end

1
scripts/target/mame/mess.lua
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@ -564,6 +564,7 @@ MACHINES["WOZFDC"] = true
MACHINES["DIABLO_HD"] = true
MACHINES["TMS1024"] = true
MACHINES["NSC810"] = true
MACHINES["VT82C496"] = true
--------------------------------------------------
-- specify available bus cores

97
src/devices/bus/lpci/vt82c505.c Normal file
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@ -0,0 +1,97 @@
// license:BSD-3-Clause
// copyright-holders:Barry Rodewald
/*
VIA VT82C505 ISA/VL PCI bridge
*/
#include "emu.h"
#include "vt82c505.h"
/***************************************************************************
IMPLEMENTATION
***************************************************************************/
const device_type VT82C505 = &device_creator<vt82c505_device>;
vt82c505_device::vt82c505_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
: device_t(mconfig, VT82C505, "VIA VT82C505 PCI bridge", tag, owner, clock, "vt82c505", __FILE__),
pci_device_interface( mconfig, *this )
{
}
UINT32 vt82c505_device::pci_read(pci_bus_device *pcibus, int function, int offset, UINT32 mem_mask)
{
UINT32 result = 0;
if (function != 0)
return result;
switch (offset)
{
case 0x00: // vendor/device ID
result = 0x05051106;
break;
case 0x04: // command / status
result = 0x00000007;
break;
case 0x80: // DIP switch / revision, memory size, buffer control, VLB interface timing
result = 0x00000100;
break;
}
logerror("%s: PCI read func %i, offset %02x, result %08x\n",tag(),function,offset,result);
return result;
}
void vt82c505_device::pci_write(pci_bus_device *pcibus, int function, int offset, UINT32 data, UINT32 mem_mask)
{
if (function != 0)
return;
switch(offset)
{
case 0x84:
if(ACCESSING_BITS_0_7) // RX87: memory window 1 A31:24
{
m_window_addr[0] = (m_window_addr[0] & 0xff00) | (data & 0x000000ff);
logerror("%s: memory window #1 A31:24 set: %04x\n",tag(),m_window_addr[0]);
}
break;
case 0x88:
if(ACCESSING_BITS_24_31) // RX88: memory window 1 A23:16
{
m_window_addr[0] = (m_window_addr[0] & 0x00ff) | ((data & 0xff000000) >> 24);
logerror("%s: memory window #1 A23:16 set: %04x\n",tag(),m_window_addr[0]);
}
if(ACCESSING_BITS_16_23) // RX89: memory window 1 attributes
{
m_window_attr[0] = ((data & 0x00ff0000) >> 16);
logerror("%s: memory window #1 attributes set: %02x\n",tag(),m_window_attr[0]);
}
break;
}
logerror("%s: PCI write func %i, offset %02x, data %08x\n",tag(),function,offset,data);
}
//-------------------------------------------------
// device_start - device-specific startup
//-------------------------------------------------
void vt82c505_device::device_start()
{
/* setup save states */
}
//-------------------------------------------------
// device_reset - device-specific reset
//-------------------------------------------------
void vt82c505_device::device_reset()
{
}

38
src/devices/bus/lpci/vt82c505.h Normal file
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@ -0,0 +1,38 @@
// license:BSD-3-Clause
// copyright-holders:Barry Rodewald
/*
VIA VT82C505 PCI bridge
*/
#ifndef __VT82C505_H__
#define __VT82C505_H__
#include "pci.h"
class vt82c505_device : public device_t,
public pci_device_interface
{
public:
// construction/destruction
vt82c505_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
virtual UINT32 pci_read(pci_bus_device *pcibus, int function, int offset, UINT32 mem_mask);
virtual void pci_write(pci_bus_device *pcibus, int function, int offset, UINT32 data, UINT32 mem_mask);
protected:
// device-level overrides
virtual void device_start();
virtual void device_reset();
private:
UINT16 m_window_addr[3];
UINT8 m_window_attr[3];
};
// device type definition
extern const device_type VT82C505;
#endif /* __VT82C505_H__ */

226
src/devices/machine/vt82c496.c Normal file
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@ -0,0 +1,226 @@
// license:BSD-3-Clause
// copyright-holders:Barry Rodewald
/*
VIA VT82C496G "Green PC" system chipset
*/
#include "vt82c496.h"
/***************************************************************************
IMPLEMENTATION
***************************************************************************/
const device_type VT82C496 = &device_creator<vt82c496_device>;
vt82c496_device::vt82c496_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
: device_t(mconfig, VT82C496, "VIA VT82C496G system chipset", tag, owner, clock, "vt82c496", __FILE__)
{
}
void vt82c496_device::device_start()
{
/* get address space we are working on */
device_t *cpu = machine().device(m_cpu_tag);
assert(cpu != NULL);
m_space = &cpu->memory().space(AS_PROGRAM);
/* get rom region */
m_rom = machine().root_device().memregion(m_region_tag)->base();
save_pointer(m_reg,"Registers",0x100);
m_ram = machine().device<ram_device>(RAM_TAG);
}
void vt82c496_device::device_reset()
{
memset(m_reg,0,0x100);
// set up default ROM banking
m_space->install_read_bank(0xc0000,0xc3fff,0,0,"bios_c0_r");
m_space->install_read_bank(0xc4000,0xc7fff,0,0,"bios_c4_r");
m_space->install_read_bank(0xc8000,0xcbfff,0,0,"bios_c8_r");
m_space->install_read_bank(0xcc000,0xcffff,0,0,"bios_cc_r");
m_space->install_read_bank(0xd0000,0xd3fff,0,0,"bios_d0_r");
m_space->install_read_bank(0xd4000,0xd7fff,0,0,"bios_d4_r");
m_space->install_read_bank(0xd8000,0xdbfff,0,0,"bios_d8_r");
m_space->install_read_bank(0xdc000,0xdffff,0,0,"bios_dc_r");
m_space->install_read_bank(0xe0000,0xeffff,0,0,"bios_e0_r");
m_space->install_read_bank(0xf0000,0xfffff,0,0,"bios_f0_r");
m_space->nop_write(0xc0000,0xfffff,0,0);
machine().root_device().membank("bios_c0_r")->set_base(m_rom);
machine().root_device().membank("bios_c4_r")->set_base(m_rom+0x4000);
machine().root_device().membank("bios_c8_r")->set_base(m_rom+0x8000);
machine().root_device().membank("bios_cc_r")->set_base(m_rom+0xc000);
machine().root_device().membank("bios_d0_r")->set_base(m_rom+0x10000);
machine().root_device().membank("bios_d4_r")->set_base(m_rom+0x14000);
machine().root_device().membank("bios_d8_r")->set_base(m_rom+0x18000);
machine().root_device().membank("bios_dc_r")->set_base(m_rom+0x1c000);
machine().root_device().membank("bios_e0_r")->set_base(m_rom+0x20000);
machine().root_device().membank("bios_f0_r")->set_base(m_rom+0x30000);
}
READ8_MEMBER(vt82c496_device::read)
{
if(offset == 1)
return m_reg[m_reg_select];
return 0x00;
}
WRITE8_MEMBER(vt82c496_device::write)
{
if(offset == 0)
m_reg_select = data;
if(offset == 1)
{
m_reg[m_reg_select] = data;
switch(m_reg_select)
{
case 0x30:
update_mem_c0(data);
break;
case 0x31:
update_mem_d0(data);
break;
case 0x32:
update_mem_e0(data);
break;
}
}
}
void vt82c496_device::update_mem_c0(UINT8 data)
{
if(data & 0x80)
machine().root_device().membank("bios_cc_r")->set_base(m_ram->pointer()+0xcc000);
else
machine().root_device().membank("bios_cc_r")->set_base(m_rom+0xc000);
if(data & 0x40)
{
m_space->install_write_bank(0xcc000,0xcffff,0,0,"bios_cc_w");
machine().root_device().membank("bios_cc_w")->set_base(m_ram->pointer()+0xcc000);
}
else
m_space->nop_write(0xcc000,0xcffff,0,0);
if(data & 0x20)
machine().root_device().membank("bios_c8_r")->set_base(m_ram->pointer()+0xc8000);
else
machine().root_device().membank("bios_c8_r")->set_base(m_rom+0x8000);
if(data & 0x10)
{
m_space->install_write_bank(0xc8000,0xcbfff,0,0,"bios_c8_w");
machine().root_device().membank("bios_c8_w")->set_base(m_ram->pointer()+0xc8000);
}
else
m_space->nop_write(0xc8000,0xcbfff,0,0);
if(data & 0x08)
machine().root_device().membank("bios_c4_r")->set_base(m_ram->pointer()+0xc4000);
else
machine().root_device().membank("bios_c4_r")->set_base(m_rom+0x4000);
if(data & 0x04)
{
m_space->install_write_bank(0xc4000,0xc7fff,0,0,"bios_c4_w");
machine().root_device().membank("bios_c4_w")->set_base(m_ram->pointer()+0xc4000);
}
else
m_space->nop_write(0xc4000,0xc7fff,0,0);
if(data & 0x02)
machine().root_device().membank("bios_c0_r")->set_base(m_ram->pointer()+0xc0000);
else
machine().root_device().membank("bios_c0_r")->set_base(m_rom+0);
if(data & 0x01)
{
m_space->install_write_bank(0xc0000,0xc3fff,0,0,"bios_c0_w");
machine().root_device().membank("bios_c0_w")->set_base(m_ram->pointer()+0xc0000);
}
else
m_space->nop_write(0xc0000,0xc3fff,0,0);
}
void vt82c496_device::update_mem_d0(UINT8 data)
{
if(data & 0x80)
machine().root_device().membank("bios_dc_r")->set_base(m_ram->pointer()+0xdc000);
else
machine().root_device().membank("bios_dc_r")->set_base(m_rom+0x1c000);
if(data & 0x40)
{
m_space->install_write_bank(0xdc000,0xdffff,0,0,"bios_dc_w");
machine().root_device().membank("bios_dc_w")->set_base(m_ram->pointer()+0xdc000);
}
else
m_space->nop_write(0xdc000,0xdffff,0,0);
if(data & 0x20)
machine().root_device().membank("bios_d8_r")->set_base(m_ram->pointer()+0xd8000);
else
machine().root_device().membank("bios_d8_r")->set_base(m_rom+0x18000);
if(data & 0x10)
{
m_space->install_write_bank(0xd8000,0xdbfff,0,0,"bios_d8_w");
machine().root_device().membank("bios_d8_w")->set_base(m_ram->pointer()+0xd8000);
}
else
m_space->nop_write(0xd8000,0xdbfff,0,0);
if(data & 0x08)
machine().root_device().membank("bios_d4_r")->set_base(m_ram->pointer()+0xd4000);
else
machine().root_device().membank("bios_d4_r")->set_base(m_rom+0x14000);
if(data & 0x04)
{
m_space->install_write_bank(0xd4000,0xd7fff,0,0,"bios_d4_w");
machine().root_device().membank("bios_d4_w")->set_base(m_ram->pointer()+0xd4000);
}
else
m_space->nop_write(0xd4000,0xd7fff,0,0);
if(data & 0x02)
machine().root_device().membank("bios_d0_r")->set_base(m_ram->pointer()+0xd0000);
else
machine().root_device().membank("bios_d0_r")->set_base(m_rom+0x10000);
if(data & 0x01)
{
m_space->install_write_bank(0xd0000,0xd3fff,0,0,"bios_d0_w");
machine().root_device().membank("bios_d0_w")->set_base(m_ram->pointer()+0xd0000);
}
else
m_space->nop_write(0xd0000,0xd3fff,0,0);
}
void vt82c496_device::update_mem_e0(UINT8 data)
{
if(data & 0x80)
machine().root_device().membank("bios_e0_r")->set_base(m_ram->pointer()+0xe0000);
else
machine().root_device().membank("bios_e0_r")->set_base(m_rom+0x20000);
if(data & 0x40)
{
m_space->install_write_bank(0xe0000,0xeffff,0,0,"bios_e0_w");
machine().root_device().membank("bios_e0_w")->set_base(m_ram->pointer()+0xe0000);
}
else
m_space->nop_write(0xe0000,0xeffff,0,0);
if(data & 0x20)
machine().root_device().membank("bios_f0_r")->set_base(m_ram->pointer()+0xf0000);
else
machine().root_device().membank("bios_f0_r")->set_base(m_rom+0x30000);
if(data & 0x10)
{
m_space->install_write_bank(0xf0000,0xfffff,0,0,"bios_f0_w");
machine().root_device().membank("bios_f0_w")->set_base(m_ram->pointer()+0xf0000);
}
else
m_space->nop_write(0xf0000,0xfffff,0,0);
}

61
src/devices/machine/vt82c496.h Normal file
View File

@ -0,0 +1,61 @@
// license:BSD-3-Clause
// copyright-holders:Barry Rodewald
/*
VIA VT82C496G "Green PC" system chipset
*/
#ifndef __VT82C496_H__
#define __VT82C496_H__
#include "emu.h"
#include "ram.h"
#define MCFG_VT82C496_ADD(_tag) \
MCFG_DEVICE_ADD(_tag, VT82C496, 0)
#define MCFG_VT82C496_CPU( _tag ) \
vt82c496_device::static_set_cpu(*device, _tag);
#define MCFG_VT82C496_REGION( _tag ) \
vt82c496_device::static_set_region(*device, _tag);
class vt82c496_device : public device_t
{
public:
// construction/destruction
vt82c496_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
static void static_set_cpu(device_t &device, const char *tag) { dynamic_cast<vt82c496_device &>(device).m_cpu_tag = tag; }
static void static_set_region(device_t &device, const char *tag) { dynamic_cast<vt82c496_device &>(device).m_region_tag = tag; }
DECLARE_READ8_MEMBER(read);
DECLARE_WRITE8_MEMBER(write);
protected:
// device-level overrides
virtual void device_start();
virtual void device_reset();
private:
const char* m_cpu_tag;
const char* m_region_tag;
// cpu_device* m_maincpu;
address_space* m_space;
ram_device* m_ram;
UINT8* m_rom;
UINT8 m_reg[0x100];
UINT8 m_reg_select;
void update_mem_c0(UINT8 data);
void update_mem_d0(UINT8 data);
void update_mem_e0(UINT8 data);
};
// device type definition
extern const device_type VT82C496;
#endif /* __VT82C496_H__ */

93
src/mess/drivers/at.c
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@ -58,6 +58,16 @@ static ADDRESS_MAP_START( at586_map, AS_PROGRAM, 32, at586_state )
AM_RANGE(0xfffe0000, 0xffffffff) AM_ROM AM_REGION("isa", 0x20000)
ADDRESS_MAP_END
static ADDRESS_MAP_START( ficpio_map, AS_PROGRAM, 32, at_state )
AM_RANGE(0x00000000, 0x0009ffff) AM_RAMBANK("bank10")
AM_RANGE(0x000a0000, 0x000bffff) AM_NOP
AM_RANGE(0x000c0000, 0x000c7fff) AM_NOP
AM_RANGE(0x000c8000, 0x000cffff) AM_NOP
AM_RANGE(0x000d0000, 0x000effff) AM_RAM
AM_RANGE(0x000f0000, 0x000fffff) AM_RAM
AM_RANGE(0x00800000, 0x00800bff) AM_RAM AM_SHARE("nvram")
AM_RANGE(0xfffe0000, 0xffffffff) AM_ROM AM_REGION("isa", 0x20000)
ADDRESS_MAP_END
READ8_MEMBER( at_state::at_dma8237_2_r )
@ -196,6 +206,25 @@ static ADDRESS_MAP_START( at586_io, AS_IO, 32, at586_state )
AM_RANGE(0x0cf8, 0x0cff) AM_DEVREADWRITE("pcibus", pci_bus_device, read, write)
ADDRESS_MAP_END
static ADDRESS_MAP_START( ficpio_io, AS_IO, 32, at_state )
ADDRESS_MAP_UNMAP_HIGH
AM_RANGE(0x0000, 0x001f) AM_DEVREADWRITE8("dma8237_1", am9517a_device, read, write, 0xffffffff)
AM_RANGE(0x0020, 0x003f) AM_DEVREADWRITE8("pic8259_master", pic8259_device, read, write, 0xffffffff)
AM_RANGE(0x0040, 0x005f) AM_DEVREADWRITE8("pit8254", pit8254_device, read, write, 0xffffffff)
AM_RANGE(0x0060, 0x0063) AM_READWRITE8(at_keybc_r, at_keybc_w, 0xffff)
AM_RANGE(0x0064, 0x0067) AM_DEVREADWRITE8("keybc", at_keyboard_controller_device, status_r, command_w, 0xffff)
AM_RANGE(0x0070, 0x007f) AM_DEVREADWRITE8("rtc", mc146818_device, read, write , 0xffffffff)
AM_RANGE(0x0080, 0x009f) AM_READWRITE8(at_page8_r, at_page8_w, 0xffffffff)
AM_RANGE(0x00a0, 0x00a7) AM_DEVREADWRITE8("pic8259_slave", pic8259_device, read, write, 0xffffffff)
AM_RANGE(0x00a8, 0x00af) AM_DEVREADWRITE8("chipset", vt82c496_device, read, write, 0xffffffff)
AM_RANGE(0x00c0, 0x00df) AM_READWRITE8(at_dma8237_2_r, at_dma8237_2_w, 0xffffffff)
AM_RANGE(0x0170, 0x0177) AM_DEVREADWRITE("ide2", ide_controller_32_device, read_cs0, write_cs0)
AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE("ide", ide_controller_32_device, read_cs0, write_cs0)
AM_RANGE(0x0370, 0x0377) AM_DEVREADWRITE("ide2", ide_controller_32_device, read_cs1, write_cs1)
AM_RANGE(0x03f0, 0x03f7) AM_DEVREADWRITE("ide", ide_controller_32_device, read_cs1, write_cs1)
AM_RANGE(0x0cf8, 0x0cff) AM_DEVREADWRITE("pcibus", pci_bus_device, read, write)
ADDRESS_MAP_END
DRIVER_INIT_MEMBER(megapc_state, megapc)
{
UINT8* ROM = memregion("bios")->base();
@ -677,6 +706,7 @@ static SLOT_INTERFACE_START( pci_devices )
SLOT_INTERFACE_INTERNAL("i82439tx", I82439TX)
SLOT_INTERFACE_INTERNAL("i82371ab", I82371AB)
SLOT_INTERFACE_INTERNAL("i82371sb", I82371SB)
SLOT_INTERFACE_INTERNAL("vt82c505", VT82C505)
SLOT_INTERFACE_END
@ -863,6 +893,47 @@ static MACHINE_CONFIG_START( megapcpla, at_state )
MCFG_SOFTWARE_LIST_ADD("disk_list","megapc")
MACHINE_CONFIG_END
static MACHINE_CONFIG_START( ficpio2, at_state )
MCFG_CPU_ADD("maincpu", I486, 25000000)
MCFG_CPU_PROGRAM_MAP(ficpio_map)
MCFG_CPU_IO_MAP(ficpio_io)
MCFG_CPU_IRQ_ACKNOWLEDGE_DEVICE("pic8259_master", pic8259_device, inta_cb)
MCFG_FRAGMENT_ADD(at_motherboard)
MCFG_DEVICE_REMOVE("rtc")
MCFG_DS12885_ADD("rtc")
MCFG_MC146818_IRQ_HANDLER(WRITELINE(at_state, at_mc146818_irq))
MCFG_MC146818_CENTURY_INDEX(0x32)
MCFG_RAM_ADD(RAM_TAG)
MCFG_RAM_DEFAULT_SIZE("4M")
MCFG_RAM_EXTRA_OPTIONS("1M,2M,8M,16M,32M,64M,128M")
// on board devices
MCFG_ISA16_SLOT_ADD("isabus","board1", pc_isa16_cards, "fdcsmc", true)
MCFG_ISA16_SLOT_ADD("isabus","board2", pc_isa16_cards, "comat", true)
MCFG_ISA16_SLOT_ADD("isabus","board3", pc_isa16_cards, "lpt", true)
MCFG_IDE_CONTROLLER_32_ADD("ide", ata_devices, "hdd", NULL, true)
MCFG_ATA_INTERFACE_IRQ_HANDLER(DEVWRITELINE("pic8259_slave", pic8259_device, ir6_w))
MCFG_IDE_CONTROLLER_32_ADD("ide2", ata_devices, "cdrom", NULL, true)
MCFG_ATA_INTERFACE_IRQ_HANDLER(DEVWRITELINE("pic8259_slave", pic8259_device, ir7_w))
MCFG_PCI_BUS_ADD("pcibus", 0)
MCFG_PCI_BUS_DEVICE("pcibus:0", pci_devices, "vt82c505", true)
MCFG_ISA16_SLOT_ADD("isabus","isa1", pc_isa16_cards, "svga_et4k", false)
MCFG_ISA16_SLOT_ADD("isabus","isa2", pc_isa16_cards, NULL, false)
MCFG_ISA16_SLOT_ADD("isabus","isa3", pc_isa16_cards, NULL, false)
MCFG_ISA16_SLOT_ADD("isabus","isa4", pc_isa16_cards, NULL, false)
MCFG_PC_KBDC_SLOT_ADD("pc_kbdc", "kbd", pc_at_keyboards, STR_KBD_MICROSOFT_NATURAL)
MCFG_VT82C496_ADD("chipset")
MCFG_VT82C496_CPU("maincpu")
MCFG_VT82C496_REGION("isa")
MCFG_FRAGMENT_ADD( at_softlists )
MACHINE_CONFIG_END
#if 0
// ibm at
@ -1355,17 +1426,17 @@ ROM_END
// FIC 486-PIO-2 (4 ISA, 4 PCI)
// VIA VT82C505 + VT82C496G + VT82C406MV, NS311/312 or NS332 I/O
// VIA VT82C505 (ISA/VL to PCI bridge) + VT82C496G (system chipset) + VT82C406MV (keyboard controller, RTC, CMOS), NS311/312 or NS332 I/O
ROM_START( ficpio2 )
ROM_REGION(0x1000000, "maincpu", 0)
ROM_SYSTEM_BIOS(0, "ficpio2c7", "FIC 486-PIO-2 1.15C701") /* pnp, i/o core: NS 332 */
ROMX_LOAD("115c701.awd", 0x0e0000, 0x20000, CRC(b0dd7975) SHA1(bfde13b0fbd141bc945d37d92faca9f4f59b716d), ROM_BIOS(1))
ROM_SYSTEM_BIOS(1, "ficpio2b7", "FIC 486-PIO-2 1.15B701") /* pnp, i/o core: NS 311/312 */
ROMX_LOAD("115b701.awd", 0x0e0000, 0x20000, CRC(ac24abad) SHA1(01174d84ed32fb1d95cd632d09f773acb8666c83), ROM_BIOS(2))
ROM_SYSTEM_BIOS(2, "ficpio2c1", "FIC 486-PIO-2 1.15C101") /* non-pnp, i/o core: NS 332 */
ROMX_LOAD("115c101.awd", 0x0e0000, 0x20000, CRC(5fadde88) SHA1(eff79692c1ecf34b6ea3f02409d14ce1f5c51bf9), ROM_BIOS(3))
ROM_SYSTEM_BIOS(3, "ficpio2b1", "FIC 486-PIO-2 1.15B101") /* non-pnp, i/o core: NS 311/312 */
ROMX_LOAD("115b101.awd", 0x0e0000, 0x20000, CRC(ff69617d) SHA1(ecbfc7315dcf6bd3e5b59e3ae9258759f64fe7a0), ROM_BIOS(4))
ROM_REGION(0x40000, "isa", 0)
ROM_SYSTEM_BIOS(0, "ficpio2c7", "FIC 486-PIO-2 1.15C701") /* pnp, i/o core: NS 332, doesn't boot, requires cache emulation? */
ROMX_LOAD("115c701.awd", 0x020000, 0x20000, CRC(b0dd7975) SHA1(bfde13b0fbd141bc945d37d92faca9f4f59b716d), ROM_BIOS(1))
ROM_SYSTEM_BIOS(1, "ficpio2b7", "FIC 486-PIO-2 1.15B701") /* pnp, i/o core: NS 311/312, doesn't boot, requires cache emulation? */
ROMX_LOAD("115b701.awd", 0x020000, 0x20000, CRC(ac24abad) SHA1(01174d84ed32fb1d95cd632d09f773acb8666c83), ROM_BIOS(2))
ROM_SYSTEM_BIOS(2, "ficpio2c1", "FIC 486-PIO-2 1.15C101") /* non-pnp, i/o core: NS 332, working */
ROMX_LOAD("115c101.awd", 0x020000, 0x20000, CRC(5fadde88) SHA1(eff79692c1ecf34b6ea3f02409d14ce1f5c51bf9), ROM_BIOS(3))
ROM_SYSTEM_BIOS(3, "ficpio2b1", "FIC 486-PIO-2 1.15B101") /* non-pnp, i/o core: NS 311/312, working */
ROMX_LOAD("115b101.awd", 0x020000, 0x20000, CRC(ff69617d) SHA1(ecbfc7315dcf6bd3e5b59e3ae9258759f64fe7a0), ROM_BIOS(4))
ROM_END
@ -1631,7 +1702,7 @@ COMP ( 1993, apxena1, ibm5170, 0, at486, atvga, at_state, atvga,
COMP ( 1993, apxenp2, ibm5170, 0, at486, atvga, at_state, atvga, "Apricot", "Apricot XEN PC (P2 Motherboard)", MACHINE_NOT_WORKING )
COMP ( 1990, c386sx16, ibm5170, 0, at386sx, atvga, at_state, atvga, "Commodore Business Machines", "Commodore 386SX-16", MACHINE_NOT_WORKING )
COMP ( 1988, cmdpc30, ibm5170, 0, ibm5162, atcga, at_state, atcga, "Commodore Business Machines", "PC 30 III", MACHINE_NOT_WORKING )
COMP ( 1995, ficpio2, ibm5170, 0, at486, atvga, at_state, atvga, "FIC", "486-PIO-2", MACHINE_NOT_WORKING )
COMP ( 1995, ficpio2, ibm5170, 0, ficpio2, atvga, at_state, atvga, "FIC", "486-PIO-2", MACHINE_NOT_WORKING )
COMP ( 1997, ficvt503, ibm5170, 0, at586, atvga, driver_device, 0, "FIC", "VT-503", MACHINE_NOT_WORKING )
COMP ( 1985, k286i, ibm5170, 0, k286i, atcga, at_state, atcga, "Kaypro", "286i", MACHINE_NOT_WORKING )
COMP ( 1991, t2000sx, ibm5170, 0, at386sx, atvga, at_state, atvga, "Toshiba", "T2000SX", MACHINE_NOT_WORKING )

3
src/mess/includes/at.h
View File

@ -18,10 +18,13 @@
#include "machine/ins8250.h"
#include "machine/mc146818.h"
#include "machine/ds128x.h"
#include "machine/pic8259.h"
#include "bus/lpci/i82371ab.h"
#include "bus/lpci/i82371sb.h"
#include "bus/lpci/i82439tx.h"
#include "bus/lpci/vt82c505.h"
#include "machine/vt82c496.h"
#include "machine/cs8221.h"
#include "machine/pit8253.h"
#include "machine/wd7600.h"

4
src/mess/machine/at.c
View File

@ -274,10 +274,10 @@ void at_state::init_at_common()
if (m_ram->size() > 0x0a0000)
{
offs_t ram_limit = 0x100000 + m_ram->size() - 0x0a0000;
offs_t ram_limit = 0x100000 + m_ram->size() - 0x100000;
space.install_read_bank(0x100000, ram_limit - 1, "bank1");
space.install_write_bank(0x100000, ram_limit - 1, "bank1");
membank("bank1")->set_base(m_ram->pointer() + 0xa0000);
membank("bank1")->set_base(m_ram->pointer() + 0x100000);
}
}