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netlist: Macro-ized CD4006 DIPs

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This commit is contained in:
Aaron Giles 2020-08-02 12:38:26 +02:00 committed by couriersud
parent 5f991abda1
commit cdca99f353
5 changed files with 56 additions and 54 deletions
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1
src/lib/netlist/devices/net_lib.cpp
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@ -126,7 +126,6 @@ namespace devices
LIB_ENTRY(AM2847)
// FIXME: duplicate?
LIB_ENTRY(CD4006)
LIB_ENTRY(CD4006_dip)
LIB_ENTRY(CD4017)
LIB_ENTRY(CD4022)
LIB_ENTRY(CD4020_WI)

31
src/lib/netlist/devices/nld_4006.cpp
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@ -20,7 +20,7 @@ namespace netlist
NETLIB_CONSTRUCTOR_MODEL(CD4006, "CD4XXX")
, m_CLOCK(*this, "CLOCK", NETLIB_DELEGATE(inputs))
, m_I(*this, {"D1", "D2", "D3", "D4"}, NETLIB_DELEGATE(inputs))
, m_Q(*this, {"D1P4", "D1P4S", "D2P4", "D2P5", "D3P4", "D4P4", "D3P5"})
, m_Q(*this, {"D1P4", "D1P4S", "D2P4", "D2P5", "D3P4", "D4P4", "D4P5"})
, m_d(*this, "m_d", 0)
, m_last_clock(*this, "m_last_clock", 0)
, m_supply(*this)
@ -69,34 +69,7 @@ namespace netlist
nld_power_pins m_supply;
};
NETLIB_OBJECT(CD4006_dip)
{
NETLIB_CONSTRUCTOR(CD4006_dip)
, A(*this, "A")
{
register_subalias("1", A.m_I[0]);
register_subalias("2", A.m_Q[1]);
register_subalias("3", A.m_CLOCK);
register_subalias("4", A.m_I[1]);
register_subalias("5", A.m_I[2]);
register_subalias("6", A.m_I[3]);
register_subalias("7", "A.VSS");
register_subalias("8", A.m_Q[5]);
register_subalias("9", A.m_Q[6]);
register_subalias("10", A.m_Q[4]);
register_subalias("11", A.m_Q[2]);
register_subalias("12", A.m_Q[3]);
register_subalias("13", A.m_Q[0]);
register_subalias("14", "A.VDD");
}
private:
NETLIB_SUB(CD4006) A;
};
NETLIB_DEVICE_IMPL(CD4006, "CD4006", "+CLOCK,+D1,+D2,+D3,+D4,+D1P4,+D1P4S,+D2P4,+D2P5,+D3P4,+D4P4,+D3P5,@VCC,@GND")
NETLIB_DEVICE_IMPL(CD4006_dip, "CD4006_DIP", "")
NETLIB_DEVICE_IMPL(CD4006, "CD4006", "+CLOCK,+D1,+D2,+D3,+D4,+D1P4,+D1P4S,+D2P4,+D2P5,+D3P4,+D4P4,+D4P5,@VCC,@GND")
} //namespace devices
} // namespace netlist

8
src/lib/netlist/devices/nld_devinc.h
View File

@ -596,10 +596,6 @@
#define CD4006(...) \
NET_REGISTER_DEVEXT(CD4006, __VA_ARGS__)
// usage : CD4006_DIP(name)
#define CD4006_DIP(...) \
NET_REGISTER_DEVEXT(CD4006_DIP, __VA_ARGS__)
// ---------------------------------------------------------------------
// Source: src/lib/netlist/devices/nld_4017.cpp
// ---------------------------------------------------------------------
@ -1254,6 +1250,10 @@
#define CD4001_DIP(...) \
NET_REGISTER_DEVEXT(CD4001_DIP, __VA_ARGS__)
// usage : CD4006_DIP(name)
#define CD4006_DIP(...) \
NET_REGISTER_DEVEXT(CD4006_DIP, __VA_ARGS__)
// usage : CD4011_DIP(name)
#define CD4011_DIP(...) \
NET_REGISTER_DEVEXT(CD4011_DIP, __VA_ARGS__)

67
src/lib/netlist/macro/nlm_cd4xxx.cpp
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@ -39,6 +39,35 @@ static NETLIST_START(CD4001_DIP)
NETLIST_END()
/*
* CD4006: CMOS 18-Stage Static Register
*
* +--------------+
* D1 |1 ++ 14| VDD
* D1+4' |2 13| D1+4
* CLOCK |3 12| D2+5
* D2 |4 4006 11| D2+4
* D3 |5 10| D3+4
* D4 |6 9| D4+5
* VSS |7 8| D4+4
* +--------------+
*/
static NETLIST_START(CD4006_DIP)
CD4006(A)
DIPPINS( /* +--------------+ */
A.D1, /* D1 |1 ++ 14| VDD */ A.VDD,
A.D1P4S, /* D1+4' |2 13| D1+4 */ A.D1P4,
A.CLOCK, /* CLOCK |3 12| D2+5 */ A.D2P5,
A.D2, /* D2 |4 4006 11| D2+4 */ A.D2P4,
A.D3, /* D3 |5 10| D3+4 */ A.D3P4,
A.D4, /* D4 |6 9| D4+5 */ A.D4P5,
A.VSS, /* VSS |7 8| D4+4 */ A.D4P4
/* +--------------+ */
)
NETLIST_END()
/* CD4011: Quad 2-Input NAND Gates
*
* +--------------+
@ -51,31 +80,28 @@ NETLIST_END()
* VSS |7 8| E
* +--------------+
*
* Naming conventions follow National Semiconductor datasheet
*
* FIXME: Timing depends on VDD-VSS
* This needs a cmos d-a/a-d proxy implementation.
* Naming conventions follow National Semiconductor datashee
*/
static NETLIST_START(CD4011_DIP)
CD4011_GATE(A)
CD4011_GATE(B)
CD4011_GATE(C)
CD4011_GATE(D)
CD4011_GATE(A)
CD4011_GATE(B)
CD4011_GATE(C)
CD4011_GATE(D)
NET_C(A.VDD, B.VDD, C.VDD, D.VDD)
NET_C(A.VSS, B.VSS, C.VSS, D.VSS)
NET_C(A.VDD, B.VDD, C.VDD, D.VDD)
NET_C(A.VSS, B.VSS, C.VSS, D.VSS)
DIPPINS( /* +--------------+ */
A.A, /* A |1 ++ 14| VDD */ A.VDD,
A.B, /* B |2 13| H */ D.B,
A.Q, /* J |3 12| G */ D.A,
B.Q, /* K |4 4011 11| M */ D.Q,
B.A, /* C |5 10| L */ C.Q,
B.B, /* D |6 9| F */ C.B,
A.VSS,/* VSS |7 8| E */ C.A
/* +--------------+ */
)
DIPPINS( /* +--------------+ */
A.A, /* A |1 ++ 14| VDD */ A.VDD,
A.B, /* B |2 13| H */ D.B,
A.Q, /* J |3 12| G */ D.A,
B.Q, /* K |4 4011 11| M */ D.Q,
B.A, /* C |5 10| L */ C.Q,
B.B, /* D |6 9| F */ C.B,
A.VSS, /* VSS |7 8| E */ C.A
/* +--------------+ */
)
NETLIST_END()
/* CD4013: Dual Positive-Edge-Triggered D Flip-Flops
@ -569,6 +595,7 @@ NETLIST_START(CD4XXX_lib)
LOCAL_LIB_ENTRY(CD4070_DIP)
/* DIP ONLY */
LOCAL_LIB_ENTRY(CD4006_DIP)
LOCAL_LIB_ENTRY(CD4013_DIP)
LOCAL_LIB_ENTRY(CD4017_DIP)
LOCAL_LIB_ENTRY(CD4022_DIP)

3
src/lib/netlist/macro/nlm_cd4xxx.h
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@ -58,6 +58,9 @@
* DIP only macros
* ---------------------------------------------------------------------------*/
#define CD4006_DIP(name) \
NET_REGISTER_DEV(CD4006_DIP, name)
#define CD4013_DIP(name) \
NET_REGISTER_DEV(CD4013_DIP, name)